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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
7e43140e
Commit
7e43140e
authored
Sep 21, 2012
by
Tomasz Wlostowski
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hdl/top: new top level with Etherbone and SDB support
parent
3e8e0ae4
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3 changed files
with
130 additions
and
279 deletions
+130
-279
Manifest.py
hdl/top/spec/wr/Manifest.py
+4
-3
spec_top.ucf
hdl/top/spec/wr/spec_top.ucf
+1
-9
spec_top.vhd
hdl/top/spec/wr/spec_top.vhd
+125
-267
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hdl/top/spec/wr/Manifest.py
View file @
7e43140e
files
=
[
"spec_top.vhd"
,
"spec_top.ucf"
,
"spec_serial_dac.vhd"
,
"spec_serial_dac_arb.vhd"
]
files
=
[
"spec_top.vhd"
,
"spec_top.ucf"
,
"spec_serial_dac.vhd"
,
"spec_serial_dac_arb.vhd"
,
"spec_reset_gen.vhd"
]
fetchto
=
"../../../ip_cores"
modules
=
{
"local"
:
[
"../../../rtl"
,
"../../../platform"
,
"mini_bone"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/wr-cores.git::wishbonized"
],
"local"
:
[
"../../../rtl"
,
"../../../platform"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/wr-cores.git"
,
"git://ohwr.org/hdl-core-lib/etherbone-core.git"
],
"svn"
:
[
"http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl"
]
}
hdl/top/spec/wr/spec_top.ucf
View file @
7e43140e
...
...
@@ -363,13 +363,7 @@ TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
PIN "U_GTP/U_Rbclk_bufg_ch1.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09
NET "U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = U_GTP/ch0_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fd_clk_ref_n_i" TNM_NET = fd_clk_ref_n_i;
TIMESPEC TS_fd_clk_ref_n_i = PERIOD "fd_clk_ref_n_i" 8 ns HIGH 50%;
...
...
@@ -382,8 +376,6 @@ TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
TIMESPEC ts_ignore_crossclock = FROM "clk_sys" TO "fd_clk_ref_p_i" 10ns DATAPATHONLY;
TIMESPEC ts_ignore_crossclock2 = FROM "fd_clk_ref_p_i" TO "clk_sys" 10ns DATAPATHONLY;
#bank 0
#PIN "U_GTP/gen2.refbufg_ch1.O" CLOCK_DEDICATED_ROUTE = FALSE;
#PIN "U_GTP/gen2.refbufg_ch1.O" CLOCK_DEDICATED_ROUTE = FALSE;
#gennum
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
...
...
hdl/top/spec/wr/spec_top.vhd
View file @
7e43140e
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