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FMC DEL 1ns 4cha
Commit 7dea47db authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/rtl/fd_delay_line_arbiter.vhd: rewritten for faster arbitration to never miss 600 ns deadline 

The commit also adds possibility of wiring the channel driver 0 and ACAM data valid strobes/state indication
to the front panel LEMO connectors on the SVEC carrier, for the purpose of debugging ACAM/output stage processing latency.
parent c2353fcd
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hdl/rtl/fd_delay_channel_driver.vhd
View file @ 7dea47db
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2012-06-01 -- Last update: 2014-03-24
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -100,7 +100,9 @@ entity fd_delay_channel_driver is ...@@ -100,7 +100,9 @@ entity fd_delay_channel_driver is
-- WB Interface (pipelined, byte-aligned) -- WB Interface (pipelined, byte-aligned)
wb_i : in t_wishbone_slave_in; wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out wb_o : out t_wishbone_slave_out;
dbg_o : out std_logic_vector(7 downto 0)
); );
end fd_delay_channel_driver; end fd_delay_channel_driver;
...@@ -191,69 +193,9 @@ architecture behavioral of fd_delay_channel_driver is ...@@ -191,69 +193,9 @@ architecture behavioral of fd_delay_channel_driver is
signal regs_in : t_fd_channel_out_registers; signal regs_in : t_fd_channel_out_registers;
signal regs_out : t_fd_channel_in_registers; signal regs_out : t_fd_channel_in_registers;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
begin begin
gen_chipscope : if(g_index = 0) generate
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_ref_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
-- chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
TRIG0(0) <= regs_in.dcr_mode_o;
TRIG0(1) <= regs_in.dcr_enable_o;
TRIG0(2) <= regs_in.dcr_update_o;
TRIG0(3) <= pending_update;
TRIG0(4) <= first_pulse_till_hit;
TRIG0(5) <= first_pulse;
TRIG0(6) <= tag_valid_i;
TRIG0(7) <= mode_int;
TRIG0(8) <= hit_start;
TRIG0(9) <= hit_end;
TRIG0(10) <= mode_int;
TRIG0(11) <= '1' when state = IDLE else '0';
TRIG0(12) <= '1' when state = WAIT_ARB_START else '0';
TRIG0(14) <= '1' when state = WAIT_START_PULSE else '0';
TRIG0(15) <= '1' when state = WAIT_ARB_END else '0';
TRIG0(16) <= '1' when state = WAIT_PULSE_END else '0';
TRIG0(17) <= '1' when state = COUNT_DOWN else '0';
trig0(18) <= csync_p1_i;
TRIG1(27 downto 0) <= tag_coarse_i;
trig2(27 downto 0) <= tb_cntr.c;
trig3(27 downto 0) <= csync_coarse_i;
end generate gen_chipscope;
U_WB_Slave : fd_channel_wb_slave U_WB_Slave : fd_channel_wb_slave
port map ( port map (
rst_n_i => rst_n_sys_i, rst_n_i => rst_n_sys_i,
...@@ -518,16 +460,18 @@ begin ...@@ -518,16 +460,18 @@ begin
end if; end if;
when WAIT_ARB_START => when WAIT_ARB_START =>
delay_load_o <= '0';
if(delay_load_done_i = '1') then if(delay_load_done_i = '1') then
state <= WAIT_START_PULSE; state <= WAIT_START_PULSE;
first_pulse <= '0'; first_pulse <= '0';
delay_load_o <= '0';
end if; end if;
when WAIT_ARB_START_CP => when WAIT_ARB_START_CP =>
delay_load_o <= '0';
if(delay_load_done_i = '1') then if(delay_load_done_i = '1') then
state <= IDLE; state <= IDLE;
delay_load_o <= '0';
end if; end if;
when WAIT_START_PULSE => when WAIT_START_PULSE =>
...@@ -551,10 +495,10 @@ begin ...@@ -551,10 +495,10 @@ begin
when WAIT_ARB_END => when WAIT_ARB_END =>
delay_pulse0_o <= '1'; delay_pulse0_o <= '1';
delay_pulse1_o <= '1'; delay_pulse1_o <= '1';
delay_load_o <= '0';
if(delay_load_done_i = '1') then if(delay_load_done_i = '1') then
state <= WAIT_PULSE_END; state <= WAIT_PULSE_END;
delay_load_o <= '0';
end if; end if;
when WAIT_PULSE_END => when WAIT_PULSE_END =>
...@@ -594,6 +538,9 @@ begin ...@@ -594,6 +538,9 @@ begin
end if; end if;
end process; end process;
dbg_o(0) <= '1' when state = WAIT_ARB_START else '0';
dbg_o(1) <= '1' when state = WAIT_START_PULSE else '0';
pstart_utc_o <= pstart.u; pstart_utc_o <= pstart.u;
pstart_coarse_o <= pstart.c; pstart_coarse_o <= pstart.c;
pstart_frac_o <= pstart.f; pstart_frac_o <= pstart.f;
......
hdl/rtl/fd_delay_line_arbiter.vhd
View file @ 7dea47db
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2013-02-21 -- Last update: 2014-03-24
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -70,15 +70,15 @@ entity fd_delay_line_arbiter is ...@@ -70,15 +70,15 @@ entity fd_delay_line_arbiter is
end fd_delay_line_arbiter; end fd_delay_line_arbiter;
architecture behavioral of fd_delay_line_arbiter is architecture behavioral of fd_delay_line_arbiter is
signal arb_sreg : std_logic_vector(4*4 - 1 downto 0);
type t_dly_array is array (integer range <>) of std_logic_vector(9 downto 0); type t_dly_array is array (integer range <>) of std_logic_vector(9 downto 0);
signal done_reg : std_logic_vector(3 downto 0); signal cntr : unsigned(1 downto 0);
signal delay_vec : t_dly_array(0 to 3); signal delay_vec : t_dly_array(0 to 3);
signal delay_len_reg : std_logic_vector(3 downto 0); signal delay_len_reg : std_logic_vector(3 downto 0);
signal delay_val_reg : std_logic_vector(9 downto 0); signal delay_val_reg : std_logic_vector(9 downto 0);
signal pending_reg : std_logic_vector(3 downto 0); signal pending_req : std_logic_vector(3 downto 0);
begin -- behavioral begin -- behavioral
...@@ -87,47 +87,76 @@ begin -- behavioral ...@@ -87,47 +87,76 @@ begin -- behavioral
delay_vec(2) <= delay_val2_i; delay_vec(2) <= delay_val2_i;
delay_vec(3) <= delay_val3_i; delay_vec(3) <= delay_val3_i;
p_arb_counter : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
cntr <= (others => '0');
else
cntr <= cntr + 1;
end if;
end if;
end process;
p_arbitrate : process(clk_ref_i) p_req_done : process(clk_ref_i)
begin begin
if rising_edge(clk_ref_i) then if rising_edge(clk_ref_i) then
if rst_n_i = '0' then if rst_n_i = '0' then
delay_len_reg <= (others => '1'); pending_req <= (others => '0');
delay_val_reg <= (others => '0');
delay_len_o <= (others => '1');
-- done_reg <= (others => '0');
done_o <= (others => '0'); done_o <= (others => '0');
arb_sreg <= std_logic_vector(to_unsigned(1, arb_sreg'length));
pending_reg <= (others => '0');
else else
arb_sreg <= arb_sreg(arb_sreg'left-1 downto 0) & arb_sreg(arb_sreg'left);
for i in 0 to 3 loop for i in 0 to 3 loop
if load_i(i) = '1' then
if(arb_sreg(4*i) = '1' and load_i(i) = '1') then pending_req(i) <= '1';
delay_val_reg <= delay_vec(i);
pending_reg(i) <= '1';
delay_len_reg(i) <= '1';
done_o(i) <= '0';
elsif(arb_sreg(4*i+1) = '1') then
delay_len_reg(i) <= not pending_reg(i);
done_o(i) <= '0';
elsif(arb_sreg(4*i+2) = '1') then
delay_len_reg(i) <= not pending_reg(i);
done_o(i) <= '0'; done_o(i) <= '0';
elsif(arb_sreg(4*i+3) = '1') then elsif (cntr = i) then
delay_len_reg(i) <= '1'; pending_req(i) <= '0';
done_o(i) <= pending_reg(i); done_o(i) <= pending_req(i);
pending_reg(i) <= '0';
else else
done_o(i) <= '0'; done_o(i) <= '0';
end if; end if;
end loop;
end if;
end if;
end process;
p_drive_delays : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_i = '0' then
delay_len_reg <= (others => '0');
delay_val_reg <= (others => '0');
else
delay_val_reg <= delay_vec(to_integer (cntr));
for i in 0 to 3 loop
if(cntr = i) then
delay_len_reg (i) <= not pending_req(i);
else
delay_len_reg (i) <= '1';
end if;
end loop; -- i
end if;
end if;
end process;
end loop; -- i in 0 to 3
delay_len_o <= delay_len_reg; p_reg_outputs : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
delay_val_o <= delay_val_reg; delay_val_o <= delay_val_reg;
end if; end if;
end process;
p_reg_len : process(clk_ref_i)
begin
-- we latch the LEN signal on the falling edge, so the L->H transition (which
-- latches the delay word in the '295 gets right in the middle of the data
-- window.
if falling_edge(clk_ref_i) then
delay_len_o <= delay_len_reg;
end if; end if;
end process; end process;
......
hdl/rtl/fine_delay_core.vhd
View file @ 7dea47db
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2012-11-23 -- Last update: 2014-03-24
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -63,7 +63,9 @@ entity fine_delay_core is ...@@ -63,7 +63,9 @@ entity fine_delay_core is
-- Wishbone slave settings -- Wishbone slave settings
g_interface_mode : t_wishbone_interface_mode := PIPELINED; g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_debug_output : boolean := false
); );
port ( port (
...@@ -233,7 +235,9 @@ entity fine_delay_core is ...@@ -233,7 +235,9 @@ entity fine_delay_core is
outx_seconds_i : in std_logic_vector(40 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 40 * 4); outx_seconds_i : in std_logic_vector(40 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 40 * 4);
outx_cycles_i : in std_logic_vector(28 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 28 * 4); outx_cycles_i : in std_logic_vector(28 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 28 * 4);
outx_frac_i : in std_logic_vector(12 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 12 * 4); outx_frac_i : in std_logic_vector(12 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 12 * 4);
outx_valid_i : in std_logic_vector(3 downto 0) := x"0" outx_valid_i : in std_logic_vector(3 downto 0) := x"0";
dbg_o : out std_logic_vector(7 downto 0)
); );
end fine_delay_core; end fine_delay_core;
...@@ -303,6 +307,7 @@ architecture rtl of fine_delay_core is ...@@ -303,6 +307,7 @@ architecture rtl of fine_delay_core is
load : std_logic; load : std_logic;
load_done : std_logic; load_done : std_logic;
tag : t_fd_timestamp; tag : t_fd_timestamp;
dbg : std_logic_vector(7 downto 0);
end record; end record;
type t_delay_channel_array is array (integer range <>) of t_delay_channel; type t_delay_channel_array is array (integer range <>) of t_delay_channel;
...@@ -329,7 +334,7 @@ architecture rtl of fine_delay_core is ...@@ -329,7 +334,7 @@ architecture rtl of fine_delay_core is
signal owr_en_int : std_logic_vector(0 downto 0); signal owr_en_int : std_logic_vector(0 downto 0);
signal owr_int : std_logic_vector(0 downto 0); signal owr_int : std_logic_vector(0 downto 0);
signal dbg : std_logic_vector(3 downto 0); signal dbg_acam : std_logic_vector(3 downto 0);
signal gen_cal_pulse : std_logic_vector(3 downto 0); signal gen_cal_pulse : std_logic_vector(3 downto 0);
signal cal_pulse_mask : std_logic_vector(3 downto 0); signal cal_pulse_mask : std_logic_vector(3 downto 0);
...@@ -536,7 +541,7 @@ begin -- rtl ...@@ -536,7 +541,7 @@ begin -- rtl
regs_i => regs_fromwb, regs_i => regs_fromwb,
regs_o => regs_towb_tsu, regs_o => regs_towb_tsu,
dbg_o => dbg); dbg_o => dbg_acam);
rbuf_mux_ts(0).u <= tag_utc; rbuf_mux_ts(0).u <= tag_utc;
rbuf_mux_ts(0).c <= tag_coarse; rbuf_mux_ts(0).c <= tag_coarse;
...@@ -680,7 +685,8 @@ begin -- rtl ...@@ -680,7 +685,8 @@ begin -- rtl
delay_idle_o => channels(i).idle, delay_idle_o => channels(i).idle,
delay_load_done_i => channels(i).load_done, delay_load_done_i => channels(i).load_done,
wb_i => cnx_out(i+1), wb_i => cnx_out(i+1),
wb_o => cnx_in(i+1)); wb_o => cnx_in(i+1),
dbg_o => channels(i).dbg);
chx_delay_idle(i) <= channels(i).idle; chx_delay_idle(i) <= channels(i).idle;
...@@ -814,4 +820,23 @@ begin -- rtl ...@@ -814,4 +820,23 @@ begin -- rtl
spi_cs_dac_n_o <= spi_cs_dac_n; spi_cs_dac_n_o <= spi_cs_dac_n;
spi_cs_pll_n_o <= spi_cs_pll_n; spi_cs_pll_n_o <= spi_cs_pll_n;
gen_with_dbg_out : if(g_with_debug_output) generate
process(clk_ref_0_i)
begin
if rising_edge(clk_ref_0_i) then
dbg_o(0) <= dbg_acam(1); -- trig_d(2)
dbg_o(1) <= dbg_acam(2); -- acam tag valid
dbg_o(2) <= channels(0).dbg(0); -- out0 ARB_START
dbg_o(3) <= channels(0).dbg(1); -- out0 WAIT_START
end if;
end process;
end generate gen_with_dbg_out;
gen_without_dbg_out : if(not g_with_debug_output) generate
dbg_o <= (others => '0');
end generate gen_without_dbg_out;
end rtl; end rtl;
hdl/rtl/fine_delay_pkg.vhd
View file @ 7dea47db
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2013-04-30 -- Last update: 2014-03-24
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -305,7 +305,8 @@ package fine_delay_pkg is ...@@ -305,7 +305,8 @@ package fine_delay_pkg is
delay_load_done_i : in std_logic; delay_load_done_i : in std_logic;
delay_idle_o : out std_logic; delay_idle_o : out std_logic;
wb_i : in t_wishbone_slave_in; wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out); wb_o : out t_wishbone_slave_out;
dbg_o : out std_logic_vector(7 downto 0));
end component; end component;
component fd_dmtd_insertion_calibrator component fd_dmtd_insertion_calibrator
...@@ -452,7 +453,9 @@ package fine_delay_pkg is ...@@ -452,7 +453,9 @@ package fine_delay_pkg is
outx_seconds_i : in std_logic_vector(40 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 40 * 4); outx_seconds_i : in std_logic_vector(40 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 40 * 4);
outx_cycles_i : in std_logic_vector(28 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 28 * 4); outx_cycles_i : in std_logic_vector(28 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 28 * 4);
outx_frac_i : in std_logic_vector(12 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 12 * 4); outx_frac_i : in std_logic_vector(12 * 4 - 1 downto 0) := f_gen_dummy_vec('0', 12 * 4);
outx_valid_i : in std_logic_vector(3 downto 0) := x"0"); outx_valid_i : in std_logic_vector(3 downto 0) := x"0";
dbg_o : out std_logic_vector(7 downto 0));
end component; end component;
function f_to_internal_time ( function f_to_internal_time (
......
hdl/syn/svec/svec_fine_delay.xise
View file @ 7dea47db
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/top/svec/svec_top.ucf
View file @ 7dea47db
...@@ -325,6 +325,27 @@ NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33"; ...@@ -325,6 +325,27 @@ NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" LOC = AF28; NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33"; NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
NET "fp_gpio1_a2b_o" LOC=R29;
NET "fp_gpio1_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio2_a2b_o" LOC=T30;
NET "fp_gpio2_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio34_a2b_o" LOC=V28;
NET "fp_gpio34_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio1_b" LOC=R30;
NET "fp_gpio1_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio2_b" LOC=T28;
NET "fp_gpio2_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio3_b" LOC=U29;
NET "fp_gpio3_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio4_b" LOC=V27;
NET "fp_gpio4_b" IOSTANDARD="LVCMOS33";
#---------------------------------------- #----------------------------------------
# UART # UART
#---------------------------------------- #----------------------------------------
......
hdl/top/svec/svec_top.vhd
View file @ 7dea47db
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-24 -- Created : 2011-08-24
-- Last update: 2014-03-18 -- Last update: 2014-03-24
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -85,6 +85,15 @@ entity svec_top is ...@@ -85,6 +85,15 @@ entity svec_top is
fp_led_line_o : out std_logic_vector(1 downto 0); fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0); fp_led_column_o : out std_logic_vector(3 downto 0);
fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic;
fp_gpio34_a2b_o : out std_logic;
fp_gpio1_b : out std_logic;
fp_gpio2_b : out std_logic;
fp_gpio3_b : out std_logic;
fp_gpio4_b : out std_logic;
------------------------------------------------------------------------- -------------------------------------------------------------------------
-- VME Interface pins -- VME Interface pins
------------------------------------------------------------------------- -------------------------------------------------------------------------
...@@ -478,6 +487,8 @@ architecture rtl of svec_top is ...@@ -478,6 +487,8 @@ architecture rtl of svec_top is
signal led_act : std_logic; signal led_act : std_logic;
signal vme_access : std_logic; signal vme_access : std_logic;
signal fd0_dbg : std_logic_vector(7 downto 0);
begin begin
p_powerup_reset : process(clk_sys) p_powerup_reset : process(clk_sys)
...@@ -988,7 +999,8 @@ begin ...@@ -988,7 +999,8 @@ begin
wb_we_i => cnx_master_out(c_SLAVE_FD0).we, wb_we_i => cnx_master_out(c_SLAVE_FD0).we,
wb_ack_o => cnx_master_in(c_SLAVE_FD0).ack, wb_ack_o => cnx_master_in(c_SLAVE_FD0).ack,
wb_stall_o => cnx_master_in(c_SLAVE_FD0).stall, wb_stall_o => cnx_master_in(c_SLAVE_FD0).stall,
wb_irq_o => fd0_irq); wb_irq_o => fd0_irq,
dbg_o => fd0_dbg);
cnx_master_in(c_SLAVE_FD0).err <= '0'; cnx_master_in(c_SLAVE_FD0).err <= '0';
cnx_master_in(c_SLAVE_FD0).rty <= '0'; cnx_master_in(c_SLAVE_FD0).rty <= '0';
...@@ -1135,7 +1147,7 @@ begin ...@@ -1135,7 +1147,7 @@ begin
line_oen_o => fp_led_line_oen_o line_oen_o => fp_led_line_oen_o
); );
U_Drive_VME_Access_Led: gc_extend_pulse U_Drive_VME_Access_Led : gc_extend_pulse
generic map ( generic map (
g_width => 5000000) g_width => 5000000)
port map ( port map (
...@@ -1144,7 +1156,7 @@ begin ...@@ -1144,7 +1156,7 @@ begin
pulse_i => cnx_slave_in(c_MASTER_VME).cyc, pulse_i => cnx_slave_in(c_MASTER_VME).cyc,
extended_o => vme_access); extended_o => vme_access);
U_Drive_PPS: gc_extend_pulse U_Drive_PPS : gc_extend_pulse
generic map ( generic map (
g_width => 5000000) g_width => 5000000)
port map ( port map (
...@@ -1189,6 +1201,19 @@ begin ...@@ -1189,6 +1201,19 @@ begin
-- The SFP is permanently enabled. -- The SFP is permanently enabled.
sfp_tx_disable_o <= '0'; sfp_tx_disable_o <= '0';
-- Debug signals assignments (FP lemos)
fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1';
fp_gpio34_a2b_o <= '1';
fp_gpio1_b <= fd0_dbg(0);
fp_gpio2_b <= fd0_dbg(1);
fp_gpio3_b <= fd0_dbg(2);
fp_gpio4_b <= fd0_dbg(3);
end rtl; end rtl;
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