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FMC DEL 1ns 4cha
Commit 7d858b70 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: improvements in IODELAY handling logic

parent dccd3b7c
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Showing with 86 additions and 32 deletions
hdl/rtl/fine_delay_core.vhd
View file @ 7d858b70
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2019-10-22
-- Last update: 2020-05-26
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -215,6 +215,7 @@ entity fine_delay_core is
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
idelay_busy_i : in std_logic;
---------------------------------------------------------------------------
......@@ -307,7 +308,7 @@ architecture rtl of fine_delay_core is
signal rst_n_sys, rst_n_ref : std_logic;
signal tsbcr_read_ack, fid_read_ack : std_logic;
signal irq_rbuf, irq_spll, irq_sync : std_logic;
signal irq_rbuf, irq_sync : std_logic;
type t_delay_channel is record
idle : std_logic;
......@@ -369,10 +370,13 @@ architecture rtl of fine_delay_core is
signal iodelay_ntaps : std_logic_vector(5 downto 0);
signal iodelay_cnt : unsigned(5 downto 0);
signal iodelay_div : unsigned(4 downto 0);
signal iodelay_div : unsigned(6 downto 0);
signal iodelay_tick : std_logic;
signal iodelay_cal_done : std_logic;
signal iodelay_cal_in_progress : std_logic;
signal iodelay_n_taps_load_refclk_p : std_logic;
signal iodelay_busy_synced: std_logic;
signal iodelay_latch_reset : std_logic;
begin -- rtl
U_WB_Adapter : wb_slave_adapter
......@@ -857,10 +861,42 @@ begin -- rtl
dbg_o <= (others => '0');
end generate gen_without_dbg_out;
p_handle_iodelay: process(clk_sys_i)
U_Sync_Busy : gc_sync_ffs
port map
(
clk_i => clk_ref_0_i,
rst_n_i => rst_n_ref,
data_i => idelay_busy_i,
synced_o => iodelay_busy_synced
);
U_Sync_taps_load: gc_pulse_synchronizer2
port map (
clk_in_i => clk_sys_i,
rst_in_n_i => rst_n_sys,
clk_out_i => clk_ref_0_i,
rst_out_n_i => rst_n_ref,
d_ready_o => open,
d_ack_p_o => open,
d_p_i => regs_fromwb.iodelay_adj_n_taps_load_o,
q_p_o => iodelay_n_taps_load_refclk_p);
p_latch_ntaps : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if regs_fromwb.iodelay_adj_n_taps_load_o = '1' then
iodelay_ntaps <= regs_fromwb.iodelay_adj_n_taps_o;
end if;
end if;
end process;
p_handle_iodelay: process(clk_ref_0_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys = '0' then
if rising_edge(clk_ref_0_i) then
if rst_n_ref = '0' then
idelay_cal_o <= '0';
idelay_inc_o <= '1';
idelay_rst_o <= '0';
......@@ -873,44 +909,38 @@ begin -- rtl
if iodelay_cal_done = '0' then
idelay_cal_o <= '1';
iodelay_cnt <= iodelay_cnt + 1;
if iodelay_cnt = 15 then
iodelay_cnt <= (others => '0');
iodelay_cal_done <= '1';
end if;
iodelay_cal_done <= '1';
else
idelay_cal_o <= '0';
end if;
iodelay_div <= iodelay_div + 1;
if iodelay_div = 0 then
iodelay_tick <= '1';
else
iodelay_tick <= '0';
end if;
if regs_fromwb.iodelay_adj_n_taps_load_o = '1' then
iodelay_cnt <= unsigned(regs_fromwb.iodelay_adj_n_taps_o);
idelay_rst_o <= '1';
iodelay_ntaps <= regs_fromwb.iodelay_adj_n_taps_o;
else
idelay_rst_o <= '0';
if iodelay_n_taps_load_refclk_p = '1' then
iodelay_cnt <= unsigned(iodelay_ntaps);
iodelay_latch_reset <= '1';
end if;
if iodelay_cal_done = '1' and iodelay_tick = '1' and iodelay_cnt /= 0 then
idelay_ce_o <= '1';
idelay_rst_o <= iodelay_latch_reset;
idelay_ce_o <= not iodelay_latch_reset;
iodelay_latch_reset <= '0';
iodelay_cnt <= iodelay_cnt - 1;
else
idelay_ce_o <= '0';
idelay_rst_o <= '0';
end if;
end if;
end if;
end process;
end process;
regs_towb_local.iodelay_adj_n_taps_i <= iodelay_ntaps;
......
hdl/top/spec/spec_fine_delay_top.vhd
View file @ 7d858b70
......@@ -175,7 +175,16 @@ entity spec_fine_delay_top is
fmc0_prsnt_m2c_n_i : in std_logic;
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic);
fmc0_sda_b : inout std_logic
-- synthesis translate_off
;
sim_wb_i : in t_wishbone_slave_in;
sim_wb_o : out t_wishbone_slave_out
-- synthesis translate_on
);
end entity spec_fine_delay_top;
......@@ -272,9 +281,8 @@ architecture arch of spec_fine_delay_top is
signal fmc0_wb_ddr_out : t_wishbone_master_data64_out;
-- Interrupts and status
signal ddr_wr_fifo_empty : std_logic;
signal fmc0_irq : std_logic;
signal irq_vector : std_logic_vector(4 downto 0);
signal irq_vector : std_logic_vector(0 downto 0);
signal gn4124_access : std_logic;
......@@ -296,7 +304,8 @@ architecture arch of spec_fine_delay_top is
signal fmc0_tdc_start_iodelay_inc : std_logic;
signal fmc0_tdc_start_iodelay_rst : std_logic;
signal fmc0_tdc_start_iodelay_cal : std_logic;
signal fmc0_tdc_start_iodelay_ce : std_logic;
signal fmc0_tdc_start_iodelay_ce : std_logic;
signal fmc0_tdc_start_iodelay_busy : std_logic;
begin -- architecture arch
......@@ -322,14 +331,16 @@ begin -- architecture arch
g_WITH_WR => TRUE,
g_WITH_DDR => FALSE,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 5,
g_NUM_USER_IRQ => 1,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 1,
g_FABRIC_IFACE => plain,
g_SIMULATION => f_int2bool(g_SIMULATION))
g_SIMULATION => f_int2bool(g_SIMULATION),
g_sim_bypass_gennum => true)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_aux_i(0) => fmc0_dcm_clk_ref_0,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
......@@ -395,11 +406,22 @@ begin -- architecture arch
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr,
pps_p_o => open,
pps_led_o => pps_led,
link_ok_o => wrabbit_en,
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM)
-- synthesis translate_off
,
sim_wb_i => sim_wb_i,
sim_wb_o => sim_wb_o
-- synthesis translate_on
);
------------------------------------------------------------------------------
-- Primary wishbone crossbar
......@@ -462,7 +484,8 @@ begin -- architecture arch
INC => fmc0_tdc_start_iodelay_inc,
CE => fmc0_tdc_start_iodelay_ce,
RST => fmc0_tdc_start_iodelay_rst,
CLK => clk_sys_62m5,
CLK => fmc0_dcm_clk_ref_0,
BUSY => fmc0_tdc_start_iodelay_busy,
ODATAIN => '0',
CAL => fmc0_tdc_start_iodelay_cal,
T => '1',
......@@ -504,6 +527,7 @@ begin -- architecture arch
idelay_rst_o => fmc0_tdc_start_iodelay_rst,
idelay_ce_o => fmc0_tdc_start_iodelay_ce,
idelay_inc_o => fmc0_tdc_start_iodelay_inc,
idelay_busy_i => fmc0_tdc_start_iodelay_busy,
trig_a_i => fmc0_fd_trig_a_i,
tdc_cal_pulse_o => fmc0_fd_tdc_cal_pulse_o,
......
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