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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
7b9803b4
Commit
7b9803b4
authored
May 16, 2012
by
Tomasz Wlostowski
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latest snapshot of the test program
parent
55c507d1
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3 changed files
with
9 additions
and
7 deletions
+9
-7
fdelay_lib.c
software/lib/fdelay_lib.c
+3
-1
fdelay_pps_demo.c
software/lib/fdelay_pps_demo.c
+4
-4
fdelay_lib.py
software/python/fdelay_lib.py
+2
-2
No files found.
software/lib/fdelay_lib.c
View file @
7b9803b4
...
...
@@ -1278,7 +1278,9 @@ int fdelay_configure_pulse_gen(fdelay_device_t *dev, int channel, int enable, fd
int
fdelay_channel_triggered
(
fdelay_device_t
*
dev
,
int
channel
)
{
fd_decl_private
(
dev
)
return
chan_readl
(
FD_REG_DCR
)
&
FD_DCR_PG_TRIG
?
1
:
0
;
uint32_t
dcr
=
chan_readl
(
FD_REG_DCR
);
printf
(
"DCR%d %x
\n
"
,
channel
,
dcr
);
return
dcr
&
FD_DCR_PG_TRIG
?
1
:
0
;
}
/* Todo: write get_time() */
...
...
software/lib/fdelay_pps_demo.c
View file @
7b9803b4
...
...
@@ -17,14 +17,14 @@ main(int argc, char *argv[])
printf
(
"Current Time: %lld:%d
\n
"
,
t_cur
.
utc
,
t_cur
.
coarse
);
t_start
.
coarse
=
t_cur
.
coarse
;
t_start
.
utc
=
t_cur
.
utc
+
1
;
t_start
.
coarse
=
0
;
//
t_cur.coarse;
t_start
.
utc
=
t_cur
.
utc
+
2
;
t_start
.
frac
=
0
;
fdelay_configure_pulse_gen
(
&
dev
,
1
,
1
,
t_start
,
48000LL
,
100000LL
,
-
1
);
/* Output 1, period = 100 ns, width = 48 ns - a bit asymmetric 10 MHz */
fdelay_configure_pulse_gen
(
&
dev
,
2
,
1
,
t_start
,
48000
LL
,
1000000000000LL
,
-
1
);
/* Output 2: period = 1 second, width = 48 ns - PPS signal */
fdelay_configure_pulse_gen
(
&
dev
,
2
,
1
,
t_start
,
1000000000000LL
/
2
LL
,
1000000000000LL
,
-
1
);
/* Output 2: period = 1 second, width = 48 ns - PPS signal */
while
(
!
fdelay_channel_triggered
(
&
dev
,
1
)
||
fdelay_channel_triggered
(
&
dev
,
2
))
while
(
!
fdelay_channel_triggered
(
&
dev
,
1
)
||
!
fdelay_channel_triggered
(
&
dev
,
2
))
usleep
(
10000
);
/* wait until both outputs have triggered*/
;
return
0
;
}
software/python/fdelay_lib.py
View file @
7b9803b4
...
...
@@ -23,7 +23,7 @@ class fd_timestamp(Structure):
class
FineDelay
:
BASE_ADDR
=
0x8
4
000
BASE_ADDR
=
0x8
0
000
FREE_RUNNING
=
0x10
WR_OFFLINE
=
0x8
...
...
@@ -39,7 +39,7 @@ class FineDelay:
self
.
handle
=
c_voidp
(
self
.
fdelay
.
fdelay_create_rawrabbit
(
c_int
(
fd
),
c_ulong
(
self
.
BASE_ADDR
)));
if
(
c_int
(
self
.
fdelay
.
fdelay_load_firmware
(
"
spec_top
.bin"
))
<
0
):
if
(
c_int
(
self
.
fdelay
.
fdelay_load_firmware
(
"
../spec_top_wr
.bin"
))
<
0
):
print
(
"Firmware loader failed..."
);
sys
.
exit
(
-
1
)
...
...
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