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FMC DEL 1ns 4cha
Commit 6df354ae authored by Federico Vaga's avatar Federico Vaga
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Merge branch '8-review-vaibhav-changes' into 'master' 

Resolve "review vaibhav changes"

Closes #8

See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!1
parents 3df0b32d e7c0e506
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Showing with 2058 additions and 6267 deletions
.gitlab-ci.yml 0 → 100644
View file @ 6df354ae
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
variables:
GIT_SUBMODULE_STRATEGY: normal
include:
- project: 'be-cem-edl/evergreen/gitlab-ci'
ref: master
file:
- 'edl-gitlab-ci.yml'
cppcheck:
stage: analyse
image:
name: gitlab-registry.cern.ch/coht/common-containers/static-analysis:latest
script:
- make -C software cppcheck
flawfinder:
stage: analyse
image:
name: gitlab-registry.cern.ch/coht/common-containers/static-analysis:latest
script:
- make -C software/tools flawfinder
documentation:
stage: build
image:
name: gitlab-registry.cern.ch/coht/common-containers/documentation:latest
script:
- make -C doc html
- mkdir -p $EDL_CI_EOS_OUTPUT_DIR
- cp -a doc/_build/html/* $EDL_CI_EOS_OUTPUT_DIR
artifacts:
paths:
- $EDL_CI_EOS_OUTPUT_DIR
.script_fetch_kernel_dep: &script_fetch_kernel_dep
- git clone -b v1.1.5 --depth 1 https://ohwr.org/project/fmc-sw.git ~/git/fmc
- export FMC=~/git/fmc
- git clone -b v1.4.4 --depth 1 https://ohwr.org/project/zio.git ~/git/zio
- export ZIO=~/git/zio
.script_build_kernel_dep: &script_build_kernel_dep
- make -C $FMC/drivers/fmc all
- make -C $ZIO/drivers/zio all
build-centos-7:
stage: build
variables:
KERNELSRC: /usr/src/kernels/*/
image:
name: gitlab-registry.cern.ch/coht/common-containers/build-centos-7:latest
before_script:
- *script_fetch_kernel_dep
- *script_build_kernel_dep
script:
- export KERNELSRC=/usr/src/kernels/*/
- make -C software
build-kernel:
stage: build
allow_failure: true
image:
name: gitlab-registry.cern.ch/coht/common-containers/build-kernel:latest
parallel:
matrix:
- VERSION: [5.10.149, 5.15.74]
before_script:
- *script_fetch_kernel_dep
script:
- source /linux-versions.sh
- fetch $VERSION && prepare $VERSION && export KERNELSRC=$(linux $VERSION)
- *script_build_kernel_dep
- make -C software/kernel all
.gitmodules
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = https://ohwr.org/project/general-cores.git
......@@ -19,6 +23,3 @@
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
[submodule "software/zio"]
path = software/zio
url = git://ohwr.org/misc/zio.git
.reuse/dep5 0 → 100644
View file @ 6df354ae
Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
Upstream-Name: fmc-adc-100m14b4ch
Upstream-Contact: Federico Vaga <federico.vaga@cern.ch>
Source: https://ohwr.org/project/fmc-delay-1ns-8cha
Files: doc/*
Copyright: 2022 CERN (home.cern)
License: CC-BY-SA-4.0+
Files: hardware/*
Copyright: 2022 CERN (home.cern)
License: CERN-OHL-W-2.0+
CHANGELOG.rst
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.. SPDX-License-Identifier: CC-BY-SA-4.0+
..
SPDX-License-Identifier: CC-0.0
SPDX-FileCopyrightText: 2019 CERN
.. SPDX-FileCopyrightText: 2019 CERN
=========
Changelog
......
LICENSES/CC-BY-SA-4.0.txt 0 → 100644
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LICENSES/CERN-OHL-W-2.0.txt 0 → 100644
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LICENSES/LICENSE.GPL-2_0 → LICENSES/GPL-2.0-or-later.txt
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GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
Copyright (C) 1989, 1991 Free Software Foundation, Inc., <http://fsf.org/>
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
......@@ -290,8 +290,8 @@ to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
spec-fmc-carrier
Copyright (C) 2019 CERN (https://home.cern)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
......@@ -329,7 +329,7 @@ necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
{signature of Ty Coon}, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
......
LICENSES/LGPL-2.1-or-later.txt 0 → 100644
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This diff is collapsed.
Manifest.py
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
modules = {
"local" : [
"hdl/rtl",
......
README.md
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<!--
SPDX-FileCopyrightText: 2022 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0+
-->
This repo contains the full source code (hardware + gateware + software) for the FmcDelay1ns4cha FMC module.
\ No newline at end of file
software/doc/.gitignore → doc/.gitignore
View file @ 6df354ae
......@@ -14,3 +14,6 @@ fine-delay.pdf
*.tp
/*.txt
*.vr
_build
.doxystamp
doxygen-fd-output
software/doc/software/Makefile → doc/Makefile
View file @ 6df354ae
......@@ -3,7 +3,7 @@
# You can set these variables from the command line, and also
# from the environment for the first two.
SPHINXOPTS ?=
SPHINXOPTS = -Drelease=$(shell git describe) -Dversion=$(shell git describe | cut -d "-" -f 1 | tr -d "v")
SPHINXBUILD ?= sphinx-build
SOURCEDIR = .
BUILDDIR = _build
......@@ -17,28 +17,5 @@ help:
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
$(MAKE) -C drawings
$(MAKE) doxygen TARGET=$@
@$(MAKE) -f Makefile.dependencies $@
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
GIT_VERSION = $(shell git describe --dirty --long --tags)
GIT_VERSION = $(shell git describe --dirty --long --tags)
doxygen:
ifeq ($(TARGET),clean)
@rm -rf doxygen-fd-output .doxystamp
else
$(MAKE) .doxystamp
endif
# List of Doxygen folders to consider
DOXINPUT := ../../lib
DOXINPUT += ../../kernel/fine-delay.h
DOXEXCL := ../../lib/PyFmcFineDelay
# List of actual Doxygen source files
DOXSRC = $(shell find $(DOXINPUT) -type f -name '*.[chS]')
.doxystamp: $(DOXSRC)
GIT_VERSION=$(GIT_VERSION) DOXINPUT="$(DOXINPUT)" DOXEXCL="$(DOXEXCL)" doxygen ./doxygen-fd-config
@touch .doxystamp
doc/Makefile.dependencies 0 → 100644
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+
TOP_DIR := $(shell pwd)/..
SW_DIR := $(TOP_DIR)/software
DOXY_OUT := doxygen-fd-output
all: doxygen drawings
GIT_VERSION = $(shell git describe --dirty --long --tags)
DOXINPUT := $(SW_DIR)/lib
DOXINPUT += $(SW_DIR)/kernel/fine-delay.h
DOXEXCL := $(SW_DIR)/lib/PyFmcFineDelay
doxygen: $(DOXY_OUT)
$(DOXY_OUT): doxygen-fd-config
GIT_VERSION=$(GIT_VERSION) DOXINPUT="$(DOXINPUT)" DOXEXCL="$(DOXEXCL)" doxygen $<
drawings:
$(MAKE) -C $@
clean:
$(MAKE) -C drawings $@
@rm -rf $(DOXY_OUT)
# Whatever sphinx target
%: all
@echo > /dev/null
.PHONY: all clean doxygen drawings
software/doc/software/doxygen-fd-config → doc/doxygen-fd-config
View file @ 6df354ae
# SPDX-License-Identifier: CC0-1.0
# SPDX-License-Identifier: CC-BY-SA-4.0+
#
# SPDX-FileCopyrightText: 2020 CERN
......
software/doc/software/drawings/Makefile → doc/drawings/Makefile
View file @ 6df354ae
......@@ -8,6 +8,6 @@ clean:
images: $(EPSIMAGES:.eps=.png)
%.png: %.eps
@convert $< $@
@inkscape $< -o $@ || inkscape --without-gui $< -A $@
.PHONY: all clean images
software/doc/software/installation.rst → doc/installation.rst
View file @ 6df354ae
......@@ -59,7 +59,7 @@ To install this software package, you need to tell it where your
kernel sources live, so the package can pick the right header files.
You need to set only one environment variable:
LINUX
KERNELSRC
The top-level directory of the Linux kernel you are compiling
against. If not set, the default may work if you compile in the same
host where you expect to run the driver.
......@@ -69,7 +69,7 @@ Most likely, this is all you need to set. After this, you can
run:::
make
sudo make install LINUX=$LINUX
sudo make install KERNELSRC=$KERNELSRC
After installation, your carrier driver should load automatically
(for example, the PCI bus will load ``spec-fmc-carrier.ko``), but
......
software/doc/software/troubleshooting.rst → doc/troubleshooting.rst
View file @ 6df354ae
......@@ -13,11 +13,11 @@ directory or fail with an error like:::
make: \*\*\* /lib/modules/3.10/build: No such file or directory.
This happens when you compiled by setting ``LINUX=`` and your
This happens when you compiled by setting ``KERNELSRC=`` and your
*sudo* is not propagating the environment to its child processes.
In this case, you should run this command instead::
sudo make modules_install LINUX=$LINUX
sudo make modules_install KERNELSRC=$KERNELSRC
Version Mismatch
================
......
hdl/.gitignore
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
*.*\#
\#*
.\#*
......
hdl/Manifest.py
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
modules = {"local" : ["platform", "rtl"] }
\ No newline at end of file
hdl/include/acam_model.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`timescale 1ps/1ps
......
hdl/include/ideal_timestamper.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`include "timestamp.svh"
module ideal_timestamper
......
hdl/include/jittery_delay.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`timescale 10fs/10fs
module jittery_delay
......
hdl/include/mc100ep195.vh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`timescale 1ps/1ps
module mc100ep195
......
hdl/include/random_pulse_gen.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
module random_pulse_gen
(
input enable_i,
......
hdl/include/regs/fd_channel_regs.vh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`define ADDR_FD_DCR 6'h0
`define FD_DCR_ENABLE_OFFSET 0
`define FD_DCR_ENABLE 32'h00000001
......
hdl/include/regs/fd_main_regs.vh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`define ADDR_FD_RSTR 8'h0
`define FD_RSTR_RST_FMC_OFFSET 0
`define FD_RSTR_RST_FMC 32'h00000001
......
hdl/include/timestamp.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`ifndef __TIMESTAMP_SVH
`define __TIMESTAMP_SVH
......
hdl/include/tunable_clock_gen.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`timescale 10fs/10fs
module tunable_clock_gen
......
hdl/include/vme64x_bfm/components/sn74vmeh22501.v
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`timescale 1ns/1ns
module sn74vmeh22501 (
......
hdl/include/vme64x_bfm/svec_vme_buffers.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`include "components/sn74vmeh22501.v"
`include "vme64x_bfm.svh"
......
hdl/include/vme64x_bfm/vme64x_bfm.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`ifndef __VME64X_BFM_SVH
`define __VME64X_BFM_SVH 1
......
hdl/platform/Manifest.py
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
files =["chipscope_icon.ngc", "chipscope_ila.ngc", "fd_ddr_driver.vhd", "fd_ddr_pll.vhd" ]
hdl/platform/fd_ddr_driver.vhd
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : Xilinx DDR driver
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/platform/fd_ddr_pll.vhd
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-- file: clk_wiz_v3_2.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
......
hdl/rtl/Manifest.py
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
files = ["fd_acam_timestamper.vhd",
"fd_ring_buffer.vhd",
"fd_ts_adder.vhd",
......
hdl/rtl/build_wb.sh
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#!/bin/bash
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
wbgen2 -V fd_main_wishbone_slave.vhd -H record -p fd_main_wbgen2_pkg.vhd -K ../include/regs/fd_main_regs.vh -s defines -C fd_main_regs.h -f texinfo -D ../../doc/design-notes/fd_main_regs.in fd_main_wishbone_slave.wb
wbgen2 -V fd_channel_wishbone_slave.vhd -H record -p fd_channel_wbgen2_pkg.vhd -K ../include/regs/fd_channel_regs.vh -s defines -C fd_channel_regs.h -f texinfo -D ../../doc/design-notes/fd_channel_regs.in fd_channel_wishbone_slave.wb
\ No newline at end of file
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : ACAM TDX-GPX timestamp postprocessor
-- Project : Fine Delay Core (FmcDelay1ns4cha)
......
hdl/rtl/fd_acam_timestamper.vhd
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : ACAM TDC-GPX Timestamper
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Fine Delay Channel WB Slave
---------------------------------------------------------------------------------------
......
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Fine Delay Channel WB Slave
---------------------------------------------------------------------------------------
......
hdl/rtl/fd_channel_wishbone_slave.wb
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
......
hdl/rtl/fd_csync_generator.vhd
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-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : Counter Sync signal generator
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_delay_channel_driver.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : Precise Programmable Pulse Generator (single channel)
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_delay_line_arbiter.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-----------------------------------------------------------------------------
-- Title : SY89295U 4-input arbitration unit
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_dmtd_insertion_calibrator.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : DMTD-based insertion delay calibrator
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_dmtd_with_deglitcher.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : Digital DMTD Edge Tagger
-- Project : White Rabbit
......
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Fine Delay Main WB Slave
---------------------------------------------------------------------------------------
......
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Fine Delay Main WB Slave
---------------------------------------------------------------------------------------
......
hdl/rtl/fd_main_wishbone_slave.wb
View file @ 6df354ae
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
......
hdl/rtl/fd_reset_generator.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-----------------------------------------------------------------------------
-- Title : Reset unit.
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_ring_buffer.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : Timestamp Ring Buffer
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_spi_dac_arbiter.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-----------------------------------------------------------------------------
-- Title : SPI Bus Master with arbitration
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_spi_master.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-----------------------------------------------------------------------------
-- Title : SPI Bus Master
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_timestamper_stat_unit.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-----------------------------------------------------------------------------
-- Title : TDC Statistics Unit
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fd_ts_adder.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : Pipelined timestamp adder with normalization
-- Project : Fine Delay Core (FmcDelay1ns4cha)
......
hdl/rtl/fine_delay_core.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : Fine Delay VHDL Core (top level block)
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/fine_delay_pkg.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : Fine Delay VHDL Core (main package)
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
......
hdl/rtl/timing/fd_dmtd_with_deglitcher.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : Digital DMTD Edge Tagger
-- Project : White Rabbit
......
hdl/rtl/timing/fd_hpll_period_detect.vhd
View file @ 6df354ae
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : DMTD Helper PLL (HPLL) - linear frequency/period detector.
-- Project : White Rabbit Switch
......
hdl/syn/spec/Manifest.py
View file @ 6df354ae
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
target = "xilinx"
action = "synthesis"
......
hdl/syn/svec/Manifest.py
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
board = "svec"
target = "xilinx"
action = "synthesis"
......
hdl/testbench/adder_test/Manifest.py
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
action = "simulation"
vlog_opt="+incdir+../../include"
......
hdl/testbench/adder_test/main.sv
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
//#`include "simdrv_defs.svh"
`timescale 1ns/1ps
......
hdl/testbench/adder_test/run.do
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
make
vsim -L XilinxCoreLib work.main -voptargs="+acc"
......
hdl/testbench/old_top/Manifest.py
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
target = "xilinx"
action = "simulation"
......
hdl/testbench/old_top/main.sv
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`timescale 10fs/10fs
`include "acam_model.svh"
......
hdl/testbench/old_top/run.do
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#make
vsim -L XilinxCoreLib work.main -voptargs="+acc"
......
hdl/testbench/old_top/wave.do
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/chx_delay_pulse0
......
hdl/testbench/spec_wr_top/Manifest.py
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
ctrls = ["bank3_32b_32b"]
action = "simulation"
target = "xilinx"
......
hdl/testbench/spec_wr_top/main.sv
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`timescale 1ns/1ps
`include "simdrv_defs.svh"
......
hdl/testbench/spec_wr_top/run.do
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#vlog -sv main.sv +incdir+"." +incdir+gn4124_bfm +incdir+../../include/wb +incdir+../../include
#make -f Makefile
vsim -L unisim -L secureip work.main -voptargs="+acc" -t 10fs -novopt
......
hdl/testbench/spec_wr_top/simdrv_fine_delay.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`include "regs/fd_main_regs.vh"
`include "regs/fd_channel_regs.vh"
......
hdl/testbench/spec_wr_top/vhd_wishbone_master.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`ifndef __VHD_WISHBONE_MASTER_INCLUDED
`define __VHD_WISHBONE_MASTER_INCLUDED
......
hdl/testbench/spec_wr_top/wave.do
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_pllref_p_i
......
hdl/testbench/svec_wr_top/Manifest.py
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
ctrls = ["bank3_32b_32b"]
action = "simulation"
target = "xilinx"
......
hdl/testbench/svec_wr_top/fdelay_board.svh
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`timescale 10fs/10fs
`include "acam_model.svh"
......
hdl/testbench/svec_wr_top/main.sv
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// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
......
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