Commit 6c14330f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/rtl/fd_delay_channel_driver: force output to 1 when DCR.FORCE_HI bit set

parent ff2a679f
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-02-29
-- Last update: 2012-06-01
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -481,8 +481,8 @@ begin
delay_load_o <= '0';
first_pulse <= '1';
first_pulse_till_hit <= '0';
delay_pulse1_o <= '0';
delay_pulse0_o <= '0';
delay_pulse1_o <= regs_in.dcr_force_hi_o;
delay_pulse0_o <= regs_in.dcr_force_hi_o;
delay_idle_o <= '1';
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment