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FMC DEL 1ns 4cha
Commit 6192e6db authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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top/spec: SPEC top level compliant with The Convention

parent b29188b3
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hdl/top/spec/Manifest.py
View file @ 6192e6db
files = ["synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf", "spec_reset_gen.vhd"]
files = ["spec_top.vhd", "spec_top.ucf"]
fetchto = "../../ip_cores"
modules = {
"local" : ["../../rtl", "../../platform" ],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git" ]
"local" : [
"../../rtl",
"../../platform",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/gn4124-core",
"../../ip_cores/spec",
"../../ip_cores/ddr3-sp6-core"
]
}
hdl/top/spec/spec_reset_gen.vhd deleted 100644 → 0
View file @ b29188b3
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/top/spec/spec_top.ucf
View file @ 6192e6db
#bank 0
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_p_i" LOC = C11;
#####################################################################
### Gennum ports
#####################################################################
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
#####################################################################
### SPEC Generic Stuff
#####################################################################
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "fmc_scl_b" LOC = F7 ;
NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
#net "led_n_o[0]" loc=c20;
#net "led_n_o[0]" IOSTANDARD=LVCMOS18;
#net "led_n_o[1]" loc=F18;
#net "led_n_o[1]" IOSTANDARD=LVCMOS18;
#net "led_n_o[2]" loc=f20;
#net "led_n_o[2]" IOSTANDARD=LVCMOS18;
#net "led_n_o[3]" loc=G19;
#net "led_n_o[3]" IOSTANDARD=LVCMOS18;
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_PRSNT_M2C_L_i" LOC="AB14";
NET "sfp_rxp_i" LOC= D15;
NET "sfp_rxn_i" LOC= C15;
NET "sfp_txp_o" LOC= B16;
NET "sfp_txn_o" LOC= A16;
NET "SFP_MOD_DEF1_b" LOC = C17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_b" LOC = G16;
NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_b" LOC = H14;
NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_FAULT_i" LOC = A17;
NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_o" LOC = F17;
NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
###########################################################################
## Flash memory SPI interface
###########################################################################
NET "flash_ncs_o" LOC = AA3;
NET "flash_ncs_o" IOSTANDARD = "LVCMOS25";
NET "flash_sclk_o" LOC = Y20;
NET "flash_sclk_o" IOSTANDARD = "LVCMOS25";
NET "flash_mosi_o" LOC = AB20;
NET "flash_mosi_o" IOSTANDARD = "LVCMOS25";
NET "flash_miso_i" LOC = AA20;
NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
####################################################################################
# FineDelay V3/V4 pins
####################################################################################
NET "fd_clk_ref_n_i" LOC = L22 ;
NET "fd_clk_ref_n_i" IOSTANDARD =LVDS_25;
NET "fd_clk_ref_p_i" LOC = L20 ;
NET "fd_clk_ref_p_i" IOSTANDARD =LVDS_25;
NET "fd_delay_len_o[3]" LOC = W14 ;
NET "fd_delay_len_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[3]" SLEW = SLOW;
NET "fd_delay_len_o[3]" DRIVE = 4;
NET "fd_delay_len_o[2]" LOC = Y14 ;
NET "fd_delay_len_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[2]" SLEW = SLOW;
NET "fd_delay_len_o[2]" DRIVE = 4;
NET "fd_delay_len_o[1]" LOC = Y18 ;
NET "fd_delay_len_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[1]" SLEW = SLOW;
NET "fd_delay_len_o[1]" DRIVE = 4;
NET "fd_delay_len_o[0]" LOC = W17 ;
NET "fd_delay_len_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_len_o[0]" SLEW = SLOW;
NET "fd_delay_len_o[0]" DRIVE = 4;
NET "fd_delay_pulse_o[3]" LOC = W13 ;
NET "fd_delay_pulse_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[2]" LOC = V13 ;
NET "fd_delay_pulse_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[1]" LOC = U15 ;
NET "fd_delay_pulse_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_pulse_o[0]" LOC = T15 ;
NET "fd_delay_pulse_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[0]" LOC = A20 ;
NET "fd_delay_val_o[0]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[0]" SLEW = SLOW;
NET "fd_delay_val_o[0]" DRIVE = 4;
NET "fd_delay_val_o[1]" LOC = B20 ;
NET "fd_delay_val_o[1]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[1]" SLEW = SLOW;
NET "fd_delay_val_o[1]" DRIVE = 4;
NET "fd_delay_val_o[2]" LOC = A19 ;
NET "fd_delay_val_o[2]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[2]" SLEW = SLOW;
NET "fd_delay_val_o[2]" DRIVE = 4;
NET "fd_delay_val_o[3]" LOC = C19 ;
NET "fd_delay_val_o[3]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[3]" SLEW = SLOW;
NET "fd_delay_val_o[3]" DRIVE = 4;
NET "fd_delay_val_o[4]" LOC = W18 ;
NET "fd_delay_val_o[4]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[4]" SLEW = SLOW;
NET "fd_delay_val_o[4]" DRIVE = 4;
NET "fd_delay_val_o[5]" LOC = V17 ;
NET "fd_delay_val_o[5]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[5]" SLEW = SLOW;
NET "fd_delay_val_o[5]" DRIVE = 4;
NET "fd_delay_val_o[6]" LOC = C18 ;
NET "fd_delay_val_o[6]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[6]" SLEW = SLOW;
NET "fd_delay_val_o[6]" DRIVE = 4;
NET "fd_delay_val_o[7]" LOC = D17 ;
NET "fd_delay_val_o[7]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[7]" SLEW = SLOW;
NET "fd_delay_val_o[7]" DRIVE = 4;
NET "fd_delay_val_o[8]" LOC = W15 ;
NET "fd_delay_val_o[8]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[8]" SLEW = SLOW;
NET "fd_delay_val_o[8]" DRIVE = 4;
NET "fd_delay_val_o[9]" LOC = Y16 ;
NET "fd_delay_val_o[9]" IOSTANDARD =LVCMOS25;
NET "fd_delay_val_o[9]" SLEW = SLOW;
NET "fd_delay_val_o[9]" DRIVE = 4;
NET "fd_led_trig_o" LOC = V11 ;
NET "fd_led_trig_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_cs_dac_n_o" LOC = AB16 ;
NET "fd_spi_cs_dac_n_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_cs_gpio_n_o" LOC = R11 ;
NET "fd_spi_cs_gpio_n_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_cs_pll_n_o" LOC = AB17 ;
NET "fd_spi_cs_pll_n_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_miso_i" LOC = AB18 ;
NET "fd_spi_miso_i" IOSTANDARD =LVCMOS25;
NET "fd_spi_mosi_o" LOC = AA18 ;
NET "fd_spi_mosi_o" IOSTANDARD =LVCMOS25;
NET "fd_spi_sclk_o" LOC = Y17 ;
NET "fd_spi_sclk_o" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_clk_o" LOC = T12 ;
NET "fd_dmtd_clk_o" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_fb_out_i" LOC = U12 ;
NET "fd_dmtd_fb_out_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_cal_pulse_o" LOC = Y15 ;
NET "fd_tdc_cal_pulse_o" IOSTANDARD =LVCMOS25;
NET "fd_pll_status_i" LOC = AB15 ;
NET "fd_pll_status_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_alutrigger_o" LOC = W12 ;
NET "fd_tdc_alutrigger_o" IOSTANDARD =LVCMOS25;
NET "fd_ext_rst_n_o" LOC = T11 ;
NET "fd_ext_rst_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[0]" LOC = AB12 ;
NET "fd_tdc_d_b[0]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[1]" LOC = U8 ;
NET "fd_tdc_d_b[1]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[10]" LOC = R9 ;
NET "fd_tdc_d_b[10]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[11]" LOC = R8 ;
NET "fd_tdc_d_b[11]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[12]" LOC = AA6 ;
NET "fd_tdc_d_b[12]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[13]" LOC = AB6 ;
NET "fd_tdc_d_b[13]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[14]" LOC = U9 ;
NET "fd_tdc_d_b[14]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[15]" LOC = V9 ;
NET "fd_tdc_d_b[15]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[16]" LOC = Y7 ;
NET "fd_tdc_d_b[16]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[17]" LOC = AB7 ;
NET "fd_tdc_d_b[17]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[18]" LOC = AA8 ;
NET "fd_tdc_d_b[18]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[19]" LOC = AB8 ;
NET "fd_tdc_d_b[19]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[2]" LOC = AA12 ;
NET "fd_tdc_d_b[2]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[20]" LOC = T10 ;
NET "fd_tdc_d_b[20]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[21]" LOC = U10 ;
NET "fd_tdc_d_b[21]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[22]" LOC = W10 ;
NET "fd_tdc_d_b[22]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[23]" LOC = Y10 ;
NET "fd_tdc_d_b[23]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[24]" LOC = Y9 ;
NET "fd_tdc_d_b[24]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[25]" LOC = AB9 ;
NET "fd_tdc_d_b[25]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[26]" LOC = AA4 ;
NET "fd_tdc_d_b[26]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[27]" LOC = AB4 ;
NET "fd_tdc_d_b[27]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[3]" LOC = T8 ;
NET "fd_tdc_d_b[3]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[4]" LOC = W8 ;
NET "fd_tdc_d_b[4]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[5]" LOC = V7 ;
NET "fd_tdc_d_b[5]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[6]" LOC = Y6 ;
NET "fd_tdc_d_b[6]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[7]" LOC = W6 ;
NET "fd_tdc_d_b[7]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[8]" LOC = Y5 ;
NET "fd_tdc_d_b[8]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_d_b[9]" LOC = AB5 ;
NET "fd_tdc_d_b[9]" IOSTANDARD =LVCMOS25;
NET "fd_tdc_emptyf_i" LOC = Y12 ;
NET "fd_tdc_emptyf_i" IOSTANDARD =LVCMOS25;
NET "fd_tdc_oe_n_o" LOC = AA16 ;
NET "fd_tdc_oe_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_rd_n_o" LOC = AB13 ;
NET "fd_tdc_rd_n_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_start_dis_o" LOC = R13 ;
NET "fd_tdc_start_dis_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_start_n_i" LOC = F16 ;
NET "fd_tdc_start_n_i" IOSTANDARD =LVDS_25;
NET "fd_tdc_start_p_i" LOC = E16 ;
NET "fd_tdc_start_p_i" IOSTANDARD =LVDS_25;
NET "fd_tdc_stop_dis_o" LOC = T14 ;
NET "fd_tdc_stop_dis_o" IOSTANDARD =LVCMOS25;
NET "fd_tdc_wr_n_o" LOC = Y13 ;
NET "fd_tdc_wr_n_o" IOSTANDARD =LVCMOS25;
NET "fd_trig_a_i" LOC = Y11 ;
NET "fd_trig_a_i" IOSTANDARD =LVCMOS25;
NET "fd_dmtd_fb_in_i" LOC = AB11 ;
NET "fd_dmtd_fb_in_i" IOSTANDARD =LVCMOS25;
NET "fd_onewire_b" LOC = W11 ;
NET "fd_onewire_b" IOSTANDARD =LVCMOS25;
####################################################################################
# Misc
####################################################################################
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fd_clk_ref_n_i" TNM_NET = fd_clk_ref_n_i;
TIMESPEC TS_fd_clk_ref_n_i = PERIOD "fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fd_clk_ref_p_i" TNM_NET = fd_clk_ref_p_i;
TIMESPEC TS_fd_clk_ref_p_i = PERIOD "fd_clk_ref_p_i" 8 ns HIGH 50%;
NET "clk_sys" TNM_NET = clk_sys;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
PIN "U_DDR_PLL/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2014/08/01
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "fmc0_fd_clk_ref_n_i" LOC = L22 ;
NET "fmc0_fd_clk_ref_n_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_clk_ref_p_i" LOC = L20 ;
NET "fmc0_fd_clk_ref_p_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_delay_len_o[3]" LOC = W14 ;
NET "fmc0_fd_delay_len_o[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[2]" LOC = Y14 ;
NET "fmc0_fd_delay_len_o[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[1]" LOC = Y18 ;
NET "fmc0_fd_delay_len_o[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[0]" LOC = W17 ;
NET "fmc0_fd_delay_len_o[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_pulse_o[3]" LOC = W13 ;
NET "fmc0_fd_delay_pulse_o[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_pulse_o[2]" LOC = V13 ;
NET "fmc0_fd_delay_pulse_o[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_pulse_o[1]" LOC = U15 ;
NET "fmc0_fd_delay_pulse_o[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_pulse_o[0]" LOC = T15 ;
NET "fmc0_fd_delay_pulse_o[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[0]" LOC = A20 ;
NET "fmc0_fd_delay_val_o[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[1]" LOC = B20 ;
NET "fmc0_fd_delay_val_o[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[2]" LOC = A19 ;
NET "fmc0_fd_delay_val_o[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[3]" LOC = C19 ;
NET "fmc0_fd_delay_val_o[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[4]" LOC = W18 ;
NET "fmc0_fd_delay_val_o[4]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[5]" LOC = V17 ;
NET "fmc0_fd_delay_val_o[5]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[6]" LOC = C18 ;
NET "fmc0_fd_delay_val_o[6]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[7]" LOC = D17 ;
NET "fmc0_fd_delay_val_o[7]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[8]" LOC = W15 ;
NET "fmc0_fd_delay_val_o[8]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[9]" LOC = Y16 ;
NET "fmc0_fd_delay_val_o[9]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc0_fd_led_trig_o" LOC = V11 ;
NET "fmc0_fd_led_trig_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_cs_dac_n_o" LOC = AB16 ;
NET "fmc0_fd_spi_cs_dac_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_cs_gpio_n_o" LOC = R11 ;
NET "fmc0_fd_spi_cs_gpio_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_cs_pll_n_o" LOC = AB17 ;
NET "fmc0_fd_spi_cs_pll_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_miso_i" LOC = AB18 ;
NET "fmc0_fd_spi_miso_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_mosi_o" LOC = AA18 ;
NET "fmc0_fd_spi_mosi_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_spi_sclk_o" LOC = Y17 ;
NET "fmc0_fd_spi_sclk_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_dmtd_clk_o" LOC = T12 ;
NET "fmc0_fd_dmtd_clk_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_dmtd_fb_out_i" LOC = U12 ;
NET "fmc0_fd_dmtd_fb_out_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_cal_pulse_o" LOC = Y15 ;
NET "fmc0_fd_tdc_cal_pulse_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_pll_status_i" LOC = AB15 ;
NET "fmc0_fd_pll_status_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_alutrigger_o" LOC = W12 ;
NET "fmc0_fd_tdc_alutrigger_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_ext_rst_n_o" LOC = T11 ;
NET "fmc0_fd_ext_rst_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[0]" LOC = AB12 ;
NET "fmc0_fd_tdc_d_b[0]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[1]" LOC = U8 ;
NET "fmc0_fd_tdc_d_b[1]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[10]" LOC = R9 ;
NET "fmc0_fd_tdc_d_b[10]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[11]" LOC = R8 ;
NET "fmc0_fd_tdc_d_b[11]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[12]" LOC = AA6 ;
NET "fmc0_fd_tdc_d_b[12]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[13]" LOC = AB6 ;
NET "fmc0_fd_tdc_d_b[13]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[14]" LOC = U9 ;
NET "fmc0_fd_tdc_d_b[14]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[15]" LOC = V9 ;
NET "fmc0_fd_tdc_d_b[15]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[16]" LOC = Y7 ;
NET "fmc0_fd_tdc_d_b[16]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[17]" LOC = AB7 ;
NET "fmc0_fd_tdc_d_b[17]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[18]" LOC = AA8 ;
NET "fmc0_fd_tdc_d_b[18]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[19]" LOC = AB8 ;
NET "fmc0_fd_tdc_d_b[19]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[2]" LOC = AA12 ;
NET "fmc0_fd_tdc_d_b[2]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[20]" LOC = T10 ;
NET "fmc0_fd_tdc_d_b[20]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[21]" LOC = U10 ;
NET "fmc0_fd_tdc_d_b[21]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[22]" LOC = W10 ;
NET "fmc0_fd_tdc_d_b[22]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[23]" LOC = Y10 ;
NET "fmc0_fd_tdc_d_b[23]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[24]" LOC = Y9 ;
NET "fmc0_fd_tdc_d_b[24]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[25]" LOC = AB9 ;
NET "fmc0_fd_tdc_d_b[25]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[26]" LOC = AA4 ;
NET "fmc0_fd_tdc_d_b[26]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[27]" LOC = AB4 ;
NET "fmc0_fd_tdc_d_b[27]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[3]" LOC = T8 ;
NET "fmc0_fd_tdc_d_b[3]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[4]" LOC = W8 ;
NET "fmc0_fd_tdc_d_b[4]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[5]" LOC = V7 ;
NET "fmc0_fd_tdc_d_b[5]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[6]" LOC = Y6 ;
NET "fmc0_fd_tdc_d_b[6]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[7]" LOC = W6 ;
NET "fmc0_fd_tdc_d_b[7]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[8]" LOC = Y5 ;
NET "fmc0_fd_tdc_d_b[8]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_d_b[9]" LOC = AB5 ;
NET "fmc0_fd_tdc_d_b[9]" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_emptyf_i" LOC = Y12 ;
NET "fmc0_fd_tdc_emptyf_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_oe_n_o" LOC = AA16 ;
NET "fmc0_fd_tdc_oe_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_rd_n_o" LOC = AB13 ;
NET "fmc0_fd_tdc_rd_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_start_dis_o" LOC = R13 ;
NET "fmc0_fd_tdc_start_dis_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_start_n_i" LOC = F16 ;
NET "fmc0_fd_tdc_start_n_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_tdc_start_p_i" LOC = E16 ;
NET "fmc0_fd_tdc_start_p_i" IOSTANDARD =LVDS_25;
NET "fmc0_fd_tdc_stop_dis_o" LOC = T14 ;
NET "fmc0_fd_tdc_stop_dis_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_tdc_wr_n_o" LOC = Y13 ;
NET "fmc0_fd_tdc_wr_n_o" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_trig_a_i" LOC = Y11 ;
NET "fmc0_fd_trig_a_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_dmtd_fb_in_i" LOC = AB11 ;
NET "fmc0_fd_dmtd_fb_in_i" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_onewire_b" LOC = W11 ;
NET "fmc0_fd_onewire_b" IOSTANDARD =LVCMOS25;
NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
TIMESPEC TS_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fmc0_fd_clk_ref_p_i" TNM_NET = fmc0_fd_clk_ref_p_i;
TIMESPEC TS_fd_clk_ref_p_i = PERIOD "fmc0_fd_clk_ref_p_i" 8 ns HIGH 50%;
PIN "cmp0_fd_ddr_pll/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "cmp0_fd_ddr_pll/pll_base_inst/CLKOUT0" TNM_NET="fmc0_dcm_clk_ref_0";
TIMESPEC TS_crossdomain_4 = FROM "clk_sys_62m5" TO "fmc0_dcm_clk_ref_0" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_5 = FROM "fmc0_dcm_clk_ref_0" TO "clk_sys_62m5" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_9 = FROM "clk_ref_125m" TO "fmc0_dcm_clk_ref_0" 4ns DATAPATHONLY;
# TIMESPEC TS_crossdomain_1 = FROM "clk_sys" TO "clk_125m_pllref_BUFG" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_4 = FROM "clk_sys" TO "dcm_clk_ref_0" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_5 = FROM "dcm_clk_ref_0" TO "clk_sys" 4ns DATAPATHONLY;
# TIMESPEC TS_crossdomain_7 = FROM "clk_125m_pllref_BUFG" TO "clk_sys" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_9 = FROM "clk_125m_pllref_BUFG" TO "dcm_clk_ref_0" 4ns DATAPATHONLY;
NET "*/gc_sync_register_in[*]" MAXDELAY=4ns;
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
hdl/top/spec/spec_top.vhd
View file @ 6192e6db
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCI-Express FMC Carrier) top level
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : spec_top.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2014-03-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top level for the SPEC 1.1 (and later releases) cards with
-- one Fine Delay FMC.
-- Supports:
-- - SDB enumeration (SDB descriptor at 0x00000)
-- - White Rabbit and Etherbone
-- - Interrupts (via WR VIC)
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- Fine Delay Mezzanine (fmc-fine-delay)
-- https://ohwr.org/projects/fmc-delay-1ns-8cha
--------------------------------------------------------------------------------
--
-- Copyright (c) 2011 - 2014 CERN / BE-CO-HT
-- unit name: spec_top
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- description: Top entity for Fine Delay reference design.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- Top level design of the SPEC-based FMC Fine Delay.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
--------------------------------------------------------------------------------
-- Copyright CERN 2011-2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all;
--use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
generic
(
g_simulation : integer := 0
);
port
(
-------------------------------------------------------------------------
-- Standard SPEC ports (Gennum bridge, LEDS, Etc. Do not modify
-------------------------------------------------------------------------
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
l_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- gpio[1] -> gn4124 gpio9
-- pcie to local [inbound data] - rx
p2l_rdy : out std_logic; -- rx buffer full flag
p2l_clkn : in std_logic; -- receiver source synchronous clock-
p2l_clkp : in std_logic; -- receiver source synchronous clock+
p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
p2l_dframe : in std_logic; -- receive frame
p2l_valid : in std_logic; -- receive data valid
-- inbound buffer request/status
p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
rx_error : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
l2p_dframe : out std_logic; -- transmit data frame
l2p_valid : out std_logic; -- transmit data valid
l2p_clkn : out std_logic; -- transmitter source synchronous clock-
l2p_clkp : out std_logic; -- transmitter source synchronous clock+
l2p_edb : out std_logic; -- packet termination and discard
-- outbound buffer status
l2p_rdy : in std_logic; -- tx buffer full flag
l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
tx_error : in std_logic; -- transmit error
vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
-- font panel leds
led_red : out std_logic;
led_green : out std_logic;
-------------------------------------------------------------------------
-- PLL VCXO DAC Drive
-------------------------------------------------------------------------
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
--dac_clr_n_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic;
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
fmc_scl_b : inout std_logic := '1';
fmc_sda_b : inout std_logic := '1';
carrier_onewire_b : inout std_logic := '1';
fmc_prsnt_m2c_l_i : in std_logic;
-------------------------------------------------------------------------
-- SFP pins
-------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '1';
sfp_mod_def0_b : in std_logic; -- detect pin
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic := '0';
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
-------------------------------------------------------------------------
-- Flash memory pins
-------------------------------------------------------------------------
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_ncs_o : out std_logic;
flash_miso_i : in std_logic;
-------------------------------------------------------------------------
-- Fine Delay Pins
-------------------------------------------------------------------------
fd_tdc_start_p_i : in std_logic;
fd_tdc_start_n_i : in std_logic;
fd_clk_ref_p_i : in std_logic;
fd_clk_ref_n_i : in std_logic;
fd_trig_a_i : in std_logic;
fd_tdc_cal_pulse_o : out std_logic;
fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fd_tdc_emptyf_i : in std_logic;
fd_tdc_alutrigger_o : out std_logic;
fd_tdc_wr_n_o : out std_logic;
fd_tdc_rd_n_o : out std_logic;
fd_tdc_oe_n_o : out std_logic;
fd_led_trig_o : out std_logic;
fd_tdc_start_dis_o : out std_logic;
fd_tdc_stop_dis_o : out std_logic;
fd_spi_cs_dac_n_o : out std_logic;
fd_spi_cs_pll_n_o : out std_logic;
fd_spi_cs_gpio_n_o : out std_logic;
fd_spi_sclk_o : out std_logic;
fd_spi_mosi_o : out std_logic;
fd_spi_miso_i : in std_logic;
fd_delay_len_o : out std_logic_vector(3 downto 0);
fd_delay_val_o : out std_logic_vector(9 downto 0);
fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fd_dmtd_clk_o : out std_logic;
fd_dmtd_fb_in_i : in std_logic;
fd_dmtd_fb_out_i : in std_logic;
fd_pll_status_i : in std_logic;
fd_ext_rst_n_o : out std_logic;
fd_onewire_b : inout std_logic;
-----------------------------------------
-- UART
-----------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic
);
end spec_top;
architecture rtl of spec_top is
component spec_serial_dac_arb
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end component;
component fd_ddr_pll
port (
RST : in std_logic;
LOCKED : out std_logic;
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic);
end component;
component spec_reset_gen
generic (
g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts
-- to speed up simulations.
g_SIMULATION : integer := 0);
port (
-- Reset button
button1_n_i : in std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_cs_n_o : out std_logic; -- 25MHz VCXO
pll20dac_cs_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
-- Carrier front panel LEDs
led_act_o : out std_logic;
led_link_o : out std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0);
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
onewire_b : inout std_logic;
-- SFP
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
-- SPI
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := 'L';
-- UART
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
------------------------------------------
-- GN4124 interface
--
-- gn_gpio_b[1] -> AB19 -> GN4124 GPIO9
-- gn_gpio_b[0] -> U16 -> GN4124 GPIO8
------------------------------------------
gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic;
gn_p2l_clk_p_i : in std_logic;
gn_p2l_rdy_o : out std_logic;
gn_p2l_dframe_i : in std_logic;
gn_p2l_valid_i : in std_logic;
gn_p2l_data_i : in std_logic_vector(15 downto 0);
gn_p_wr_req_i : in std_logic_vector(1 downto 0);
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0);
gn_rx_error_o : out std_logic;
gn_l2p_clk_n_o : out std_logic;
gn_l2p_clk_p_o : out std_logic;
gn_l2p_dframe_o : out std_logic;
gn_l2p_valid_o : out std_logic;
gn_l2p_edb_o : out std_logic;
gn_l2p_data_o : out std_logic_vector(15 downto 0);
gn_l2p_rdy_i : in std_logic;
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0);
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0);
gn_tx_error_i : in std_logic;
gn_vc_rdy_i : in std_logic_vector(1 downto 0);
gn_gpio_b : inout std_logic_vector(1 downto 0);
------------------------------------------
-- FMC slots
------------------------------------------
fmc0_fd_tdc_start_p_i : in std_logic;
fmc0_fd_tdc_start_n_i : in std_logic;
fmc0_fd_clk_ref_p_i : in std_logic;
fmc0_fd_clk_ref_n_i : in std_logic;
fmc0_fd_trig_a_i : in std_logic;
fmc0_fd_tdc_cal_pulse_o : out std_logic;
fmc0_fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fmc0_fd_tdc_emptyf_i : in std_logic;
fmc0_fd_tdc_alutrigger_o : out std_logic;
fmc0_fd_tdc_wr_n_o : out std_logic;
fmc0_fd_tdc_rd_n_o : out std_logic;
fmc0_fd_tdc_oe_n_o : out std_logic;
fmc0_fd_led_trig_o : out std_logic;
fmc0_fd_tdc_start_dis_o : out std_logic;
fmc0_fd_tdc_stop_dis_o : out std_logic;
fmc0_fd_spi_cs_dac_n_o : out std_logic;
fmc0_fd_spi_cs_pll_n_o : out std_logic;
fmc0_fd_spi_cs_gpio_n_o : out std_logic;
fmc0_fd_spi_sclk_o : out std_logic;
fmc0_fd_spi_mosi_o : out std_logic;
fmc0_fd_spi_miso_i : in std_logic;
fmc0_fd_delay_len_o : out std_logic_vector(3 downto 0);
fmc0_fd_delay_val_o : out std_logic_vector(9 downto 0);
fmc0_fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fmc0_fd_dmtd_clk_o : out std_logic;
fmc0_fd_dmtd_fb_in_i : in std_logic;
fmc0_fd_dmtd_fb_out_i : in std_logic;
fmc0_fd_pll_status_i : in std_logic;
fmc0_fd_ext_rst_n_o : out std_logic;
fmc0_fd_onewire_b : inout std_logic;
-- FMC slot management
fmc0_prsnt_m2c_n_i : in std_logic;
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic);
end entity spec_top;
architecture arch of spec_top is
component IBUFDS is
generic (
CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE;
DQS_BIAS : string := "FALSE";
IBUF_DELAY_VALUE : string := "0";
IBUF_LOW_PWR : boolean := TRUE;
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
function f_resize_slv (x : std_logic_vector; len : integer) return std_logic_vector is
variable tmp : std_logic_vector(len-1 downto 0);
begin
if(len > x'length) then
tmp(x'length-1 downto 0) := x;
tmp(len-1 downto x'length) := (others => '0');
elsif(len < x'length) then
tmp := x(len-1 downto 0);
else
tmp := x;
end if;
return tmp;
end f_resize_slv;
function f_int2bool (x : integer) return boolean is
begin
if(x = 0) then
return false;
else
return true;
end if;
end f_int2bool;
constant c_NUM_WB_MASTERS : integer := 3;
constant c_NUM_WB_SLAVES : integer := 2;
constant c_MASTER_GENNUM : integer := 0;
constant c_MASTER_ETHERBONE : integer := 1;
constant c_SLAVE_FD : integer := 0;
constant c_SLAVE_WRCORE : integer := 1;
constant c_SLAVE_VIC : integer := 2;
constant c_DESC_SYNTHESIS : integer := 3;
constant c_DESC_REPO_URL : integer := 4;
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS+1 downto 0) :=
(c_SLAVE_WRCORE => f_sdb_embed_bridge(c_WRCORE_BRIDGE_SDB, x"000c0000"),
c_SLAVE_FD => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00080000"),
c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00090000"),
c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
c_DESC_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url));
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
(0 => x"00080000");
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_fb_dmtd : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_125m_gtp : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic_vector(0 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic_vector(0 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_loopen_vec : std_logic_vector(2 downto 0);
signal phy_rdy : std_logic;
signal local_reset_n : std_logic;
O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component IBUFDS;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters attached to the primary wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves attached to the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 2;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_GENNUM : integer := 0;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FMC_DELAY : integer := 1;
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FMC_DELAY => x"0001_0000");
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes
c_WB_SLAVE_FMC_DELAY => x"0003_0000"); -- 0x10000 bytes
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Clocks and resets
signal clk_dmtd_125m : std_logic;
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal dcm_clk_ref_0, dcm_clk_ref_180 : std_logic;
signal fd_tdc_start : std_logic;
signal tdc_data_out, tdc_data_in : std_logic_vector(27 downto 0);
signal tdc_data_oe : std_logic;
-- WRPC TM interface and status
signal tm_link_up : std_logic;
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal tm_clk_aux_lock_en : std_logic;
signal tm_clk_aux_locked : std_logic;
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr : std_logic;
signal tm_time_valid_sync : std_logic;
signal tm_clk_aux_lock_en : std_logic_vector(0 downto 0);
signal tm_clk_aux_locked : std_logic_vector(0 downto 0);
signal tm_dac_value : std_logic_vector( 23 downto 0);
signal tm_dac_wr : std_logic_vector(0 downto 0);
signal wrabbit_en : std_logic;
signal pps_led : std_logic;
signal ddr_pll_reset : std_logic;
signal ddr_pll_locked, fd_pll_status : std_logic;
-- Wishbone bus from cross-clocking module to FMC0 mezzanine
signal cnx_fmc0_sync_master_out : t_wishbone_master_out;
signal cnx_fmc0_sync_master_in : t_wishbone_master_in;
signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in : std_logic;
signal fd_scl_out, fd_scl_in, fd_sda_out, fd_sda_in : std_logic;
signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in : std_logic;
signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
signal fd_owr_en, fd_owr_in : std_logic;
signal fd_irq : std_logic;
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Wishbone buses from FMC ADC cores to DDR controller
signal fmc0_wb_ddr_in : t_wishbone_master_data64_in;
signal fmc0_wb_ddr_out : t_wishbone_master_data64_out;
signal pps : std_logic;
-- Interrupts and status
signal ddr_wr_fifo_empty : std_logic;
signal fmc0_irq : std_logic;
signal irq_vector : std_logic_vector(4 downto 0);
signal gn4124_access : std_logic;
signal etherbone_rst_n : std_logic;
signal etherbone_src_out : t_wrf_source_out;
signal etherbone_src_in : t_wrf_source_in;
signal etherbone_snk_out : t_wrf_sink_out;
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
signal vic_irqs : std_logic_vector(31 downto 0);
signal fmc0_fd_tdc_start : std_logic;
signal fmc0_ddr_pll_reset : std_logic;
signal fmc0_ddr_pll_locked: std_logic;
attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
attribute buffer_type of clk_125m_pllref : signal is "BUFG";
signal fmc0_dcm_clk_ref_0 : std_logic;
signal fmc0_dcm_clk_ref_180 : std_logic;
begin
signal fmc0_fd_pll_status : std_logic;
signal fmc0_tdc_data_out, fmc0_tdc_data_in : std_logic_vector(27 downto 0);
signal fmc0_tdc_data_oe : std_logic;
U_Reset_Generator : spec_reset_gen
port map (
clk_sys_i => clk_sys,
rst_pcie_n_a_i => l_rst_n,
rst_button_n_a_i => button1_i,
rst_n_o => local_reset_n);
signal fmc0_fd_owr_en : std_logic;
signal fmc0_fd_owr_in : std_logic;
begin -- architecture arch
U_Buf_CLK_PLL : IBUFGDS
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => true -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574E_cafe", -- WRTD Node (WN) 1
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
U_Buf_CLK_GTP : IBUFDS
inst_spec_template : entity work.spec_template_wr
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR => FALSE,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 5,
g_DPRAM_INITF => g_WRPC_INITF,
g_FABRIC_IFACE => plain,
g_SIMULATION => g_SIMULATION)
port map (
O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i
);
cmp_sys_clk_pll : PLL_BASE
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
rst_ref_125m_n_o => rst_ref_125m_n,
irq_user_i => irq_vector,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
pps_p_o => open,
pps_led_o => pps_led,
link_ok_o => wrabbit_en,
ddr_dma_clk_i => '0',
ddr_dma_rst_n_i => '0',
ddr_dma_wb_i => c_DUMMY_WB_SLAVE_D64_IN,
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
------------------------------------------------------------------------------
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_crossbar : xwb_crossbar
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
g_VERBOSE => FALSE,
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open, --pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
cmp_clk_dmtd_buf : BUFG
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
------------------------------------------------------------------------------
-- FMC Fine Delay mezzanine
------------------------------------------------------------------------------
cmp0_tm_time_valid_sync : gc_sync_ffs
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => tm_time_valid,
synced_o => tm_time_valid_sync);
cmp_clk_vcxo : BUFG
cmp0_fmc_irq_sync : gc_sync_ffs
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
-------------------------------------------------------------------------------
-- Gennum core
-------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => L_RST_N,
status_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
-- L2P Control
l2p_edb_o => L2P_EDB,
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => open,
dma_reg_clk_i => clk_sys,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => clk_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => '0',
dma_clk_i => clk_sys,
dma_ack_i => '1',
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0',
dma_dat_i => (others => '0'),
dma_int_i => '0',
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_cyc_i => '0',
dma_reg_we_i => '0'
);
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fmc0_irq,
synced_o => irq_vector(0));
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
-------------------------------------------------------------------------------
-- Top level interconnect and interrupt controller
-------------------------------------------------------------------------------
U_Intercon : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_VIC : xwb_vic
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => fd_irq,
irq_master_o => GPIO(0));
-------------------------------------------------------------------------------
-- White Rabbit Core + PHY
-------------------------------------------------------------------------------
-- Tristates for FMC EEPROM
fmc_scl_b <= '0' when (wrc_scl_out = '0' or fd_scl_out = '0') else 'Z';
fmc_sda_b <= '0' when (wrc_sda_out = '0' or fd_sda_out = '0') else 'Z';
wrc_scl_in <= fmc_scl_b;
wrc_sda_in <= fmc_sda_b;
fd_scl_in <= fmc_scl_b;
fd_sda_in <= fmc_sda_b;
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= carrier_onewire_b;
U_WR_CORE : xwr_core
generic map (
g_simulation => g_simulation,
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
g_aux_clks => 1,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false)
port map (
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
clk_aux_i(0) => dcm_clk_ref_0,
rst_n_i => local_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_loopen_vec_o => phy_loopen_vec,
phy_rdy_i => phy_rdy,
led_act_o => LED_RED,
led_link_o => LED_GREEN,
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
sda_o => wrc_sda_out,
sda_i => wrc_sda_in,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b,
spi_sclk_o => flash_sclk_o,
spi_ncs_o => flash_ncs_o,
spi_mosi_o => flash_mosi_o,
spi_miso_i => flash_miso_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in,
slave_i => cnx_master_out(c_SLAVE_WRCORE),
slave_o => cnx_master_in(c_SLAVE_WRCORE),
--aux_master_o => etherbone_cfg_in,
--aux_master_i => etherbone_cfg_out,
--wrf_src_o => etherbone_snk_in,
--wrf_src_i => etherbone_snk_out,
--wrf_snk_o => etherbone_src_in,
--wrf_snk_i => etherbone_src_out,
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o(0) => tm_dac_wr,
tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_utc,
tm_cycles_o => tm_cycles,
btn1_i => '0',
btn2_i => '0',
rst_aux_n_o => etherbone_rst_n,
pps_p_o => pps
);
U_GTP : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation,
g_enable_ch0 => 0,
g_enable_ch1 => 1)
port map (
gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_data_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k(0),
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k(0),
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => phy_loopen,
ch1_loopen_vec_i => phy_loopen_vec,
ch1_rdy_o => phy_rdy,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0',
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
--U_Etherbone : eb_slave_core
-- generic map (
-- g_sdb_address => f_resize_slv(c_sdb_address, 64))
-- port map (
-- clk_i => clk_sys,
-- nRst_i => etherbone_rst_n,
-- src_o => etherbone_src_out,
-- src_i => etherbone_src_in,
-- snk_o => etherbone_snk_out,
-- snk_i => etherbone_snk_in,
-- cfg_slave_o => etherbone_cfg_out,
-- cfg_slave_i => etherbone_cfg_in,
-- master_o => cnx_slave_in(c_MASTER_ETHERBONE),
-- master_i => cnx_slave_out(c_MASTER_ETHERBONE));
cnx_slave_in(c_MASTER_ETHERBONE).cyc <= '0';
U_DAC_ARB : spec_serial_dac_arb
generic map (
g_invert_sclk => false,
g_num_extra_bits => 8)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => dac_cs1_n_o,
dac_cs_n_o(1) => dac_cs2_n_o,
-- dac_clr_n_o => open,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
-- dac_clr_n_o <= '1';
sfp_tx_disable_o <= '0';
-------------------------------------------------------------------------------
-- FINE DELAY INSTANTIATION
-------------------------------------------------------------------------------
cmp_fd_tdc_start : IBUFDS
cmp0_fd_tdc_start : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => fd_tdc_start, -- Buffer output
I => fd_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
O => fmc0_fd_tdc_start, -- Buffer output
I => fmc0_fd_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fmc0_fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
U_DDR_PLL : fd_ddr_pll
cmp0_fd_ddr_pll : entity work.fd_ddr_pll
port map (
RST => ddr_pll_reset,
LOCKED => ddr_pll_locked,
CLK_IN1_P => fd_clk_ref_p_i,
CLK_IN1_N => fd_clk_ref_n_i,
CLK_OUT1 => dcm_clk_ref_0,
CLK_OUT2 => dcm_clk_ref_180);
ddr_pll_reset <= not fd_pll_status_i;
fd_pll_status <= fd_pll_status_i and ddr_pll_locked;
U_FineDelay_Core : fine_delay_core
RST => fmc0_ddr_pll_reset,
LOCKED => fmc0_ddr_pll_locked,
CLK_IN1_P => fmc0_fd_clk_ref_p_i,
CLK_IN1_N => fmc0_fd_clk_ref_n_i,
CLK_OUT1 => fmc0_dcm_clk_ref_0,
CLK_OUT2 => fmc0_dcm_clk_ref_180);
fmc0_ddr_pll_reset <= not fmc0_fd_pll_status_i;
fmc0_fd_pll_status <= fmc0_fd_pll_status_i and fmc0_ddr_pll_locked;
cmp0_fmc_fdelay_mezzanine : entity work.fine_delay_core
generic map (
g_with_wr_core => true,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
g_address_granularity => BYTE,
g_fmc_slot_id => 0)
port map (
clk_ref_0_i => dcm_clk_ref_0,
clk_ref_180_i => dcm_clk_ref_180,
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
rst_n_i => local_reset_n,
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
clk_ref_0_i => fmc0_dcm_clk_ref_0,
clk_ref_180_i => fmc0_dcm_clk_ref_180,
clk_dmtd_i => clk_dmtd_125m,
dcm_reset_o => open,
dcm_locked_i => ddr_pll_locked,
trig_a_i => fd_trig_a_i,
tdc_cal_pulse_o => fd_tdc_cal_pulse_o,
tdc_start_i => fd_tdc_start,
dmtd_fb_in_i => fd_dmtd_fb_in_i,
dmtd_fb_out_i => fd_dmtd_fb_out_i,
dmtd_samp_o => fd_dmtd_clk_o,
led_trig_o => fd_led_trig_o,
ext_rst_n_o => fd_ext_rst_n_o,
pll_status_i => fd_pll_status,
acam_d_o => tdc_data_out,
acam_d_i => tdc_data_in,
acam_d_oen_o => tdc_data_oe,
acam_emptyf_i => fd_tdc_emptyf_i,
acam_alutrigger_o => fd_tdc_alutrigger_o,
acam_wr_n_o => fd_tdc_wr_n_o,
acam_rd_n_o => fd_tdc_rd_n_o,
acam_start_dis_o => fd_tdc_start_dis_o,
acam_stop_dis_o => fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd_spi_cs_gpio_n_o,
spi_sclk_o => fd_spi_sclk_o,
spi_mosi_o => fd_spi_mosi_o,
spi_miso_i => fd_spi_miso_i,
delay_len_o => fd_delay_len_o,
delay_val_o => fd_delay_val_o,
delay_pulse_o => fd_delay_pulse_o,
dcm_locked_i => fmc0_ddr_pll_locked,
trig_a_i => fmc0_fd_trig_a_i,
tdc_cal_pulse_o => fmc0_fd_tdc_cal_pulse_o,
tdc_start_i => fmc0_fd_tdc_start,
dmtd_fb_in_i => fmc0_fd_dmtd_fb_in_i,
dmtd_fb_out_i => fmc0_fd_dmtd_fb_out_i,
dmtd_samp_o => fmc0_fd_dmtd_clk_o,
led_trig_o => fmc0_fd_led_trig_o,
ext_rst_n_o => fmc0_fd_ext_rst_n_o,
pll_status_i => fmc0_fd_pll_status,
acam_d_o => fmc0_tdc_data_out,
acam_d_i => fmc0_tdc_data_in,
acam_d_oen_o => fmc0_tdc_data_oe,
acam_emptyf_i => fmc0_fd_tdc_emptyf_i,
acam_alutrigger_o => fmc0_fd_tdc_alutrigger_o,
acam_wr_n_o => fmc0_fd_tdc_wr_n_o,
acam_rd_n_o => fmc0_fd_tdc_rd_n_o,
acam_start_dis_o => fmc0_fd_tdc_start_dis_o,
acam_stop_dis_o => fmc0_fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fmc0_fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fmc0_fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fmc0_fd_spi_cs_gpio_n_o,
spi_sclk_o => fmc0_fd_spi_sclk_o,
spi_mosi_o => fmc0_fd_spi_mosi_o,
spi_miso_i => fmc0_fd_spi_miso_i,
delay_len_o => fmc0_fd_delay_len_o,
delay_val_o => fmc0_fd_delay_val_o,
delay_pulse_o => fmc0_fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_utc,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en,
tm_clk_aux_locked_i => tm_clk_aux_locked,
tm_utc_i => tm_tai, -- fixme - it's really TAI, not utc. Fix
-- in the FD core
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_i => tm_clk_aux_locked(0),
tm_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the
-- WRCore
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr,
tm_dac_wr_i => tm_dac_wr(0),
owr_en_o => fmc0_fd_owr_en,
owr_i => fmc0_fd_owr_in,
-- i2c now from spec template
i2c_scl_oen_o => open,
i2c_scl_i => '1',
i2c_sda_oen_o => open,
i2c_sda_i => '1',
fmc_present_n_i => fmc0_prsnt_m2c_n_i,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).adr,
wb_dat_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_FMC_DELAY).dat,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).sel,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).cyc,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_FMC_DELAY).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_FMC_DELAY).ack,
wb_stall_o => cnx_slave_out(c_WB_SLAVE_FMC_DELAY).stall,
wb_irq_o => fmc0_irq
);
cnx_slave_out(c_WB_SLAVE_FMC_DELAY).rty <= '0';
cnx_slave_out(c_WB_SLAVE_FMC_DELAY).err <= '0';
owr_en_o => fd_owr_en,
owr_i => fd_owr_in,
i2c_scl_oen_o => fd_scl_out,
i2c_scl_i => fd_scl_in,
i2c_sda_oen_o => fd_sda_out,
i2c_sda_i => fd_sda_in,
fmc_present_n_i => fmc_prsnt_m2c_l_i,
wb_adr_i => cnx_master_out(c_SLAVE_FD).adr,
wb_dat_i => cnx_master_out(c_SLAVE_FD).dat,
wb_dat_o => cnx_master_in(c_SLAVE_FD).dat,
wb_sel_i => cnx_master_out(c_SLAVE_FD).sel,
wb_cyc_i => cnx_master_out(c_SLAVE_FD).cyc,
wb_stb_i => cnx_master_out(c_SLAVE_FD).stb,
wb_we_i => cnx_master_out(c_SLAVE_FD).we,
wb_ack_o => cnx_master_in(c_SLAVE_FD).ack,
wb_stall_o => cnx_master_in(c_SLAVE_FD).stall,
wb_irq_o => fd_irq);
fmc0_fd_tdc_d_b <= fmc0_tdc_data_out when fmc0_tdc_data_oe = '1' else (others => 'Z');
fmc0_fd_tdc_oe_n_o <= '1';
fmc0_tdc_data_in <= fmc0_fd_tdc_d_b;
-- tristate buffer for the TDC data bus:
fd_tdc_d_b <= tdc_data_out when tdc_data_oe = '1' else (others => 'Z');
fd_tdc_oe_n_o <= '1';
tdc_data_in <= fd_tdc_d_b;
fmc0_fd_onewire_b <= '0' when fmc0_fd_owr_en = '1' else 'Z';
fmc0_fd_owr_in <= fmc0_fd_onewire_b;
fd_onewire_b <= '0' when fd_owr_en = '1' else 'Z';
fd_owr_in <= fd_onewire_b;
------------------------------------------------------------------------------
-- Carrier LEDs
------------------------------------------------------------------------------
end rtl;
cmp_pci_access_led : gc_extend_pulse
generic map (
g_width => 2500000)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_GENNUM).cyc,
extended_o => gn4124_access);
aux_leds_o(0) <= not gn4124_access;
aux_leds_o(1) <= '1';
aux_leds_o(2) <= not tm_time_valid;
aux_leds_o(3) <= not pps_led;
end architecture arch;
hdl/top/spec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ b29188b3
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec-fine-delay ",
syn_commit_id => "7dd0a8c348dee0a3a660143c80487a8a",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20141209",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end package synthesis_descriptor;
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