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FMC DEL 1ns 4cha
Commits
5c08b95a
Commit
5c08b95a
authored
Feb 26, 2012
by
Tomasz Wlostowski
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hdl: renamed timing components to avoid conflicts with wr-cores
parent
f2a729ec
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4 changed files
with
13 additions
and
15 deletions
+13
-15
Manifest.py
hdl/rtl/Manifest.py
+2
-4
fd_dmtd_insertion_calibrator.vhd
hdl/rtl/fd_dmtd_insertion_calibrator.vhd
+4
-4
fd_dmtd_with_deglitcher.vhd
hdl/rtl/timing/fd_dmtd_with_deglitcher.vhd
+4
-4
fd_hpll_period_detect.vhd
hdl/rtl/timing/fd_hpll_period_detect.vhd
+3
-3
No files found.
hdl/rtl/Manifest.py
View file @
5c08b95a
files
=
[
"fd_acam_timestamper.vhd"
,
files
=
[
"fd_acam_timestamper.vhd"
,
"fd_ring_buffer.vhd"
,
"fd_ring_buffer.vhd"
,
"fd_ts_adder.vhd"
,
"fd_ts_adder.vhd"
,
"fd_ts_normalizer.vhd"
,
"fd_reset_generator.vhd"
,
"fd_reset_generator.vhd"
,
"fd_csync_generator.vhd"
,
"fd_csync_generator.vhd"
,
"fd_timestamper_stat_unit.vhd"
,
"fd_timestamper_stat_unit.vhd"
,
"fd_acam_timestamp_postprocessor.vhd"
,
"fd_acam_timestamp_postprocessor.vhd"
,
"fd_delay_channel_driver.vhd"
,
"fd_delay_channel_driver.vhd"
,
"fd_delay_line_arbiter.vhd"
,
"fd_delay_line_arbiter.vhd"
,
"fd_rearm_generator.vhd"
,
"fd_spi_master.vhd"
,
"fd_spi_master.vhd"
,
"fd_spi_dac_arbiter.vhd"
,
"fd_spi_dac_arbiter.vhd"
,
"fine_delay_pkg.vhd"
,
"fine_delay_pkg.vhd"
,
...
@@ -18,8 +16,8 @@ files = ["fd_acam_timestamper.vhd",
...
@@ -18,8 +16,8 @@ files = ["fd_acam_timestamper.vhd",
"fd_channel_wbgen2_pkg.vhd"
,
"fd_channel_wbgen2_pkg.vhd"
,
"fd_main_wbgen2_pkg.vhd"
,
"fd_main_wbgen2_pkg.vhd"
,
"fd_dmtd_insertion_calibrator.vhd"
,
"fd_dmtd_insertion_calibrator.vhd"
,
"timing/dmtd_with_deglitcher.vhd"
,
"timing/
fd_
dmtd_with_deglitcher.vhd"
,
"timing/hpll_period_detect.vhd"
"timing/
fd_
hpll_period_detect.vhd"
];
];
fetchto
=
"../ip_cores"
fetchto
=
"../ip_cores"
...
...
hdl/rtl/fd_dmtd_insertion_calibrator.vhd
View file @
5c08b95a
...
@@ -97,7 +97,7 @@ architecture rtl of fd_dmtd_insertion_calibrator is
...
@@ -97,7 +97,7 @@ architecture rtl of fd_dmtd_insertion_calibrator is
constant
c_INPUT_DEGLITCH_THRESHOLD
:
integer
:
=
200
;
constant
c_INPUT_DEGLITCH_THRESHOLD
:
integer
:
=
200
;
component
hpll_period_detect
component
fd_
hpll_period_detect
generic
(
generic
(
g_freq_err_frac_bits
:
integer
);
g_freq_err_frac_bits
:
integer
);
port
(
port
(
...
@@ -113,7 +113,7 @@ architecture rtl of fd_dmtd_insertion_calibrator is
...
@@ -113,7 +113,7 @@ architecture rtl of fd_dmtd_insertion_calibrator is
hpll_fbcr_ferr_set_i
:
in
std_logic_vector
(
11
downto
0
));
hpll_fbcr_ferr_set_i
:
in
std_logic_vector
(
11
downto
0
));
end
component
;
end
component
;
component
dmtd_with_deglitcher
component
fd_
dmtd_with_deglitcher
generic
(
generic
(
g_counter_bits
:
natural
;
g_counter_bits
:
natural
;
g_chipscope
:
boolean
:
=
false
);
g_chipscope
:
boolean
:
=
false
);
...
@@ -163,7 +163,7 @@ begin -- rtl
...
@@ -163,7 +163,7 @@ begin -- rtl
synced_o
=>
rst_n_dmtd
);
synced_o
=>
rst_n_dmtd
);
gen_without_wr_core
:
if
(
g_with_wr_core
=
false
)
generate
gen_without_wr_core
:
if
(
g_with_wr_core
=
false
)
generate
U_Period_Detect
:
hpll_period_detect
U_Period_Detect
:
fd_
hpll_period_detect
generic
map
(
generic
map
(
g_freq_err_frac_bits
=>
0
)
g_freq_err_frac_bits
=>
0
)
port
map
(
port
map
(
...
@@ -179,7 +179,7 @@ begin -- rtl
...
@@ -179,7 +179,7 @@ begin -- rtl
hpll_fbcr_ferr_set_i
=>
x"000"
-- no error setpoint, we can do that in software
hpll_fbcr_ferr_set_i
=>
x"000"
-- no error setpoint, we can do that in software
);
);
U_SoftPLL_DMTD
:
dmtd_with_deglitcher
U_SoftPLL_DMTD
:
fd_
dmtd_with_deglitcher
generic
map
(
generic
map
(
g_counter_bits
=>
20
,
g_counter_bits
=>
20
,
g_chipscope
=>
false
)
g_chipscope
=>
false
)
...
...
hdl/rtl/timing/dmtd_with_deglitcher.vhd
→
hdl/rtl/timing/
fd_
dmtd_with_deglitcher.vhd
View file @
5c08b95a
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
-- Title : Digital DMTD Edge Tagger
-- Title : Digital DMTD Edge Tagger
-- Project : White Rabbit
-- Project : White Rabbit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : dmtd_with_deglitcher.vhd
-- File :
fd_
dmtd_with_deglitcher.vhd
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Created : 2010-02-25
...
@@ -48,7 +48,7 @@ use ieee.NUMERIC_STD.all;
...
@@ -48,7 +48,7 @@ use ieee.NUMERIC_STD.all;
library
work
;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
entity
dmtd_with_deglitcher
is
entity
fd_
dmtd_with_deglitcher
is
generic
(
generic
(
-- Size of the phase tag counter. Must be big enough to cover at least one
-- Size of the phase tag counter. Must be big enough to cover at least one
-- full period of the DDMTD detector output. Given the frequencies of clk_in_i
-- full period of the DDMTD detector output. Given the frequencies of clk_in_i
...
@@ -95,9 +95,9 @@ entity dmtd_with_deglitcher is
...
@@ -95,9 +95,9 @@ entity dmtd_with_deglitcher is
tag_stb_p1_o
:
out
std_logic
tag_stb_p1_o
:
out
std_logic
);
);
end
dmtd_with_deglitcher
;
end
fd_
dmtd_with_deglitcher
;
architecture
rtl
of
dmtd_with_deglitcher
is
architecture
rtl
of
fd_
dmtd_with_deglitcher
is
type
t_state
is
(
WAIT_STABLE_0
,
WAIT_EDGE
,
GOT_EDGE
);
type
t_state
is
(
WAIT_STABLE_0
,
WAIT_EDGE
,
GOT_EDGE
);
...
...
hdl/rtl/timing/hpll_period_detect.vhd
→
hdl/rtl/timing/
fd_
hpll_period_detect.vhd
View file @
5c08b95a
...
@@ -32,7 +32,7 @@ use ieee.numeric_std.all;
...
@@ -32,7 +32,7 @@ use ieee.numeric_std.all;
use
work
.
gencores_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
entity
hpll_period_detect
is
entity
fd_
hpll_period_detect
is
generic
(
generic
(
g_freq_err_frac_bits
:
integer
);
g_freq_err_frac_bits
:
integer
);
port
(
port
(
...
@@ -75,9 +75,9 @@ entity hpll_period_detect is
...
@@ -75,9 +75,9 @@ entity hpll_period_detect is
hpll_fbcr_ferr_set_i
:
in
std_logic_vector
(
11
downto
0
)
hpll_fbcr_ferr_set_i
:
in
std_logic_vector
(
11
downto
0
)
);
);
end
hpll_period_detect
;
end
fd_
hpll_period_detect
;
architecture
rtl
of
hpll_period_detect
is
architecture
rtl
of
fd_
hpll_period_detect
is
-- derived from the maximum gating period (2 ^ 21 + 1 "safety" bit)
-- derived from the maximum gating period (2 ^ 21 + 1 "safety" bit)
constant
c_COUNTER_BITS
:
integer
:
=
22
;
constant
c_COUNTER_BITS
:
integer
:
=
22
;
...
...
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