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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
57dd2715
Commit
57dd2715
authored
Aug 13, 2012
by
Tomasz Wlostowski
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rtl/fine_delay_core.vhd: increase SPI clock speed for system-level simulation
parent
78b34df6
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32 deletions
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fine_delay_core.vhd
hdl/rtl/fine_delay_core.vhd
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hdl/rtl/fine_delay_core.vhd
View file @
57dd2715
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-0
6-06
-- Last update: 2012-0
8-09
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -242,6 +242,15 @@ architecture rtl of fine_delay_core is
x"000003c0"
,
x"000003c0"
);
function
f_select_spi_rate
return
integer
is
begin
if
(
g_simulation
)
then
return
1
;
else
return
8
;
end
if
;
end
f_select_spi_rate
;
signal
tag_frac
:
std_logic_vector
(
c_TIMESTAMP_FRAC_BITS
-1
downto
0
);
signal
tag_coarse
:
std_logic_vector
(
c_TIMESTAMP_COARSE_BITS
-1
downto
0
);
signal
tag_utc
:
std_logic_vector
(
c_TIMESTAMP_UTC_BITS
-1
downto
0
);
...
...
@@ -398,7 +407,7 @@ begin -- rtl
U_SPI_Arbiter
:
fd_spi_dac_arbiter
generic
map
(
g_div_ratio_log2
=>
8
)
g_div_ratio_log2
=>
f_select_spi_rate
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys
,
...
...
@@ -694,7 +703,7 @@ begin -- rtl
-- VCXO Frequency measuremnt (for DAC testing purposes)
U_VCXO_Freq_Meter
:
gc_frequency_meter
U_VCXO_Freq_Meter
:
gc_frequency_meter
generic
map
(
g_with_internal_timebase
=>
true
,
g_clk_sys_freq
=>
c_SYS_CLK_FREQ
,
...
...
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