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FMC DEL 1ns 4cha
Commits
4d14ac35
Commit
4d14ac35
authored
Jun 11, 2013
by
Tomasz Wlostowski
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hdl/top/svec: support for SVEC front panel LEDs displaying WR/VME status
parent
1f87dc6a
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6 changed files
with
679 additions
and
242 deletions
+679
-242
svec_fine_delay.xise
hdl/syn/svec/wr/svec_fine_delay.xise
+225
-228
Manifest.py
hdl/top/svec/wr/Manifest.py
+1
-1
bicolor_led_ctrl.vhd
hdl/top/svec/wr/bicolor_led_ctrl.vhd
+241
-0
bicolor_led_ctrl_pkg.vhd
hdl/top/svec/wr/bicolor_led_ctrl_pkg.vhd
+98
-0
svec_top.ucf
hdl/top/svec/wr/svec_top.ucf
+17
-0
svec_top.vhd
hdl/top/svec/wr/svec_top.vhd
+97
-13
No files found.
hdl/syn/svec/wr/svec_fine_delay.xise
View file @
4d14ac35
...
...
@@ -356,683 +356,680 @@
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>
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>
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<file
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>
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<file
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>
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>
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>
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>
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>
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4
"
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<association
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3
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</file>
<file
xil_pn:name=
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xil_pn:type=
"FILE_VHDL"
>
<association
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5
"
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<association
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4
"
/>
</file>
<file
xil_pn:name=
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xil_pn:type=
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>
<association
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xil_pn:seqID=
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6
"
/>
<association
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5
"
/>
</file>
<file
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xil_pn:type=
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>
<association
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7
"
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<association
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6
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</file>
<file
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xil_pn:type=
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>
<association
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8
"
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<association
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</file>
<file
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>
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<file
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>
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20
"
/>
<association
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19
"
/>
</file>
<file
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xil_pn:type=
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>
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1
"
/>
<association
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0
"
/>
</file>
<file
xil_pn:name=
"../../../../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"22
2
"
/>
<association
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1
"
/>
</file>
<file
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"../../../../../wr-cores/modules/wrc_core/xwr_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
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"Implementation"
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3
"
/>
<association
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2
"
/>
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<file
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xil_pn:type=
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>
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4
"
/>
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3
"
/>
</file>
<file
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"../../../top/svec/wr/svec_top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
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"Implementation"
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5
"
/>
<association
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4
"
/>
</file>
<file
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"../../../../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
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>
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6
"
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<association
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</file>
<file
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>
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7
"
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6
"
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>
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8
"
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<association
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"Implementation"
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"22
7
"
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</file>
<file
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"../../../../../wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
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"Implementation"
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9
"
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<association
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"22
8
"
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</file>
<file
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"../../../../../wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd"
xil_pn:type=
"FILE_VHDL"
>
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30
"
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29
"
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<file
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>
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"
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<association
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"
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</file>
<file
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xil_pn:type=
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>
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"
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<association
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1
"
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<file
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>
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"
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<association
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"Implementation"
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"23
2
"
/>
</file>
</files>
...
...
hdl/top/svec/wr/Manifest.py
View file @
4d14ac35
files
=
[
"synthesis_descriptor.vhd"
,
"svec_top.vhd"
,
"svec_top.ucf"
,
"xvme64x_core.vhd"
]
files
=
[
"synthesis_descriptor.vhd"
,
"svec_top.vhd"
,
"svec_top.ucf"
,
"xvme64x_core.vhd"
,
"bicolor_led_ctrl.vhd"
,
"bicolor_led_ctrl_pkg.vhd"
]
fetchto
=
"../../../ip_cores"
...
...
hdl/top/svec/wr/bicolor_led_ctrl.vhd
0 → 100644
View file @
4d14ac35
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
-- The FPGA ouputs for the columns (C) are connected to buffers
-- and serial resistances and then to the LEDs. The FPGA outputs
-- for lines (L) are connected to tri-state buffers and the to
-- the LEDs. The FPGA outputs for lines output enable (L_OEN) are
-- connected to the output enable of the tri-state buffers.
--
-- Example with three lines and two columns:
--
-- |<refresh period>|
--
-- L1/L2/L3 __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--
-- L1_OEN -----|___________|-----|___________|-----|___________|-----|___________|--
--
-- L2_OEN _____|-----|___________|-----|___________|-----|___________|-----|________
--
-- L3_OEN ___________|-----|___________|-----|___________|-----|___________|-----|__
--
-- Cn __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
--
-- LED Ln/Cn OFF | color_1 | color_2 | both_colors |
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
library
work
;
use
work
.
bicolor_led_ctrl_pkg
.
all
;
entity
bicolor_led_ctrl
is
generic
(
g_NB_COLUMN
:
natural
:
=
4
;
g_NB_LINE
:
natural
:
=
2
;
g_CLK_FREQ
:
natural
:
=
125000000
;
-- in Hz
g_REFRESH_RATE
:
natural
:
=
250
-- in Hz
);
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
led_intensity_i
:
in
std_logic_vector
(
6
downto
0
);
led_state_i
:
in
std_logic_vector
((
g_NB_LINE
*
g_NB_COLUMN
*
2
)
-
1
downto
0
);
column_o
:
out
std_logic_vector
(
g_NB_COLUMN
-
1
downto
0
);
line_o
:
out
std_logic_vector
(
g_NB_LINE
-
1
downto
0
);
line_oen_o
:
out
std_logic_vector
(
g_NB_LINE
-
1
downto
0
)
);
end
bicolor_led_ctrl
;
architecture
rtl
of
bicolor_led_ctrl
is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant
c_REFRESH_CNT_INIT
:
natural
:
=
natural
(
g_CLK_FREQ
/
(
2
*
g_NB_LINE
*
g_REFRESH_RATE
))
-
1
;
constant
c_REFRESH_CNT_NB_BITS
:
natural
:
=
log2_ceil
(
c_REFRESH_CNT_INIT
);
constant
c_LINE_OEN_CNT_NB_BITS
:
natural
:
=
log2_ceil
(
g_NB_LINE
);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal
refresh_rate_cnt
:
unsigned
(
c_REFRESH_CNT_NB_BITS
-
1
downto
0
);
signal
refresh_rate
:
std_logic
;
signal
line_ctrl
:
std_logic
;
signal
intensity_ctrl_cnt
:
unsigned
(
c_REFRESH_CNT_NB_BITS
-
1
downto
0
);
signal
intensity_ctrl
:
std_logic
;
signal
line_oen_cnt
:
unsigned
(
c_LINE_OEN_CNT_NB_BITS
-
1
downto
0
);
signal
line_oen
:
std_logic_vector
(
2
**
c_LINE_OEN_CNT_NB_BITS
-
1
downto
0
);
signal
led_state
:
std_logic_vector
((
g_NB_LINE
*
g_NB_COLUMN
)
-1
downto
0
);
begin
------------------------------------------------------------------------------
-- Refresh rate counter
------------------------------------------------------------------------------
p_refresh_rate_cnt
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
refresh_rate_cnt
<=
(
others
=>
'0'
);
refresh_rate
<=
'0'
;
elsif
refresh_rate_cnt
=
0
then
refresh_rate_cnt
<=
to_unsigned
(
c_REFRESH_CNT_INIT
,
c_REFRESH_CNT_NB_BITS
);
refresh_rate
<=
'1'
;
else
refresh_rate_cnt
<=
refresh_rate_cnt
-
1
;
refresh_rate
<=
'0'
;
end
if
;
end
if
;
end
process
p_refresh_rate_cnt
;
------------------------------------------------------------------------------
-- Intensity control
------------------------------------------------------------------------------
p_intensity_ctrl_cnt
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
intensity_ctrl_cnt
<=
(
others
=>
'0'
);
elsif
refresh_rate
=
'1'
then
intensity_ctrl_cnt
<=
to_unsigned
(
natural
(
c_REFRESH_CNT_INIT
/
100
)
*
to_integer
(
unsigned
(
led_intensity_i
)),
c_REFRESH_CNT_NB_BITS
);
else
intensity_ctrl_cnt
<=
intensity_ctrl_cnt
-
1
;
end
if
;
end
if
;
end
process
p_intensity_ctrl_cnt
;
p_intensity_ctrl
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
intensity_ctrl
<=
'0'
;
elsif
refresh_rate
=
'1'
then
intensity_ctrl
<=
'1'
;
elsif
intensity_ctrl_cnt
=
0
then
intensity_ctrl
<=
'0'
;
end
if
;
end
if
;
end
process
p_intensity_ctrl
;
------------------------------------------------------------------------------
-- Lines ouput
------------------------------------------------------------------------------
p_line_ctrl
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
line_ctrl
<=
'0'
;
elsif
refresh_rate
=
'1'
then
line_ctrl
<=
not
(
line_ctrl
);
end
if
;
end
if
;
end
process
p_line_ctrl
;
f_line_o
:
for
I
in
0
to
g_NB_LINE
-
1
generate
line_o
(
I
)
<=
line_ctrl
and
intensity_ctrl
;
end
generate
f_line_o
;
------------------------------------------------------------------------------
-- Lines output enable
------------------------------------------------------------------------------
p_line_oen_cnt
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
line_oen_cnt
<=
(
others
=>
'0'
);
elsif
line_ctrl
=
'1'
and
refresh_rate
=
'1'
then
if
line_oen_cnt
=
0
then
line_oen_cnt
<=
to_unsigned
(
g_NB_LINE
-
1
,
c_LINE_OEN_CNT_NB_BITS
);
else
line_oen_cnt
<=
line_oen_cnt
-
1
;
end
if
;
end
if
;
end
if
;
end
process
p_line_oen_cnt
;
p_line_oen_decode
:
process
(
line_oen_cnt
)
variable
v_onehot
:
std_logic_vector
((
2
**
line_oen_cnt
'length
)
-1
downto
0
);
variable
v_index
:
integer
range
0
to
(
2
**
line_oen_cnt
'length
)
-1
;
begin
v_onehot
:
=
(
others
=>
'0'
);
v_index
:
=
0
;
for
i
in
line_oen_cnt
'range
loop
if
(
line_oen_cnt
(
i
)
=
'1'
)
then
v_index
:
=
2
*
v_index
+
1
;
else
v_index
:
=
2
*
v_index
;
end
if
;
end
loop
;
v_onehot
(
v_index
)
:
=
'1'
;
line_oen
<=
v_onehot
;
end
process
p_line_oen_decode
;
line_oen_o
<=
line_oen
(
line_oen_o
'left
downto
0
);
------------------------------------------------------------------------------
-- Columns output
------------------------------------------------------------------------------
f_led_state
:
for
I
in
0
to
(
g_NB_COLUMN
*
g_NB_LINE
)
-
1
generate
led_state
(
I
)
<=
'0'
when
led_state_i
(
2
*
I
+
1
downto
2
*
I
)
=
c_LED_RED
else
'1'
when
led_state_i
(
2
*
I
+
1
downto
2
*
I
)
=
c_LED_GREEN
else
(
line_ctrl
and
intensity_ctrl
)
when
led_state_i
(
2
*
I
+
1
downto
2
*
I
)
=
c_LED_OFF
else
not
(
line_ctrl
and
intensity_ctrl
)
when
led_state_i
(
2
*
I
+
1
downto
2
*
I
)
=
c_LED_RED_GREEN
;
end
generate
f_led_state
;
f_column_o
:
for
C
in
0
to
g_NB_COLUMN
-
1
generate
column_o
(
C
)
<=
led_state
(
g_NB_COLUMN
*
to_integer
(
line_oen_cnt
)
+
C
);
end
generate
f_column_o
;
end
rtl
;
hdl/top/svec/wr/bicolor_led_ctrl_pkg.vhd
0 → 100644
View file @
4d14ac35
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller package
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_pkg
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Package for Bi-color LED controller.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
package
bicolor_led_ctrl_pkg
is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant
c_LED_RED
:
std_logic_vector
(
1
downto
0
)
:
=
"10"
;
constant
c_LED_GREEN
:
std_logic_vector
(
1
downto
0
)
:
=
"01"
;
constant
c_LED_RED_GREEN
:
std_logic_vector
(
1
downto
0
)
:
=
"11"
;
constant
c_LED_OFF
:
std_logic_vector
(
1
downto
0
)
:
=
"00"
;
------------------------------------------------------------------------------
-- Functions declaration
------------------------------------------------------------------------------
function
log2_ceil
(
N
:
natural
)
return
positive
;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component
bicolor_led_ctrl
generic
(
g_NB_COLUMN
:
natural
:
=
4
;
g_NB_LINE
:
natural
:
=
2
;
g_CLK_FREQ
:
natural
:
=
125000000
;
-- in Hz
g_REFRESH_RATE
:
natural
:
=
250
-- in Hz
);
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
led_intensity_i
:
in
std_logic_vector
(
6
downto
0
);
led_state_i
:
in
std_logic_vector
((
g_NB_LINE
*
g_NB_COLUMN
*
2
)
-
1
downto
0
);
column_o
:
out
std_logic_vector
(
g_NB_COLUMN
-
1
downto
0
);
line_o
:
out
std_logic_vector
(
g_NB_LINE
-
1
downto
0
);
line_oen_o
:
out
std_logic_vector
(
g_NB_LINE
-
1
downto
0
)
);
end
component
;
end
bicolor_led_ctrl_pkg
;
package
body
bicolor_led_ctrl_pkg
is
------------------------------------------------------------------------------
-- Function : Returns log of 2 of a natural number
------------------------------------------------------------------------------
function
log2_ceil
(
N
:
natural
)
return
positive
is
begin
if
N
<=
2
then
return
1
;
elsif
N
mod
2
=
0
then
return
1
+
log2_ceil
(
N
/
2
);
else
return
1
+
log2_ceil
((
N
+
1
)
/
2
);
end
if
;
end
;
end
bicolor_led_ctrl_pkg
;
hdl/top/svec/wr/svec_top.ucf
View file @
4d14ac35
...
...
@@ -308,6 +308,23 @@ NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
...
...
hdl/top/svec/wr/svec_top.vhd
View file @
4d14ac35
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-0
5-22
-- Last update: 2013-0
6-11
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -79,6 +79,12 @@ entity svec_top is
rst_n_i
:
in
std_logic
;
-- SVEC Front panel LEDs
fp_led_line_oen_o
:
out
std_logic_vector
(
1
downto
0
);
fp_led_line_o
:
out
std_logic_vector
(
1
downto
0
);
fp_led_column_o
:
out
std_logic_vector
(
3
downto
0
);
-------------------------------------------------------------------------
-- VME Interface pins
-------------------------------------------------------------------------
...
...
@@ -297,6 +303,22 @@ architecture rtl of svec_top is
xdone_o
:
out
std_logic
);
end
component
;
component
bicolor_led_ctrl
generic
(
g_NB_COLUMN
:
natural
;
g_NB_LINE
:
natural
;
g_CLK_FREQ
:
natural
;
g_REFRESH_RATE
:
natural
);
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
led_intensity_i
:
in
std_logic_vector
(
6
downto
0
);
led_state_i
:
in
std_logic_vector
((
g_NB_LINE
*
g_NB_COLUMN
*
2
)
-
1
downto
0
);
column_o
:
out
std_logic_vector
(
g_NB_COLUMN
-
1
downto
0
);
line_o
:
out
std_logic_vector
(
g_NB_LINE
-
1
downto
0
);
line_oen_o
:
out
std_logic_vector
(
g_NB_LINE
-
1
downto
0
));
end
component
;
signal
VME_DATA_b_out
:
std_logic_vector
(
31
downto
0
);
signal
VME_ADDR_b_out
:
std_logic_vector
(
31
downto
1
);
signal
VME_LWORD_n_b_out
,
VME_DATA_DIR_int
,
VME_ADDR_DIR_int
:
std_logic
;
...
...
@@ -336,13 +358,13 @@ architecture rtl of svec_top is
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_MASTERS
+
1
downto
0
)
:
=
(
c_SLAVE_FD0
=>
f_sdb_embed_device
(
c_FD_SDB_DEVICE
,
x"00010000"
),
c_SLAVE_FD1
=>
f_sdb_embed_device
(
c_FD_SDB_DEVICE
,
x"00020000"
),
c_SLAVE_VIC
=>
f_sdb_embed_device
(
c_xwb_vic_sdb
,
x"00030000"
),
c_SLAVE_WRCORE
=>
f_sdb_embed_bridge
(
c_WRCORE_BRIDGE_SDB
,
x"00040000"
),
c_DESC_SYNTHESIS
=>
f_sdb_embed_synthesis
(
c_sdb_synthesis_info
),
c_DESC_REPO_URL
=>
f_sdb_embed_repo_url
(
c_sdb_repo_url
)
);
c_SLAVE_FD0
=>
f_sdb_embed_device
(
c_FD_SDB_DEVICE
,
x"00010000"
),
c_SLAVE_FD1
=>
f_sdb_embed_device
(
c_FD_SDB_DEVICE
,
x"00020000"
),
c_SLAVE_VIC
=>
f_sdb_embed_device
(
c_xwb_vic_sdb
,
x"00030000"
),
c_SLAVE_WRCORE
=>
f_sdb_embed_bridge
(
c_WRCORE_BRIDGE_SDB
,
x"00040000"
),
c_DESC_SYNTHESIS
=>
f_sdb_embed_synthesis
(
c_sdb_synthesis_info
),
c_DESC_REPO_URL
=>
f_sdb_embed_repo_url
(
c_sdb_repo_url
)
);
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00000000"
;
...
...
@@ -448,6 +470,13 @@ architecture rtl of svec_top is
signal
powerup_reset_cnt
:
unsigned
(
7
downto
0
)
:
=
"00000000"
;
signal
powerup_rst_n
:
std_logic
:
=
'0'
;
signal
sys_locked
:
std_logic
;
signal
led_state
:
std_logic_vector
(
15
downto
0
);
signal
pps_led
:
std_logic
;
signal
led_link
:
std_logic
;
signal
led_act
:
std_logic
;
signal
vme_access
:
std_logic
;
begin
...
...
@@ -687,8 +716,8 @@ begin
phy_rst_o
=>
phy_rst
,
phy_loopen_o
=>
phy_loopen
,
led_link_o
=>
open
,
led_act_o
=>
open
,
led_link_o
=>
led_link
,
led_act_o
=>
led_act
,
scl_o
=>
wrc_scl_out
,
scl_i
=>
wrc_scl_in
,
...
...
@@ -730,7 +759,8 @@ begin
tm_cycles_o
=>
tm_cycles
,
rst_aux_n_o
=>
etherbone_rst_n
,
pps_p_o
=>
pps
pps_p_o
=>
pps
,
pps_led_o
=>
pps_led
);
U_DAC_Helper
:
spec_serial_dac
...
...
@@ -784,7 +814,7 @@ begin
cnx_slave_in
(
c_MASTER_ETHERBONE
)
.
cyc
<=
'0'
;
U_Intercon
:
xwb_sdb_crossbar
generic
map
(
g_num_masters
=>
c_NUM_WB_SLAVES
,
...
...
@@ -975,7 +1005,7 @@ begin
-------------------------------------------------------------------------------
-- FINE DELAY
0
INSTANTIATION
-- FINE DELAY
1
INSTANTIATION
-------------------------------------------------------------------------------
cmp_fd_tdc_start1
:
IBUFDS
...
...
@@ -1086,6 +1116,60 @@ begin
fd1_onewire_b
<=
'0'
when
fd1_owr_en
=
'1'
else
'Z'
;
fd1_owr_in
<=
fd1_onewire_b
;
U_LED_Controller
:
bicolor_led_ctrl
generic
map
(
g_NB_COLUMN
=>
4
,
g_NB_LINE
=>
2
,
g_CLK_FREQ
=>
62500000
,
-- in Hz
g_REFRESH_RATE
=>
250
-- in Hz
)
port
map
(
rst_n_i
=>
local_reset_n
,
clk_i
=>
clk_sys
,
led_intensity_i
=>
"1100100"
,
-- in %
led_state_i
=>
led_state
,
column_o
=>
fp_led_column_o
,
line_o
=>
fp_led_line_o
,
line_oen_o
=>
fp_led_line_oen_o
);
U_Drive_VME_Access_Led
:
gc_extend_pulse
generic
map
(
g_width
=>
5000000
)
port
map
(
clk_i
=>
clk_sys
,
rst_n_i
=>
local_reset_n
,
pulse_i
=>
cnx_slave_in
(
c_MASTER_VME
)
.
cyc
,
extended_o
=>
vme_access
);
-- Drive the front panel LEDs:
-- LED 1: WR Link status
led_state
(
0
)
<=
led_link
;
led_state
(
1
)
<=
'0'
;
-- LED 2: WR Link activity status
led_state
(
2
)
<=
led_act
;
led_state
(
3
)
<=
'0'
;
-- LED 3: WR PPS blink
led_state
(
4
)
<=
pps_led
;
led_state
(
5
)
<=
'0'
;
-- LED 4: WR Time validity
led_state
(
6
)
<=
tm_time_valid
;
led_state
(
7
)
<=
'0'
;
-- LED 5: VME access
led_state
(
8
)
<=
vme_access
;
led_state
(
9
)
<=
'0'
;
led_state
(
15
downto
10
)
<=
(
others
=>
'0'
);
-- The SFP is permanently enabled.
sfp_tx_disable_o
<=
'0'
;
end
rtl
;
...
...
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