Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC DEL 1ns 4cha
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
2
Issues
2
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC DEL 1ns 4cha
Commits
47fc9599
Commit
47fc9599
authored
May 24, 2013
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl/top/svec: temporarily removed Etherbone (due to non-compatible API changes)
parent
c3aabf77
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
28 additions
and
65 deletions
+28
-65
svec_fine_delay.xise
hdl/syn/svec/wr/svec_fine_delay.xise
+1
-40
Manifest.py
hdl/top/svec/wr/Manifest.py
+2
-2
svec_top.vhd
hdl/top/svec/wr/svec_top.vhd
+25
-23
No files found.
hdl/syn/svec/wr/svec_fine_delay.xise
View file @
47fc9599
...
...
@@ -1007,7 +1007,7 @@
<file
xil_pn:name=
"../../../../../wr-cores/modules/wrc_core/xwr_syscon_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"224"
/>
</file>
<file
xil_pn:name=
"../../../
../../etherbone-core/hdl/eb_slave_core/etherbone_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../
top/svec/wr/svec_top
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"225"
/>
</file>
<file
xil_pn:name=
"../../../../../wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -1034,45 +1034,6 @@
<file
xil_pn:name=
"../../../../../wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"233"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"234"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/eb_checksum.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"235"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/eb_config.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"236"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"237"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"238"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"239"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"240"
/>
</file>
<file
xil_pn:name=
"../../../top/svec/wr/svec_top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"241"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/piso_flag.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"242"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"243"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/sipo_flag.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"244"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"245"
/>
</file>
<file
xil_pn:name=
"../../../../../etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"246"
/>
</file>
</files>
<bindings/>
...
...
hdl/top/svec/wr/Manifest.py
View file @
47fc9599
...
...
@@ -4,7 +4,7 @@ fetchto = "../../../ip_cores"
modules
=
{
"local"
:
[
"../../../rtl"
,
"../../../platform"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/wr-cores.git"
,
"git://ohwr.org/hdl-core-lib/etherbone-core.git"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/wr-cores.git"
]
,
#
"git://ohwr.org/hdl-core-lib/etherbone-core.git" ],
"svn"
:
[
"http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl"
]
}
hdl/top/svec/wr/svec_top.vhd
View file @
47fc9599
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-05-
17
-- Last update: 2013-05-
22
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -48,7 +48,7 @@ use work.wrcore_pkg.all;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
fine_delay_pkg
.
all
;
use
work
.
etherbone_pkg
.
all
;
--
use work.etherbone_pkg.all;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
synthesis_descriptor
.
all
;
...
...
@@ -709,13 +709,13 @@ begin
slave_i
=>
cnx_master_out
(
c_SLAVE_WRCORE
),
slave_o
=>
cnx_master_in
(
c_SLAVE_WRCORE
),
aux_master_o
=>
etherbone_cfg_in
,
aux_master_i
=>
etherbone_cfg_out
,
--
aux_master_o => etherbone_cfg_in,
--
aux_master_i => etherbone_cfg_out,
wrf_src_o
=>
etherbone_snk_in
,
wrf_src_i
=>
etherbone_snk_out
,
wrf_snk_o
=>
etherbone_src_in
,
wrf_snk_i
=>
etherbone_src_out
,
--
wrf_src_o => etherbone_snk_in,
--
wrf_src_i => etherbone_snk_out,
--
wrf_snk_o => etherbone_src_in,
--
wrf_snk_i => etherbone_src_out,
btn1_i
=>
'0'
,
btn2_i
=>
'0'
,
...
...
@@ -767,21 +767,23 @@ begin
dac_sdata_o
=>
pll25dac_din_o
,
xdone_o
=>
open
);
U_Etherbone
:
eb_slave_core
generic
map
(
g_sdb_address
=>
f_resize_slv
(
c_sdb_address
,
64
))
port
map
(
clk_i
=>
clk_sys
,
nRst_i
=>
etherbone_rst_n
,
src_o
=>
etherbone_src_out
,
src_i
=>
etherbone_src_in
,
snk_o
=>
etherbone_snk_out
,
snk_i
=>
etherbone_snk_in
,
cfg_slave_o
=>
etherbone_cfg_out
,
cfg_slave_i
=>
etherbone_cfg_in
,
master_o
=>
cnx_slave_in
(
c_MASTER_ETHERBONE
),
master_i
=>
cnx_slave_out
(
c_MASTER_ETHERBONE
));
--U_Etherbone : eb_slave_core
-- generic map (
-- g_sdb_address => f_resize_slv(c_sdb_address, 64))
-- port map (
-- clk_i => clk_sys,
-- nRst_i => etherbone_rst_n,
-- src_o => etherbone_src_out,
-- src_i => etherbone_src_in,
-- snk_o => etherbone_snk_out,
-- snk_i => etherbone_snk_in,
-- cfg_slave_o => etherbone_cfg_out,
-- cfg_slave_i => etherbone_cfg_in,
-- master_o => cnx_slave_in(c_MASTER_ETHERBONE),
-- master_i => cnx_slave_out(c_MASTER_ETHERBONE));
cnx_slave_in
(
c_MASTER_ETHERBONE
)
.
cyc
<=
'0'
;
U_Intercon
:
xwb_sdb_crossbar
generic
map
(
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment