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FMC DEL 1ns 4cha
Commits
4160f44e
Commit
4160f44e
authored
Oct 24, 2012
by
Tomasz Wlostowski
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hdl/testbench: minor fixes
parent
36e07dc3
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6 changed files
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263 additions
and
1091 deletions
+263
-1091
Makefile
hdl/testbench/old_top/Makefile
+0
-994
Manifest.py
hdl/testbench/old_top/Manifest.py
+1
-0
main.sv
hdl/testbench/old_top/main.sv
+37
-77
wave.do
hdl/testbench/old_top/wave.do
+4
-16
main.sv
hdl/testbench/svec_wr_top/main.sv
+1
-1
wave.do
hdl/testbench/svec_wr_top/wave.do
+220
-3
No files found.
hdl/testbench/old_top/Makefile
deleted
100644 → 0
View file @
36e07dc3
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
/opt/modelsim_10
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VERILOG_SRC
:=
main.sv
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
\
VERILOG_OBJ
:=
work/main/.main_sv
\
work/sockit_owm/.sockit_owm_v
\
work/spi_clgen/.spi_clgen_v
\
work/spi_shift/.spi_shift_v
\
work/spi_top/.spi_top_v
\
work/lm32_allprofiles/.lm32_allprofiles_v
\
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v
\
work/jtag_cores/.jtag_cores_v
\
work/lm32_adder/.lm32_adder_v
\
work/lm32_addsub/.lm32_addsub_v
\
work/lm32_dp_ram/.lm32_dp_ram_v
\
work/lm32_logic_op/.lm32_logic_op_v
\
work/lm32_ram/.lm32_ram_v
\
work/lm32_shifter/.lm32_shifter_v
\
work/lm32_multiplier/.lm32_multiplier_v
\
work/jtag_tap/.jtag_tap_v
\
VHDL_SRC
:=
../../platform/fd_ddr_driver.vhd
\
../../platform/fd_ddr_pll.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
\
../../rtl/fd_channel_wbgen2_pkg.vhd
\
../../rtl/fd_ts_adder.vhd
\
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
\
../../rtl/fd_main_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
\
../../rtl/fine_delay_pkg.vhd
\
../../rtl/fd_delay_line_arbiter.vhd
\
../../rtl/fd_spi_master.vhd
\
../../rtl/fd_spi_dac_arbiter.vhd
\
../../rtl/fd_acam_timestamper.vhd
\
../../rtl/fd_acam_timestamp_postprocessor.vhd
\
../../rtl/fd_channel_wishbone_slave.vhd
\
../../rtl/fd_timestamper_stat_unit.vhd
\
../../rtl/fd_delay_channel_driver.vhd
\
../../rtl/fd_ring_buffer.vhd
\
../../rtl/fd_dmtd_insertion_calibrator.vhd
\
../../rtl/timing/fd_dmtd_with_deglitcher.vhd
\
../../rtl/timing/fd_hpll_period_detect.vhd
\
../../rtl/fd_reset_generator.vhd
\
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
\
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
\
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
\
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
\
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
\
../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd
\
../../ip_cores/general-cores/modules/common/gc_wfifo.vhd
\
../../rtl/fd_csync_generator.vhd
\
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
\
../../rtl/fine_delay_core.vhd
\
../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
\
../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
\
../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdwb_rom.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdwb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
\
../../rtl/fd_main_wishbone_slave.vhd
\
VHDL_OBJ
:=
work/fd_ddr_driver/.fd_ddr_driver_vhd
\
work/fd_ddr_pll/.fd_ddr_pll_vhd
\
work/wbgen2_pkg/.wbgen2_pkg_vhd
\
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg_vhd
\
work/fd_ts_adder/.fd_ts_adder_vhd
\
work/genram_pkg/.genram_pkg_vhd
\
work/gencores_pkg/.gencores_pkg_vhd
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg_vhd
\
work/wishbone_pkg/.wishbone_pkg_vhd
\
work/fine_delay_pkg/.fine_delay_pkg_vhd
\
work/fd_delay_line_arbiter/.fd_delay_line_arbiter_vhd
\
work/fd_spi_master/.fd_spi_master_vhd
\
work/fd_spi_dac_arbiter/.fd_spi_dac_arbiter_vhd
\
work/fd_acam_timestamper/.fd_acam_timestamper_vhd
\
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor_vhd
\
work/fd_channel_wishbone_slave/.fd_channel_wishbone_slave_vhd
\
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit_vhd
\
work/fd_delay_channel_driver/.fd_delay_channel_driver_vhd
\
work/fd_ring_buffer/.fd_ring_buffer_vhd
\
work/fd_dmtd_insertion_calibrator/.fd_dmtd_insertion_calibrator_vhd
\
work/fd_dmtd_with_deglitcher/.fd_dmtd_with_deglitcher_vhd
\
work/fd_hpll_period_detect/.fd_hpll_period_detect_vhd
\
work/fd_reset_generator/.fd_reset_generator_vhd
\
work/gc_crc_gen/.gc_crc_gen_vhd
\
work/gc_moving_average/.gc_moving_average_vhd
\
work/gc_extend_pulse/.gc_extend_pulse_vhd
\
work/gc_delay_gen/.gc_delay_gen_vhd
\
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd
\
work/gc_serial_dac/.gc_serial_dac_vhd
\
work/gc_sync_ffs/.gc_sync_ffs_vhd
\
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd
\
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd
\
work/gc_frequency_meter/.gc_frequency_meter_vhd
\
work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd
\
work/gc_wfifo/.gc_wfifo_vhd
\
work/fd_csync_generator/.fd_csync_generator_vhd
\
work/memory_loader_pkg/.memory_loader_pkg_vhd
\
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd
\
work/fine_delay_core/.fine_delay_core_vhd
\
work/generic_async_fifo/.generic_async_fifo_vhd
\
work/generic_dpram/.generic_dpram_vhd
\
work/generic_spram/.generic_spram_vhd
\
work/generic_sync_fifo/.generic_sync_fifo_vhd
\
work/wb_async_bridge/.wb_async_bridge_vhd
\
work/xwb_async_bridge/.xwb_async_bridge_vhd
\
work/wb_onewire_master/.wb_onewire_master_vhd
\
work/xwb_onewire_master/.xwb_onewire_master_vhd
\
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd
\
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd
\
work/i2c_master_top/.i2c_master_top_vhd
\
work/wb_i2c_master/.wb_i2c_master_vhd
\
work/xwb_i2c_master/.xwb_i2c_master_vhd
\
work/xwb_bus_fanout/.xwb_bus_fanout_vhd
\
work/xwb_dpram/.xwb_dpram_vhd
\
work/wb_gpio_port/.wb_gpio_port_vhd
\
work/xwb_gpio_port/.xwb_gpio_port_vhd
\
work/wb_tics/.wb_tics_vhd
\
work/xwb_tics/.xwb_tics_vhd
\
work/uart_async_rx/.uart_async_rx_vhd
\
work/uart_async_tx/.uart_async_tx_vhd
\
work/uart_baud_gen/.uart_baud_gen_vhd
\
work/simple_uart_pkg/.simple_uart_pkg_vhd
\
work/simple_uart_wb/.simple_uart_wb_vhd
\
work/wb_simple_uart/.wb_simple_uart_vhd
\
work/xwb_simple_uart/.xwb_simple_uart_vhd
\
work/vic_prio_enc/.vic_prio_enc_vhd
\
work/wb_slave_vic/.wb_slave_vic_vhd
\
work/wb_vic/.wb_vic_vhd
\
work/xwb_vic/.xwb_vic_vhd
\
work/wb_spi/.wb_spi_vhd
\
work/xwb_spi/.xwb_spi_vhd
\
work/sdwb_rom/.sdwb_rom_vhd
\
work/xwb_crossbar/.xwb_crossbar_vhd
\
work/xwb_sdwb_crossbar/.xwb_sdwb_crossbar_vhd
\
work/xwb_lm32/.xwb_lm32_vhd
\
work/wb_slave_adapter/.wb_slave_adapter_vhd
\
work/xloader_registers_pkg/.xloader_registers_pkg_vhd
\
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd
\
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd
\
work/xloader_wb/.xloader_wb_vhd
\
work/xwb_clock_crossing/.xwb_clock_crossing_vhd
\
work/xwb_dma/.xwb_dma_vhd
\
work/wbgen2_dpssram/.wbgen2_dpssram_vhd
\
work/wbgen2_eic/.wbgen2_eic_vhd
\
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd
\
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd
\
work/fd_main_wishbone_slave/.fd_main_wishbone_slave_vhd
\
LIBS
:=
work
LIB_IND
:=
work/.work
## rules #################################
sim
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
$(VHDL_OBJ)
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
clean
:
rm
-rf
./modelsim.ini
$(LIBS)
.PHONY
:
clean
work/.work
:
(
vlib work
&&
vmap
-modelsimini
modelsim.ini work
&&
touch
work/.work
)||
rm
-rf
work
work/main/.main_sv
:
main.sv ../../include/random_pulse_gen.sv ../../include/jittery_delay.sv ../../include/ideal_timestamper.sv ../../include/regs/fd_channel_regs.vh ../../include/acam_model.sv ../../include/mc100ep195.sv ../../include/regs/fd_main_regs.vh ../../include/tunable_clock_gen.sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
+incdir+. +incdir+../../include +incdir+../../include/wb
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/sockit_owm/.sockit_owm_v
:
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spi_clgen/.spi_clgen_v
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spi_shift/.spi_shift_v
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spi_top/.spi_top_v
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_allprofiles/.lm32_allprofiles_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/jtag_cores/.jtag_cores_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_adder/.lm32_adder_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_addsub/.lm32_addsub_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_dp_ram/.lm32_dp_ram_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_logic_op/.lm32_logic_op_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_ram/.lm32_ram_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_shifter/.lm32_shifter_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_multiplier/.lm32_multiplier_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/jtag_tap/.jtag_tap_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_ddr_driver/.fd_ddr_driver_vhd
:
../../platform/fd_ddr_driver.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_ddr_pll/.fd_ddr_pll_vhd
:
../../platform/fd_ddr_pll.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_pkg/.wbgen2_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg_vhd
:
../../rtl/fd_channel_wbgen2_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_ts_adder/.fd_ts_adder_vhd
:
../../rtl/fd_ts_adder.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/genram_pkg/.genram_pkg_vhd
:
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gencores_pkg/.gencores_pkg_vhd
:
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gencores_pkg/.gencores_pkg
:
\
work/genram_pkg/.genram_pkg
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg_vhd
:
../../rtl/fd_main_wbgen2_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wishbone_pkg/.wishbone_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wishbone_pkg/.wishbone_pkg
:
\
work/genram_pkg/.genram_pkg
work/fine_delay_pkg/.fine_delay_pkg_vhd
:
../../rtl/fine_delay_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fine_delay_pkg/.fine_delay_pkg
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/fd_delay_line_arbiter/.fd_delay_line_arbiter_vhd
:
../../rtl/fd_delay_line_arbiter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_spi_master/.fd_spi_master_vhd
:
../../rtl/fd_spi_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_spi_dac_arbiter/.fd_spi_dac_arbiter_vhd
:
../../rtl/fd_spi_dac_arbiter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_spi_dac_arbiter/.fd_spi_dac_arbiter
:
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/fd_acam_timestamper/.fd_acam_timestamper_vhd
:
../../rtl/fd_acam_timestamper.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_acam_timestamper/.fd_acam_timestamper
:
\
work/fine_delay_pkg/.fine_delay_pkg
\
work/gencores_pkg/.gencores_pkg
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor_vhd
:
../../rtl/fd_acam_timestamp_postprocessor.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor
:
\
work/fine_delay_pkg/.fine_delay_pkg
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/fd_channel_wishbone_slave/.fd_channel_wishbone_slave_vhd
:
../../rtl/fd_channel_wishbone_slave.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_channel_wishbone_slave/.fd_channel_wishbone_slave
:
\
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit_vhd
:
../../rtl/fd_timestamper_stat_unit.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit
:
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/fd_delay_channel_driver/.fd_delay_channel_driver_vhd
:
../../rtl/fd_delay_channel_driver.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_delay_channel_driver/.fd_delay_channel_driver
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/fine_delay_pkg/.fine_delay_pkg
\
work/gencores_pkg/.gencores_pkg
\
work/fd_channel_wbgen2_pkg/.fd_channel_wbgen2_pkg
work/fd_ring_buffer/.fd_ring_buffer_vhd
:
../../rtl/fd_ring_buffer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_ring_buffer/.fd_ring_buffer
:
\
work/fine_delay_pkg/.fine_delay_pkg
\
work/genram_pkg/.genram_pkg
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/fd_dmtd_insertion_calibrator/.fd_dmtd_insertion_calibrator_vhd
:
../../rtl/fd_dmtd_insertion_calibrator.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_dmtd_insertion_calibrator/.fd_dmtd_insertion_calibrator
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/fine_delay_pkg/.fine_delay_pkg
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/fd_dmtd_with_deglitcher/.fd_dmtd_with_deglitcher_vhd
:
../../rtl/timing/fd_dmtd_with_deglitcher.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_dmtd_with_deglitcher/.fd_dmtd_with_deglitcher
:
\
work/gencores_pkg/.gencores_pkg
work/fd_hpll_period_detect/.fd_hpll_period_detect_vhd
:
../../rtl/timing/fd_hpll_period_detect.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_hpll_period_detect/.fd_hpll_period_detect
:
\
work/gencores_pkg/.gencores_pkg
work/fd_reset_generator/.fd_reset_generator_vhd
:
../../rtl/fd_reset_generator.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_reset_generator/.fd_reset_generator
:
\
work/gencores_pkg/.gencores_pkg
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/gc_crc_gen/.gc_crc_gen_vhd
:
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_crc_gen/.gc_crc_gen
:
\
work/gencores_pkg/.gencores_pkg
work/gc_moving_average/.gc_moving_average_vhd
:
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_moving_average/.gc_moving_average
:
\
work/gencores_pkg/.gencores_pkg
work/gc_extend_pulse/.gc_extend_pulse_vhd
:
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_extend_pulse/.gc_extend_pulse
:
\
work/gencores_pkg/.gencores_pkg
work/gc_delay_gen/.gc_delay_gen_vhd
:
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_delay_gen/.gc_delay_gen
:
\
work/gencores_pkg/.gencores_pkg
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd
:
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_dual_pi_controller/.gc_dual_pi_controller
:
\
work/gencores_pkg/.gencores_pkg
work/gc_serial_dac/.gc_serial_dac_vhd
:
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_sync_ffs/.gc_sync_ffs_vhd
:
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd
:
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_arbitrated_mux/.gc_arbitrated_mux
:
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd
:
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_pulse_synchronizer/.gc_pulse_synchronizer
:
\
work/gencores_pkg/.gencores_pkg
work/gc_frequency_meter/.gc_frequency_meter_vhd
:
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_frequency_meter/.gc_frequency_meter
:
\
work/gencores_pkg/.gencores_pkg
work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd
:
../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_wfifo/.gc_wfifo_vhd
:
../../ip_cores/general-cores/modules/common/gc_wfifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_wfifo/.gc_wfifo
:
\
work/gencores_pkg/.gencores_pkg
work/fd_csync_generator/.fd_csync_generator_vhd
:
../../rtl/fd_csync_generator.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_csync_generator/.fd_csync_generator
:
\
work/fine_delay_pkg/.fine_delay_pkg
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/memory_loader_pkg/.memory_loader_pkg_vhd
:
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/memory_loader_pkg/.memory_loader_pkg
:
\
work/genram_pkg/.genram_pkg
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_shiftreg_fifo/.generic_shiftreg_fifo
:
\
work/genram_pkg/.genram_pkg
work/fine_delay_core/.fine_delay_core_vhd
:
../../rtl/fine_delay_core.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fine_delay_core/.fine_delay_core
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/fine_delay_pkg/.fine_delay_pkg
\
work/gencores_pkg/.gencores_pkg
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
work/generic_async_fifo/.generic_async_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_async_fifo/.generic_async_fifo
:
\
work/genram_pkg/.genram_pkg
work/generic_dpram/.generic_dpram_vhd
:
../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_dpram/.generic_dpram
:
\
work/memory_loader_pkg/.memory_loader_pkg
\
work/genram_pkg/.genram_pkg
work/generic_spram/.generic_spram_vhd
:
../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_spram/.generic_spram
:
\
work/genram_pkg/.genram_pkg
work/generic_sync_fifo/.generic_sync_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_sync_fifo/.generic_sync_fifo
:
\
work/genram_pkg/.genram_pkg
work/wb_async_bridge/.wb_async_bridge_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_async_bridge/.wb_async_bridge
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_async_bridge/.xwb_async_bridge_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_async_bridge/.xwb_async_bridge
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_onewire_master/.wb_onewire_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_onewire_master/.wb_onewire_master
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_onewire_master/.xwb_onewire_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_onewire_master/.xwb_onewire_master
:
\
work/wishbone_pkg/.wishbone_pkg
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/i2c_master_top/.i2c_master_top_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_i2c_master/.wb_i2c_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_i2c_master/.wb_i2c_master
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_i2c_master/.xwb_i2c_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_i2c_master/.xwb_i2c_master
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_bus_fanout/.xwb_bus_fanout_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_bus_fanout/.xwb_bus_fanout
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_dpram/.xwb_dpram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_dpram/.xwb_dpram
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/genram_pkg/.genram_pkg
work/wb_gpio_port/.wb_gpio_port_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_gpio_port/.wb_gpio_port
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_gpio_port/.xwb_gpio_port_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_gpio_port/.xwb_gpio_port
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_tics/.wb_tics_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_tics/.wb_tics
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_tics/.xwb_tics_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_tics/.xwb_tics
:
\
work/wishbone_pkg/.wishbone_pkg
work/uart_async_rx/.uart_async_rx_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/uart_async_tx/.uart_async_tx_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/uart_baud_gen/.uart_baud_gen_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_uart_pkg/.simple_uart_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_uart_wb/.simple_uart_wb_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_uart_wb/.simple_uart_wb
:
\
work/simple_uart_pkg/.simple_uart_pkg
work/wb_simple_uart/.wb_simple_uart_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_simple_uart/.wb_simple_uart
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/genram_pkg/.genram_pkg
\
work/simple_uart_pkg/.simple_uart_pkg
work/xwb_simple_uart/.xwb_simple_uart_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_simple_uart/.xwb_simple_uart
:
\
work/wishbone_pkg/.wishbone_pkg
work/vic_prio_enc/.vic_prio_enc_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_slave_vic/.wb_slave_vic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_slave_vic/.wb_slave_vic
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wb_vic/.wb_vic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_vic/.wb_vic
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_vic/.xwb_vic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_vic/.xwb_vic
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_spi/.wb_spi_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_spi/.wb_spi
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_spi/.xwb_spi_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_spi/.xwb_spi
:
\
work/wishbone_pkg/.wishbone_pkg
work/sdwb_rom/.sdwb_rom_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdwb_rom.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/sdwb_rom/.sdwb_rom
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_crossbar/.xwb_crossbar_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_crossbar/.xwb_crossbar
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_sdwb_crossbar/.xwb_sdwb_crossbar_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdwb_crossbar.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_sdwb_crossbar/.xwb_sdwb_crossbar
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_lm32/.xwb_lm32_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_lm32/.xwb_lm32
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_slave_adapter/.wb_slave_adapter_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_slave_adapter/.wb_slave_adapter
:
\
work/wishbone_pkg/.wishbone_pkg
work/xloader_registers_pkg/.xloader_registers_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xloader_registers_pkg/.xloader_registers_pkg
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
\
work/xloader_registers_pkg/.xloader_registers_pkg
work/xloader_wb/.xloader_wb_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xloader_wb/.xloader_wb
:
\
work/wbgen2_pkg/.wbgen2_pkg
\
work/xloader_registers_pkg/.xloader_registers_pkg
work/xwb_clock_crossing/.xwb_clock_crossing_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_clock_crossing/.xwb_clock_crossing
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_dma/.xwb_dma_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_dma/.xwb_dma
:
\
work/wishbone_pkg/.wishbone_pkg
work/wbgen2_dpssram/.wbgen2_dpssram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_dpssram/.wbgen2_dpssram
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_eic/.wbgen2_eic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_eic/.wbgen2_eic
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_fifo_async/.wbgen2_fifo_async
:
\
work/genram_pkg/.genram_pkg
\
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_fifo_sync/.wbgen2_fifo_sync
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/fd_main_wishbone_slave/.fd_main_wishbone_slave_vhd
:
../../rtl/fd_main_wishbone_slave.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fd_main_wishbone_slave/.fd_main_wishbone_slave
:
\
work/wbgen2_pkg/.wbgen2_pkg
\
work/fd_main_wbgen2_pkg/.fd_main_wbgen2_pkg
hdl/testbench/old_top/Manifest.py
View file @
4160f44e
target
=
"xilinx"
action
=
"simulation"
vlog_opt
=
"+incdir+../../include +incdir+../../include/wb"
...
...
hdl/testbench/old_top/main.sv
View file @
4160f44e
`timescale
10
fs
/
10
fs
`include
"acam_model.sv"
`include
"tunable_clock_gen.sv"
`include
"random_pulse_gen.sv"
`include
"jittery_delay.sv"
`include
"ideal_timestamper.sv"
`include
"mc100ep195.
sv
"
`include
"acam_model.sv
h
"
`include
"tunable_clock_gen.sv
h
"
`include
"random_pulse_gen.sv
h
"
`include
"jittery_delay.sv
h
"
`include
"ideal_timestamper.sv
h
"
`include
"mc100ep195.
vh
"
`include
"regs/fd_main_regs.vh"
`include
"regs/fd_channel_regs.vh"
...
...
@@ -31,7 +31,7 @@ module clock_reset_gen
output
reg
rst_n_o
)
;
parameter
real
g_ref_period
=
8
ns
;
parameter
real
g_dmtd_period
=
8.31
ns
;
parameter
real
g_dmtd_period
=
15.9
ns
;
parameter
real
g_sys_period
=
16.31
ns
;
parameter
real
g_ref_jitter
=
10
ps
;
parameter
real
g_tdc_jitter
=
10
ps
;
...
...
@@ -100,6 +100,9 @@ const int SPI_PLL = 0;
const
int
SPI_GPIO
=
1
;
const
int
SPI_DAC
=
2
;
int
dly_seed
=
10
;
class
CSimDrv_FineDelay
;
protected
CBusAccessor
m_acc
;
protected
VIAcamDirect
m_acam
;
...
...
@@ -181,23 +184,22 @@ class CSimDrv_FineDelay;
end
endtask
// set_reference
task
rbuf_update
()
;
Timestamp
ts
;
uint64_t
utc
,
coarse
,
seq_frac
,
stat
,
sech
,
secl
;
m_acc
.
read
(
`ADDR_FD_TSBCR
,
stat
)
;
// $display("TSBCR %x\n", stat);
if
((
stat
&
`FD_TSBCR_EMPTY
)
==
0
)
begin
m_acc
.
write
(
`ADDR_FD_TSBR_ADVANCE
,
1
)
;
m_acc
.
read
(
`ADDR_FD_TSBR_SECH
,
sech
)
;
m_acc
.
read
(
`ADDR_FD_TSBR_SECL
,
secl
)
;
m_acc
.
read
(
`ADDR_FD_TSBR_CYCLES
,
coarse
)
;
m_acc
.
read
(
`ADDR_FD_TSBR_FID
,
seq_frac
)
;
ts
=
new
(
0
,
0
,
0
)
;
ts
.
source
=
seq_frac
&
'h7
;
...
...
@@ -264,20 +266,13 @@ class CSimDrv_FineDelay;
if
(
mode
==
PULSE_GEN
)
dcr
|=
`FD_DCR_MODE
;
if
((
width_ps
<
200000
)
||
(((
delta_ps
-
width_ps
)
<
150000
)
&&
(
rep_count
>
1
)))
begin
dcr
|=
`FD_DCR_NO_FINE
;
$
display
(
"NoFine!"
)
;
end
dcr
|=
`FD_DCR_NO_FINE
;
m_acc
.
write
(
'h100
+
'h100
*
channel
+
`ADDR_FD_DCR
,
dcr
)
;
if
(
mode
==
PULSE_GEN
)
m_acc
.
write
(
'h100
+
'h100
*
channel
+
`ADDR_FD_DCR
,
dcr
|
`FD_DCR_PG_ARM
)
;
endtask
// config_output
task
init
()
;
int
rval
;
Timestamp
t
=
new
;
...
...
@@ -291,42 +286,31 @@ class CSimDrv_FineDelay;
acam_write
(
5
,
c_acam_start_offset
)
;
// set StartOffset
acam_read
(
5
,
rval
)
;
$
display
(
"AcamReadback %x"
,
rval
)
;
m_acam
.
addr
=
8
;
/* permanently select FIFO1 */
// Clear the ring buffer
m_acc
.
write
(
`ADDR_FD_TSBCR
,
`FD_TSBCR_ENABLE
|
`FD_TSBCR_PURGE
|
`FD_TSBCR_RST_SEQ
|
(
3
<<
`FD_TSBCR_CHAN_MASK_OFFSET
))
;
m_acc
.
write
(
`ADDR_FD_ADSFR
,
int
'
(
real
'
(
1
<<
(
c_frac_bits
+
c_scaler_shift
))
*
c_acam_bin
/
c_ref_period
))
;
$
display
(
"ADSFR: %d"
,
int
'
(
real
'
(
1
<<
(
c_frac_bits
+
c_scaler_shift
))
*
c_acam_bin
/
c_ref_period
))
;
m_acc
.
write
(
`ADDR_FD_ASOR
,
c_acam_start_offset
*
3
)
;
m_acc
.
write
(
`ADDR_FD_ATMCR
,
c_acam_merge_c_threshold
|
(
c_acam_merge_f_threshold
<<
4
))
;
// Enable trigger input
m_acc
.
write
(
`ADDR_FD_GCR
,
0
)
;
t
.
utc
=
1
;
t
.
coarse
=
100
0
;
t
.
utc
=
0
;
t
.
coarse
=
0
;
set_time
(
t
)
;
// get_time(t);
// Enable trigger input
m_acc
.
write
(
`ADDR_FD_GCR
,
`FD_GCR_INPUT_EN
)
;
endtask
// init
task
force_cal_pulse
(
int
channel
,
int
delay_setpoint
)
;
m_acc
.
write
(
`ADDR_FD_FRR
+
(
channel
*
'h20
)
,
delay_setpoint
)
;
m_acc
.
write
(
`ADDR_FD_DCR
+
(
channel
*
'h20
)
,
`FD_DCR_FORCE_DLY
)
;
m_acc
.
write
(
`ADDR_FD_CALR
,
`FD_CALR_CAL_PULSE
|
((
1
<<
channel
)
<<
`FD_CALR_PSEL_OFFSET
))
;
endtask
// force_cal_pulse
endclass
// CSimDrv_FineDelay
...
...
@@ -440,8 +424,8 @@ module main;
random_pulse_gen
#(
.
g_pulse_width
(
40
ns
)
,
.
g_min_spacing
(
1
00.111
ns
)
,
.
g_max_spacing
(
10
0.112
ns
)
.
g_min_spacing
(
50
00.111
ns
)
,
.
g_max_spacing
(
501
0.112
ns
)
)
TRIG_GEN
(
...
...
@@ -547,7 +531,7 @@ module main;
fine_delay_core
#(
.
g_simulation
(
1
)
,
.
g_with_wr_core
(
0
))
.
g_with_wr_core
(
1
))
DUT
(
.
clk_ref_0_i
(
clk_ref
)
,
.
clk_ref_180_i
(
~
clk_ref
)
,
...
...
@@ -660,10 +644,9 @@ module main;
dmtd_fb_in
<=
~
trig_a_muxed
;
dmtd_out_chx
[
0
]
<=
~
d_out
[
0
]
;
dmtd_out_chx
[
1
]
<=
~
d_out
[
1
]
;
end
assign
dmtd_fb_out
=
dmtd_out_chx
[
0
]
&
dmtd_out_chx
[
1
]
;
assign
dmtd_fb_out
=
dmtd_out_chx
[
0
]
&
dmtd_out_chx
[
1
]
;
always
@
(
posedge
clk_ref
)
...
...
@@ -697,64 +680,41 @@ module main;
fd_drv
.
init
()
;
fd_drv
.
get_time
(
t_cur
)
;
//fd_drv.set_reference(0
);
fd_drv
.
set_reference
(
1
)
;
$
display
(
"GetTime: %d:%d"
,
t_cur
.
utc
,
t_cur
.
coarse
)
;
t_cur
.
utc
=
0
;
t_cur
.
frac
=
0
;
t_cur
.
coarse
=
500
/
8
;
fd_drv
.
config_output
(
0
,
CSimDrv_FineDelay
::
DELAY
,
1
,
t_cur
,
100000
,
100000
,
3
)
;
t_cur
.
unflatten
(
600000.0
*
4096.0
/
8000.0
)
;
fd_drv
.
config_output
(
0
,
CSimDrv_FineDelay
::
DELAY
,
1
,
t_cur
,
200000
,
100000
,
1
)
;
wb
.
write
(
`ADDR_FD_CALR
,
`FD_CALR_CAL_DMTD
)
;
trig_cal_sel
=
0
;
// fd_drv.config_output(1,1, 1100500, 200000);
// fd_drv.config_output(2,1, 1100900, 200000);
// fd_drv.config_output(3,1, 1110100, 200000);
// fd_drv.force_cal_pulse(0, 100);
// #(320ns);
// fd_drv.force_cal_pulse(0, 200);
// forever fd_drv.rbuf_update();
forever
fd_drv
.
rbuf_update
()
;
end
Timestamp
prev
=
null
;
int
prev_seqid
=
-
1
;
always
@
(
posedge
clk_ref
)
if
(
fd_drv
!=
null
)
begin
if
(
fd_drv
.
poll
()
&&
IDEAL_TSU
.
poll
()
&&
Output_TSU0
.
poll
()
/* && Output_TSU1.poll()*/
)
if
(
fd_drv
.
poll
())
begin
real
delta
,
delta2
,
delta3
;
Timestamp
t_acam
;
Timestamp
t_ideal
;
Timestamp
t_out0
,
t_out1
;
t_acam
=
fd_drv
.
get
()
;
t_ideal
=
IDEAL_TSU
.
get
()
;
t_out0
=
Output_TSU0
.
get
()
;
// t_out1 = Output_TSU1.get();
delta
=
t_acam
.
flatten
()
-
t_ideal
.
flatten
()
;
delta2
=
t_out0
.
flatten
()
-
t_ideal
.
flatten
()
;
// delta3 = t_out1.flatten() - t_ideal.flatten();
$
display
(
"TS: seq %d [%d:%d:%d src %d] delta %.4f delta_out %.4f %.4f"
,
t_acam
.
seq_id
,
t_acam
.
utc
,
t_acam
.
coarse
,
t_acam
.
frac
,
t_acam
.
source
,
delta
,
delta2
,
delta3
)
;
if
(
delta
>
0.1
||
delta
<
-
0.1
)
$
display
(
"TS: seq %d [%d:%d:%d src %d]"
,
t_acam
.
seq_id
,
t_acam
.
utc
,
t_acam
.
coarse
,
t_acam
.
frac
,
t_acam
.
source
)
;
if
((
prev_seqid
+
1
)
&
'hffff
!=
t_acam
.
seq_id
)
begin
// $display("TS Failure
");
//
$stop;
$
error
(
"Seqid mismatch
"
)
;
$
stop
;
end
end
end
...
...
hdl/testbench/old_top/wave.do
View file @
4160f44e
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_with_internal_timebase
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_clk_sys_freq
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_counter_bits
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/clk_sys_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/clk_in_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/rst_n_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/pps_p1_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_o
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_valid_o
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/gate_pulse
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/gate_pulse_synced
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/cntr_gate
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/cntr_meas
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_reg
add wave -noupdate /main/DUT/chx_delay_pulse0
add wave -noupdate /main/DUT/chx_delay_pulse1
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {
814532520
0 fs} 0}
WaveRestoreCursors {{Cursor 1} {
6452419355
0 fs} 0}
configure wave -namecolwidth 183
configure wave -valuecolwidth 100
configure wave -justifyvalue left
...
...
@@ -30,4 +18,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {
26250 n
s}
WaveRestoreZoom {0 fs} {
840 u
s}
hdl/testbench/svec_wr_top/main.sv
View file @
4160f44e
...
...
@@ -130,7 +130,7 @@ module main;
init_vme64x_core
(
acc
)
;
acc_casted
.
set_default_xfer_size
(
A32
|
SINGLE
|
D32
)
;
drv0
=
new
(
acc
,
'h
4
0000
)
;
drv0
=
new
(
acc
,
'h
1
0000
)
;
drv0
.
init
()
;
dly
=
new
;
...
...
hdl/testbench/svec_wr_top/wave.do
View file @
4160f44e
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/U_VME_Core/master_o
add wave -noupdate /main/DUT/U_VME_Core/master_i
add wave -noupdate /main/DUT/g_with_wr_phy
add wave -noupdate /main/DUT/g_simulation
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_p_i
add wave -noupdate /main/DUT/clk_125m_gtp_n_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/VME_AS_n_i
add wave -noupdate /main/DUT/VME_RST_n_i
add wave -noupdate /main/DUT/VME_WRITE_n_i
add wave -noupdate /main/DUT/VME_AM_i
add wave -noupdate /main/DUT/VME_DS_n_i
add wave -noupdate /main/DUT/VME_GA_i
add wave -noupdate /main/DUT/VME_BERR_o
add wave -noupdate /main/DUT/VME_DTACK_n_o
add wave -noupdate /main/DUT/VME_RETRY_n_o
add wave -noupdate /main/DUT/VME_RETRY_OE_o
add wave -noupdate /main/DUT/VME_LWORD_n_b
add wave -noupdate /main/DUT/VME_ADDR_b
add wave -noupdate /main/DUT/VME_DATA_b
add wave -noupdate /main/DUT/VME_BBSY_n_i
add wave -noupdate /main/DUT/VME_IRQ_n_o
add wave -noupdate /main/DUT/VME_IACK_n_i
add wave -noupdate /main/DUT/VME_IACKIN_n_i
add wave -noupdate /main/DUT/VME_IACKOUT_n_o
add wave -noupdate /main/DUT/VME_DTACK_OE_o
add wave -noupdate /main/DUT/VME_DATA_DIR_o
add wave -noupdate /main/DUT/VME_DATA_OE_N_o
add wave -noupdate /main/DUT/VME_ADDR_DIR_o
add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/fmc0_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc1_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc0_scl_b
add wave -noupdate /main/DUT/fmc0_sda_b
add wave -noupdate /main/DUT/fmc1_scl_b
add wave -noupdate /main/DUT/fmc1_sda_b
add wave -noupdate /main/DUT/pll20dac_din_o
add wave -noupdate /main/DUT/pll20dac_sclk_o
add wave -noupdate /main/DUT/pll20dac_sync_n_o
add wave -noupdate /main/DUT/pll25dac_din_o
add wave -noupdate /main/DUT/pll25dac_sclk_o
add wave -noupdate /main/DUT/pll25dac_sync_n_o
add wave -noupdate /main/DUT/tempid_dq_b
add wave -noupdate /main/DUT/fp_ledn_o
add wave -noupdate /main/DUT/fd0_tdc_start_p_i
add wave -noupdate /main/DUT/fd0_tdc_start_n_i
add wave -noupdate /main/DUT/fd0_clk_ref_p_i
add wave -noupdate /main/DUT/fd0_clk_ref_n_i
add wave -noupdate /main/DUT/fd0_trig_a_i
add wave -noupdate /main/DUT/fd0_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd0_tdc_d_b
add wave -noupdate /main/DUT/fd0_tdc_emptyf_i
add wave -noupdate /main/DUT/fd0_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd0_tdc_wr_n_o
add wave -noupdate /main/DUT/fd0_tdc_rd_n_o
add wave -noupdate /main/DUT/fd0_tdc_oe_n_o
add wave -noupdate /main/DUT/fd0_led_trig_o
add wave -noupdate /main/DUT/fd0_tdc_start_dis_o
add wave -noupdate /main/DUT/fd0_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd0_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd0_spi_sclk_o
add wave -noupdate /main/DUT/fd0_spi_mosi_o
add wave -noupdate /main/DUT/fd0_spi_miso_i
add wave -noupdate /main/DUT/fd0_delay_len_o
add wave -noupdate /main/DUT/fd0_delay_val_o
add wave -noupdate /main/DUT/fd0_delay_pulse_o
add wave -noupdate /main/DUT/fd0_dmtd_clk_o
add wave -noupdate /main/DUT/fd0_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd0_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd0_pll_status_i
add wave -noupdate /main/DUT/fd0_ext_rst_n_o
add wave -noupdate /main/DUT/fd0_onewire_b
add wave -noupdate /main/DUT/fd1_tdc_start_p_i
add wave -noupdate /main/DUT/fd1_tdc_start_n_i
add wave -noupdate /main/DUT/fd1_clk_ref_p_i
add wave -noupdate /main/DUT/fd1_clk_ref_n_i
add wave -noupdate /main/DUT/fd1_trig_a_i
add wave -noupdate /main/DUT/fd1_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd1_tdc_d_b
add wave -noupdate /main/DUT/fd1_tdc_emptyf_i
add wave -noupdate /main/DUT/fd1_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd1_tdc_wr_n_o
add wave -noupdate /main/DUT/fd1_tdc_rd_n_o
add wave -noupdate /main/DUT/fd1_tdc_oe_n_o
add wave -noupdate /main/DUT/fd1_led_trig_o
add wave -noupdate /main/DUT/fd1_tdc_start_dis_o
add wave -noupdate /main/DUT/fd1_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd1_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd1_spi_sclk_o
add wave -noupdate /main/DUT/fd1_spi_mosi_o
add wave -noupdate /main/DUT/fd1_spi_miso_i
add wave -noupdate /main/DUT/fd1_delay_len_o
add wave -noupdate /main/DUT/fd1_delay_val_o
add wave -noupdate /main/DUT/fd1_delay_pulse_o
add wave -noupdate /main/DUT/fd1_dmtd_clk_o
add wave -noupdate /main/DUT/fd1_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd1_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd1_pll_status_i
add wave -noupdate /main/DUT/fd1_ext_rst_n_o
add wave -noupdate /main/DUT/fd1_onewire_b
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/VME_DATA_b_out
add wave -noupdate /main/DUT/VME_ADDR_b_out
add wave -noupdate /main/DUT/VME_LWORD_n_b_out
add wave -noupdate /main/DUT/VME_DATA_DIR_int
add wave -noupdate /main/DUT/VME_ADDR_DIR_int
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate /main/DUT/dcm0_clk_ref_0
add wave -noupdate /main/DUT/dcm0_clk_ref_180
add wave -noupdate /main/DUT/fd0_tdc_start
add wave -noupdate /main/DUT/tdc0_data_out
add wave -noupdate /main/DUT/tdc0_data_in
add wave -noupdate /main/DUT/tdc0_data_oe
add wave -noupdate /main/DUT/dcm1_clk_ref_0
add wave -noupdate /main/DUT/dcm1_clk_ref_180
add wave -noupdate /main/DUT/fd1_tdc_start
add wave -noupdate /main/DUT/tdc1_data_out
add wave -noupdate /main/DUT/tdc1_data_in
add wave -noupdate /main/DUT/tdc1_data_oe
add wave -noupdate /main/DUT/tm_link_up
add wave -noupdate /main/DUT/tm_utc
add wave -noupdate /main/DUT/tm_cycles
add wave -noupdate /main/DUT/tm_time_valid
add wave -noupdate /main/DUT/tm0_clk_aux_lock_en
add wave -noupdate /main/DUT/tm0_clk_aux_locked
add wave -noupdate /main/DUT/tm1_clk_aux_lock_en
add wave -noupdate /main/DUT/tm1_clk_aux_locked
add wave -noupdate /main/DUT/tm_dac_value
add wave -noupdate /main/DUT/tm0_dac_wr
add wave -noupdate /main/DUT/tm1_dac_wr
add wave -noupdate /main/DUT/ddr0_pll_reset
add wave -noupdate /main/DUT/ddr0_pll_locked
add wave -noupdate /main/DUT/fd0_pll_status
add wave -noupdate /main/DUT/ddr1_pll_reset
add wave -noupdate /main/DUT/ddr1_pll_locked
add wave -noupdate /main/DUT/fd1_pll_status
add wave -noupdate /main/DUT/wrc_scl_out
add wave -noupdate /main/DUT/wrc_scl_in
add wave -noupdate /main/DUT/wrc_sda_out
add wave -noupdate /main/DUT/wrc_sda_in
add wave -noupdate /main/DUT/fd0_scl_out
add wave -noupdate /main/DUT/fd0_scl_in
add wave -noupdate /main/DUT/fd0_sda_out
add wave -noupdate /main/DUT/fd0_sda_in
add wave -noupdate /main/DUT/fd1_scl_out
add wave -noupdate /main/DUT/fd1_scl_in
add wave -noupdate /main/DUT/fd1_sda_out
add wave -noupdate /main/DUT/fd1_sda_in
add wave -noupdate /main/DUT/sfp_scl_out
add wave -noupdate /main/DUT/sfp_scl_in
add wave -noupdate /main/DUT/sfp_sda_out
add wave -noupdate /main/DUT/sfp_sda_in
add wave -noupdate /main/DUT/wrc_owr_en
add wave -noupdate /main/DUT/wrc_owr_in
add wave -noupdate /main/DUT/fd0_owr_en
add wave -noupdate /main/DUT/fd0_owr_in
add wave -noupdate /main/DUT/fd1_owr_en
add wave -noupdate /main/DUT/fd1_owr_in
add wave -noupdate /main/DUT/fd0_irq
add wave -noupdate /main/DUT/fd1_irq
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_125m_gtp
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/local_reset_n
add wave -noupdate /main/DUT/vme_master_out
add wave -noupdate /main/DUT/vme_master_in
add wave -noupdate /main/DUT/pins
add wave -noupdate /main/DUT/rst_n_a
add wave -noupdate /main/DUT/pps
add wave -noupdate /main/DUT/led_divider
add wave -noupdate /main/DUT/leds
add wave -noupdate /main/DUT/etherbone_rst_n
add wave -noupdate /main/DUT/etherbone_src_out
add wave -noupdate /main/DUT/etherbone_src_in
add wave -noupdate /main/DUT/etherbone_snk_out
add wave -noupdate /main/DUT/etherbone_snk_in
add wave -noupdate /main/DUT/etherbone_cfg_in
add wave -noupdate /main/DUT/etherbone_cfg_out
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {23693000000 fs} 0}
configure wave -namecolwidth 183
...
...
@@ -18,4 +235,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {
49151514620 fs} {59369721
340 fs}
WaveRestoreZoom {
2400011620 fs} {12618218
340 fs}
Write
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