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FMC DEL 1ns 4cha
Commit 4160f44e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/testbench: minor fixes

parent 36e07dc3
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Showing with 263 additions and 1091 deletions
hdl/testbench/old_top/Makefile deleted 100644 → 0
View file @ 36e07dc3
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hdl/testbench/old_top/Manifest.py
View file @ 4160f44e
target = "xilinx"
action = "simulation"
vlog_opt="+incdir+../../include +incdir+../../include/wb"
......
hdl/testbench/old_top/main.sv
View file @ 4160f44e
`timescale 10fs/10fs
`include "acam_model.sv"
`include "tunable_clock_gen.sv"
`include "random_pulse_gen.sv"
`include "jittery_delay.sv"
`include "ideal_timestamper.sv"
`include "mc100ep195.sv"
`include "acam_model.svh"
`include "tunable_clock_gen.svh"
`include "random_pulse_gen.svh"
`include "jittery_delay.svh"
`include "ideal_timestamper.svh"
`include "mc100ep195.vh"
`include "regs/fd_main_regs.vh"
`include "regs/fd_channel_regs.vh"
......@@ -31,7 +31,7 @@ module clock_reset_gen
output reg rst_n_o);
parameter real g_ref_period = 8ns;
parameter real g_dmtd_period = 8.31ns;
parameter real g_dmtd_period = 15.9ns;
parameter real g_sys_period = 16.31ns;
parameter real g_ref_jitter = 10ps;
parameter real g_tdc_jitter = 10ps;
......@@ -100,6 +100,9 @@ const int SPI_PLL = 0;
const int SPI_GPIO = 1;
const int SPI_DAC = 2;
int dly_seed= 10;
class CSimDrv_FineDelay;
protected CBusAccessor m_acc;
protected VIAcamDirect m_acam;
......@@ -181,23 +184,22 @@ class CSimDrv_FineDelay;
end
endtask // set_reference
task rbuf_update();
Timestamp ts;
uint64_t utc, coarse, seq_frac, stat, sech, secl;
m_acc.read(`ADDR_FD_TSBCR, stat);
// $display("TSBCR %x\n", stat);
if((stat & `FD_TSBCR_EMPTY) == 0) begin
m_acc.write(`ADDR_FD_TSBR_ADVANCE, 1);
m_acc.read(`ADDR_FD_TSBR_SECH, sech);
m_acc.read(`ADDR_FD_TSBR_SECL, secl);
m_acc.read(`ADDR_FD_TSBR_CYCLES, coarse);
m_acc.read(`ADDR_FD_TSBR_FID, seq_frac);
ts = new (0,0,0);
ts.source = seq_frac & 'h7;
......@@ -264,20 +266,13 @@ class CSimDrv_FineDelay;
if(mode == PULSE_GEN)
dcr |= `FD_DCR_MODE;
if((width_ps < 200000) || (((delta_ps-width_ps) < 150000) && (rep_count > 1)))
begin
dcr |= `FD_DCR_NO_FINE;
$display("NoFine!");
end
dcr |= `FD_DCR_NO_FINE;
m_acc.write('h100 + 'h100 * channel + `ADDR_FD_DCR, dcr);
if(mode == PULSE_GEN)
m_acc.write('h100 + 'h100 * channel + `ADDR_FD_DCR, dcr | `FD_DCR_PG_ARM);
endtask // config_output
task init();
int rval;
Timestamp t = new;
......@@ -291,42 +286,31 @@ class CSimDrv_FineDelay;
acam_write(5, c_acam_start_offset); // set StartOffset
acam_read(5, rval);
$display("AcamReadback %x", rval);
m_acam.addr= 8; /* permanently select FIFO1 */
// Clear the ring buffer
m_acc.write(`ADDR_FD_TSBCR, `FD_TSBCR_ENABLE | `FD_TSBCR_PURGE | `FD_TSBCR_RST_SEQ | (3 << `FD_TSBCR_CHAN_MASK_OFFSET));
m_acc.write(`ADDR_FD_ADSFR, int' (real'(1<< (c_frac_bits + c_scaler_shift)) * c_acam_bin / c_ref_period));
$display("ADSFR: %d", int' (real'(1<< (c_frac_bits + c_scaler_shift)) * c_acam_bin / c_ref_period));
m_acc.write(`ADDR_FD_ASOR, c_acam_start_offset * 3);
m_acc.write(`ADDR_FD_ATMCR, c_acam_merge_c_threshold | (c_acam_merge_f_threshold << 4));
// Enable trigger input
m_acc.write(`ADDR_FD_GCR, 0);
t.utc = 1;
t.coarse = 1000;
t.utc = 0;
t.coarse = 0;
set_time(t);
// get_time(t);
// Enable trigger input
m_acc.write(`ADDR_FD_GCR, `FD_GCR_INPUT_EN);
endtask // init
task force_cal_pulse(int channel, int delay_setpoint);
m_acc.write(`ADDR_FD_FRR + (channel * 'h20), delay_setpoint);
m_acc.write(`ADDR_FD_DCR + (channel * 'h20), `FD_DCR_FORCE_DLY);
m_acc.write(`ADDR_FD_CALR, `FD_CALR_CAL_PULSE | ((1<<channel) << `FD_CALR_PSEL_OFFSET));
endtask // force_cal_pulse
endclass // CSimDrv_FineDelay
......@@ -440,8 +424,8 @@ module main;
random_pulse_gen
#(
.g_pulse_width(40ns),
.g_min_spacing(100.111ns),
.g_max_spacing(100.112ns)
.g_min_spacing(5000.111ns),
.g_max_spacing(5010.112ns)
)
TRIG_GEN
(
......@@ -547,7 +531,7 @@ module main;
fine_delay_core
#(
.g_simulation(1),
.g_with_wr_core(0))
.g_with_wr_core(1))
DUT (
.clk_ref_0_i(clk_ref),
.clk_ref_180_i(~clk_ref),
......@@ -660,10 +644,9 @@ module main;
dmtd_fb_in <= ~trig_a_muxed;
dmtd_out_chx[0] <= ~d_out[0];
dmtd_out_chx[1] <= ~d_out[1];
end
assign dmtd_fb_out = dmtd_out_chx[0] & dmtd_out_chx[1];
assign dmtd_fb_out = dmtd_out_chx[0] & dmtd_out_chx[1];
always@(posedge clk_ref)
......@@ -697,64 +680,41 @@ module main;
fd_drv.init();
fd_drv.get_time(t_cur);
//fd_drv.set_reference(0);
fd_drv.set_reference(1);
$display("GetTime: %d:%d",t_cur.utc, t_cur.coarse);
t_cur.utc= 0 ;
t_cur.frac = 0;
t_cur.coarse = 500/8;
fd_drv.config_output(0, CSimDrv_FineDelay::DELAY, 1, t_cur, 100000, 100000, 3);
t_cur.unflatten(600000.0 * 4096.0 / 8000.0);
fd_drv.config_output(0, CSimDrv_FineDelay::DELAY, 1, t_cur, 200000, 100000, 1);
wb.write(`ADDR_FD_CALR, `FD_CALR_CAL_DMTD);
trig_cal_sel = 0;
// fd_drv.config_output(1,1, 1100500, 200000);
// fd_drv.config_output(2,1, 1100900, 200000);
// fd_drv.config_output(3,1, 1110100, 200000);
// fd_drv.force_cal_pulse(0, 100);
// #(320ns);
// fd_drv.force_cal_pulse(0, 200);
// forever fd_drv.rbuf_update();
forever fd_drv.rbuf_update();
end
Timestamp prev = null;
int prev_seqid = -1;
always@(posedge clk_ref)
if (fd_drv != null)
begin
if(fd_drv.poll() && IDEAL_TSU.poll() && Output_TSU0.poll()/* && Output_TSU1.poll()*/)
if(fd_drv.poll())
begin
real delta, delta2, delta3;
Timestamp t_acam;
Timestamp t_ideal;
Timestamp t_out0, t_out1;
t_acam = fd_drv.get();
t_ideal = IDEAL_TSU.get();
t_out0 = Output_TSU0.get();
// t_out1 = Output_TSU1.get();
delta = t_acam.flatten() - t_ideal.flatten();
delta2 = t_out0.flatten() - t_ideal.flatten();
// delta3 = t_out1.flatten() - t_ideal.flatten();
$display("TS: seq %d [%d:%d:%d src %d] delta %.4f delta_out %.4f %.4f", t_acam.seq_id, t_acam.utc, t_acam.coarse, t_acam.frac, t_acam.source, delta, delta2, delta3);
if(delta > 0.1 || delta < -0.1)
$display("TS: seq %d [%d:%d:%d src %d]", t_acam.seq_id, t_acam.utc, t_acam.coarse, t_acam.frac, t_acam.source);
if((prev_seqid+1)&'hffff != t_acam.seq_id)
begin
// $display("TS Failure");
// $stop;
$error("Seqid mismatch");
$stop;
end
end
end
......
hdl/testbench/old_top/wave.do
View file @ 4160f44e
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_with_internal_timebase
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_clk_sys_freq
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_counter_bits
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/clk_sys_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/clk_in_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/rst_n_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/pps_p1_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_o
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_valid_o
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/gate_pulse
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/gate_pulse_synced
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/cntr_gate
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/cntr_meas
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_reg
add wave -noupdate /main/DUT/chx_delay_pulse0
add wave -noupdate /main/DUT/chx_delay_pulse1
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8145325200 fs} 0}
WaveRestoreCursors {{Cursor 1} {64524193550 fs} 0}
configure wave -namecolwidth 183
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -30,4 +18,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {26250 ns}
WaveRestoreZoom {0 fs} {840 us}
hdl/testbench/svec_wr_top/main.sv
View file @ 4160f44e
......@@ -130,7 +130,7 @@ module main;
init_vme64x_core(acc);
acc_casted.set_default_xfer_size(A32|SINGLE|D32);
drv0 = new(acc, 'h40000);
drv0 = new(acc, 'h10000);
drv0.init();
dly=new;
......
hdl/testbench/svec_wr_top/wave.do
View file @ 4160f44e
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/U_VME_Core/master_o
add wave -noupdate /main/DUT/U_VME_Core/master_i
add wave -noupdate /main/DUT/g_with_wr_phy
add wave -noupdate /main/DUT/g_simulation
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_p_i
add wave -noupdate /main/DUT/clk_125m_gtp_n_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/VME_AS_n_i
add wave -noupdate /main/DUT/VME_RST_n_i
add wave -noupdate /main/DUT/VME_WRITE_n_i
add wave -noupdate /main/DUT/VME_AM_i
add wave -noupdate /main/DUT/VME_DS_n_i
add wave -noupdate /main/DUT/VME_GA_i
add wave -noupdate /main/DUT/VME_BERR_o
add wave -noupdate /main/DUT/VME_DTACK_n_o
add wave -noupdate /main/DUT/VME_RETRY_n_o
add wave -noupdate /main/DUT/VME_RETRY_OE_o
add wave -noupdate /main/DUT/VME_LWORD_n_b
add wave -noupdate /main/DUT/VME_ADDR_b
add wave -noupdate /main/DUT/VME_DATA_b
add wave -noupdate /main/DUT/VME_BBSY_n_i
add wave -noupdate /main/DUT/VME_IRQ_n_o
add wave -noupdate /main/DUT/VME_IACK_n_i
add wave -noupdate /main/DUT/VME_IACKIN_n_i
add wave -noupdate /main/DUT/VME_IACKOUT_n_o
add wave -noupdate /main/DUT/VME_DTACK_OE_o
add wave -noupdate /main/DUT/VME_DATA_DIR_o
add wave -noupdate /main/DUT/VME_DATA_OE_N_o
add wave -noupdate /main/DUT/VME_ADDR_DIR_o
add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/fmc0_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc1_prsntm2c_n_i
add wave -noupdate /main/DUT/fmc0_scl_b
add wave -noupdate /main/DUT/fmc0_sda_b
add wave -noupdate /main/DUT/fmc1_scl_b
add wave -noupdate /main/DUT/fmc1_sda_b
add wave -noupdate /main/DUT/pll20dac_din_o
add wave -noupdate /main/DUT/pll20dac_sclk_o
add wave -noupdate /main/DUT/pll20dac_sync_n_o
add wave -noupdate /main/DUT/pll25dac_din_o
add wave -noupdate /main/DUT/pll25dac_sclk_o
add wave -noupdate /main/DUT/pll25dac_sync_n_o
add wave -noupdate /main/DUT/tempid_dq_b
add wave -noupdate /main/DUT/fp_ledn_o
add wave -noupdate /main/DUT/fd0_tdc_start_p_i
add wave -noupdate /main/DUT/fd0_tdc_start_n_i
add wave -noupdate /main/DUT/fd0_clk_ref_p_i
add wave -noupdate /main/DUT/fd0_clk_ref_n_i
add wave -noupdate /main/DUT/fd0_trig_a_i
add wave -noupdate /main/DUT/fd0_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd0_tdc_d_b
add wave -noupdate /main/DUT/fd0_tdc_emptyf_i
add wave -noupdate /main/DUT/fd0_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd0_tdc_wr_n_o
add wave -noupdate /main/DUT/fd0_tdc_rd_n_o
add wave -noupdate /main/DUT/fd0_tdc_oe_n_o
add wave -noupdate /main/DUT/fd0_led_trig_o
add wave -noupdate /main/DUT/fd0_tdc_start_dis_o
add wave -noupdate /main/DUT/fd0_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd0_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd0_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd0_spi_sclk_o
add wave -noupdate /main/DUT/fd0_spi_mosi_o
add wave -noupdate /main/DUT/fd0_spi_miso_i
add wave -noupdate /main/DUT/fd0_delay_len_o
add wave -noupdate /main/DUT/fd0_delay_val_o
add wave -noupdate /main/DUT/fd0_delay_pulse_o
add wave -noupdate /main/DUT/fd0_dmtd_clk_o
add wave -noupdate /main/DUT/fd0_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd0_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd0_pll_status_i
add wave -noupdate /main/DUT/fd0_ext_rst_n_o
add wave -noupdate /main/DUT/fd0_onewire_b
add wave -noupdate /main/DUT/fd1_tdc_start_p_i
add wave -noupdate /main/DUT/fd1_tdc_start_n_i
add wave -noupdate /main/DUT/fd1_clk_ref_p_i
add wave -noupdate /main/DUT/fd1_clk_ref_n_i
add wave -noupdate /main/DUT/fd1_trig_a_i
add wave -noupdate /main/DUT/fd1_tdc_cal_pulse_o
add wave -noupdate /main/DUT/fd1_tdc_d_b
add wave -noupdate /main/DUT/fd1_tdc_emptyf_i
add wave -noupdate /main/DUT/fd1_tdc_alutrigger_o
add wave -noupdate /main/DUT/fd1_tdc_wr_n_o
add wave -noupdate /main/DUT/fd1_tdc_rd_n_o
add wave -noupdate /main/DUT/fd1_tdc_oe_n_o
add wave -noupdate /main/DUT/fd1_led_trig_o
add wave -noupdate /main/DUT/fd1_tdc_start_dis_o
add wave -noupdate /main/DUT/fd1_tdc_stop_dis_o
add wave -noupdate /main/DUT/fd1_spi_cs_dac_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_pll_n_o
add wave -noupdate /main/DUT/fd1_spi_cs_gpio_n_o
add wave -noupdate /main/DUT/fd1_spi_sclk_o
add wave -noupdate /main/DUT/fd1_spi_mosi_o
add wave -noupdate /main/DUT/fd1_spi_miso_i
add wave -noupdate /main/DUT/fd1_delay_len_o
add wave -noupdate /main/DUT/fd1_delay_val_o
add wave -noupdate /main/DUT/fd1_delay_pulse_o
add wave -noupdate /main/DUT/fd1_dmtd_clk_o
add wave -noupdate /main/DUT/fd1_dmtd_fb_in_i
add wave -noupdate /main/DUT/fd1_dmtd_fb_out_i
add wave -noupdate /main/DUT/fd1_pll_status_i
add wave -noupdate /main/DUT/fd1_ext_rst_n_o
add wave -noupdate /main/DUT/fd1_onewire_b
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/VME_DATA_b_out
add wave -noupdate /main/DUT/VME_ADDR_b_out
add wave -noupdate /main/DUT/VME_LWORD_n_b_out
add wave -noupdate /main/DUT/VME_DATA_DIR_int
add wave -noupdate /main/DUT/VME_ADDR_DIR_int
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate /main/DUT/dcm0_clk_ref_0
add wave -noupdate /main/DUT/dcm0_clk_ref_180
add wave -noupdate /main/DUT/fd0_tdc_start
add wave -noupdate /main/DUT/tdc0_data_out
add wave -noupdate /main/DUT/tdc0_data_in
add wave -noupdate /main/DUT/tdc0_data_oe
add wave -noupdate /main/DUT/dcm1_clk_ref_0
add wave -noupdate /main/DUT/dcm1_clk_ref_180
add wave -noupdate /main/DUT/fd1_tdc_start
add wave -noupdate /main/DUT/tdc1_data_out
add wave -noupdate /main/DUT/tdc1_data_in
add wave -noupdate /main/DUT/tdc1_data_oe
add wave -noupdate /main/DUT/tm_link_up
add wave -noupdate /main/DUT/tm_utc
add wave -noupdate /main/DUT/tm_cycles
add wave -noupdate /main/DUT/tm_time_valid
add wave -noupdate /main/DUT/tm0_clk_aux_lock_en
add wave -noupdate /main/DUT/tm0_clk_aux_locked
add wave -noupdate /main/DUT/tm1_clk_aux_lock_en
add wave -noupdate /main/DUT/tm1_clk_aux_locked
add wave -noupdate /main/DUT/tm_dac_value
add wave -noupdate /main/DUT/tm0_dac_wr
add wave -noupdate /main/DUT/tm1_dac_wr
add wave -noupdate /main/DUT/ddr0_pll_reset
add wave -noupdate /main/DUT/ddr0_pll_locked
add wave -noupdate /main/DUT/fd0_pll_status
add wave -noupdate /main/DUT/ddr1_pll_reset
add wave -noupdate /main/DUT/ddr1_pll_locked
add wave -noupdate /main/DUT/fd1_pll_status
add wave -noupdate /main/DUT/wrc_scl_out
add wave -noupdate /main/DUT/wrc_scl_in
add wave -noupdate /main/DUT/wrc_sda_out
add wave -noupdate /main/DUT/wrc_sda_in
add wave -noupdate /main/DUT/fd0_scl_out
add wave -noupdate /main/DUT/fd0_scl_in
add wave -noupdate /main/DUT/fd0_sda_out
add wave -noupdate /main/DUT/fd0_sda_in
add wave -noupdate /main/DUT/fd1_scl_out
add wave -noupdate /main/DUT/fd1_scl_in
add wave -noupdate /main/DUT/fd1_sda_out
add wave -noupdate /main/DUT/fd1_sda_in
add wave -noupdate /main/DUT/sfp_scl_out
add wave -noupdate /main/DUT/sfp_scl_in
add wave -noupdate /main/DUT/sfp_sda_out
add wave -noupdate /main/DUT/sfp_sda_in
add wave -noupdate /main/DUT/wrc_owr_en
add wave -noupdate /main/DUT/wrc_owr_in
add wave -noupdate /main/DUT/fd0_owr_en
add wave -noupdate /main/DUT/fd0_owr_in
add wave -noupdate /main/DUT/fd1_owr_en
add wave -noupdate /main/DUT/fd1_owr_in
add wave -noupdate /main/DUT/fd0_irq
add wave -noupdate /main/DUT/fd1_irq
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_125m_gtp
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/local_reset_n
add wave -noupdate /main/DUT/vme_master_out
add wave -noupdate /main/DUT/vme_master_in
add wave -noupdate /main/DUT/pins
add wave -noupdate /main/DUT/rst_n_a
add wave -noupdate /main/DUT/pps
add wave -noupdate /main/DUT/led_divider
add wave -noupdate /main/DUT/leds
add wave -noupdate /main/DUT/etherbone_rst_n
add wave -noupdate /main/DUT/etherbone_src_out
add wave -noupdate /main/DUT/etherbone_src_in
add wave -noupdate /main/DUT/etherbone_snk_out
add wave -noupdate /main/DUT/etherbone_snk_in
add wave -noupdate /main/DUT/etherbone_cfg_in
add wave -noupdate /main/DUT/etherbone_cfg_out
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {23693000000 fs} 0}
configure wave -namecolwidth 183
......@@ -18,4 +235,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {49151514620 fs} {59369721340 fs}
WaveRestoreZoom {2400011620 fs} {12618218340 fs}
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