Commit 40936f9e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wip

parent 620cd691
......@@ -354,6 +354,26 @@ Stop disable
@code{ALUTRIG}
@tab @code{0} @tab
Pulse <code>Alutrigger</code> line
@item @code{8}
@tab W/O @tab
@code{IDELAY_CE}
@tab @code{0} @tab
IDELAY CE (pulse)
@item @code{9}
@tab R/W @tab
@code{IDELAY_RST}
@tab @code{0} @tab
IDELAY RST (GPIO)
@item @code{10}
@tab R/W @tab
@code{IDELAY_CAL}
@tab @code{0} @tab
IDELAY CAL (GPIO)
@item @code{11}
@tab R/W @tab
@code{IDELAY_INC}
@tab @code{0} @tab
IDELAY CAL (GPIO)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -365,6 +385,10 @@ Pulse <code>Alutrigger</code> line
@item @code{START_EN} @tab Controls the @code{StartDis} input of the TDC.@* write 1: enables the TDC start input.@* write 0: no effect.
@item @code{STOP_DIS} @tab Controls the @code{StopDis} input of the TDC.@* write 1: disables the TDC stop input.@* write 0: no effect.
@item @code{ALUTRIG} @tab Controls the TDC's @code{Alutrigger} line. Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.@* write 1: generates a pulse ACAM's @code{Alutrigger} line@* write 0: no effect.
@item @code{IDELAY_CE} @tab Write 1 to pulse the IDELAY CE line for 1 clock tick.
@item @code{IDELAY_RST} @tab State of IDELAY RST line
@item @code{IDELAY_CAL} @tab State of IDELAY CAL line
@item @code{IDELAY_INC} @tab State of IDELAY INC line
@end multitable
@regsection @code{CALR} - Calibration register
Controls calibration logic.
......
`timescale 10fs/10fs
module jittery_delay
(
......@@ -20,4 +21,4 @@ module jittery_delay
out_o <= #(delta) in_i;
end
endmodule // jittery_delay
\ No newline at end of file
endmodule // jittery_delay
......@@ -12,7 +12,7 @@
`define FD_GCR_INPUT_EN_OFFSET 1
`define FD_GCR_INPUT_EN 32'h00000002
`define FD_GCR_DDR_LOCKED_OFFSET 2
`define FD_GCR_DDR_LOCKED 32'h00000004
`define FD_GCR_DDR_LOCKED 32'h0000CAL0004
`define FD_GCR_FMC_PRESENT_OFFSET 3
`define FD_GCR_FMC_PRESENT 32'h00000008
`define ADDR_FD_TCR 8'hc
......@@ -53,6 +53,14 @@
`define FD_TDCSR_STOP_DIS 32'h00000040
`define FD_TDCSR_ALUTRIG_OFFSET 7
`define FD_TDCSR_ALUTRIG 32'h00000080
`define FD_TDCSR_IDELAY_CE_OFFSET 8
`define FD_TDCSR_IDELAY_CE 32'h00000100
`define FD_TDCSR_IDELAY_RST_OFFSET 9
`define FD_TDCSR_IDELAY_RST 32'h00000200
`define FD_TDCSR_IDELAY_CAL_OFFSET 10
`define FD_TDCSR_IDELAY_CAL 32'h00000400
`define FD_TDCSR_IDELAY_INC_OFFSET 11
`define FD_TDCSR_IDELAY_INC 32'h00000800
`define ADDR_FD_CALR 8'h24
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
......
......@@ -10,8 +10,8 @@ module tunable_clock_gen
parameter g_tunable = 0;
parameter g_tuning_range = 20e-6; // 20 ppm
parameter g_tuning_voltage = 1.0;
parameter real g_period = 8ns;
parameter real g_jitter = 10ps;
parameter time g_period = 8ns;
parameter time g_jitter = 10ps;
reg clk = 1'b1;
......@@ -74,4 +74,4 @@ module tunable_clock_gen
end // else: !if(enable)
assign clk_o = clk;
endmodule // tunable_clock_gen
\ No newline at end of file
endmodule // tunable_clock_gen
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include"
sim_tool="modelsim"
sim_top="main"
include_dirs = ["../../include/wb", "../../include/vme64x_bfm", "../../include" ];
syn_device="xc6slx150t"
files = [ "main.sv" ]
......
......@@ -182,6 +182,8 @@ module main;
drv0 = new(acc, 'h80010000);
drv0.init();
drv0.set_idelay_taps(30);
t_start=new;
drv0.get_time(t_start);
t_start.coarse += 20000;
......
vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include
vsim work.main -voptargs=+acc
vsim -t 1ps work.main -novopt -L unisim
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
......@@ -39,6 +39,33 @@ class CSimDrv_FineDelay;
endfunction // new
task set_idelay_taps( int taps );
uint64_t tdcsr;
readl(`ADDR_FD_TDCSR, tdcsr);
// calibrate the iodelay
writel( `ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CAL );
#3us;
writel( `ADDR_FD_TDCSR , tdcsr );
$display("Set IDELAY tap count = %d", taps);
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_RST );
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_INC );
for(int i = 0; i<taps;i++)
begin
writel(`ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CE | `FD_TDCSR_IDELAY_INC );
#1us;
end
endtask // set_idelay_taps
/* fixme - maybe use real mcp23s17 model instead of this stub? */
task sgpio_write(int value);
......
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate -group VME /main/rst_n
add wave -noupdate -group VME /main/clk_125m
add wave -noupdate -group VME /main/clk_20m
add wave -noupdate -group VME /main/VME_AS_n
add wave -noupdate -group VME /main/VME_RST_n
add wave -noupdate -group VME /main/VME_WRITE_n
add wave -noupdate -group VME /main/VME_AM
add wave -noupdate -group VME /main/VME_DS_n
add wave -noupdate -group VME /main/VME_BERR
add wave -noupdate -group VME /main/VME_DTACK_n
add wave -noupdate -group VME /main/VME_RETRY_n
add wave -noupdate -group VME /main/VME_RETRY_OE
add wave -noupdate -group VME /main/VME_LWORD_n
add wave -noupdate -group VME /main/VME_ADDR
add wave -noupdate -group VME /main/VME_DATA
add wave -noupdate -group VME /main/VME_BBSY_n
add wave -noupdate -group VME /main/VME_IRQ_n
add wave -noupdate -group VME /main/VME_IACKIN_n
add wave -noupdate -group VME /main/VME_IACK_n
add wave -noupdate -group VME /main/VME_IACKOUT_n
add wave -noupdate -group VME /main/VME_DTACK_OE
add wave -noupdate -group VME /main/VME_DATA_DIR
add wave -noupdate -group VME /main/VME_DATA_OE_N
add wave -noupdate -group VME /main/VME_ADDR_DIR
add wave -noupdate -group VME /main/VME_ADDR_OE_N
add wave -noupdate -group VME /main/trig0
add wave -noupdate -group VME /main/trig1
add wave -noupdate -group VME /main/out0
add wave -noupdate -group VME /main/out1
add wave -noupdate -group VME /main/pulse_enable
add wave -noupdate -group VME /main/out0_delayed
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/BUSY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DOUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/TOUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CAL
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CE
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CLK
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDATAIN
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/INC
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK0
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ODATAIN
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/RST
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/T
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/COUNTER_WRAPAROUND_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATA_RATE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DELAY_SRC_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY2_VALUE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_MODE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_TYPE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_VALUE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ODELAY_VALUE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/SERDES_MODE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/SIM_TAPDELAY_VALUE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/Tstep
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/COUNTER_WRAPAROUND_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DELAY_SRC_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_MODE_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_TYPE_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/SERDES_MODE_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/GSR_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/rst_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ce_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/inc_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/cal_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_out_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_out
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_out
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_out_dly
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/tout_out_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_pe_one_shot
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_ne_one_shot
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_dly
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_pe_dly
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_pe_dly1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_ne_dly
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_ne_dly1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/sdo_out_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ioclk0_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ioclk1_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ioclk_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/first_edge
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/sat_at_max_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/rst_to_half_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ignore_rst
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/force_rx_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/force_dly_dir_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/output_delay_off
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/input_delay_off
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/isslave
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/encasc
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/counter_wraparound_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/data_rate_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/serdes_mode_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/odelay_value_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_value_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/sim_tap_delay_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_type_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_mode_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_src_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay2_value_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/attr_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/cal_count
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/cal_delay
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/max_delay
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/half_max
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_pe_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_ne_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_pe_clk
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_ne_clk
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/first_time_pe
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/first_time_ne
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_m_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_s_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_m_reg1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_s_reg1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_m_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_s_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_m_reg1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_s_reg1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_reached
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_reached_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_reached_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_working
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_working_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_working_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_ignore
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_pe_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_ne_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/odelay_val_pe_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/odelay_val_ne_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_reached
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_reached_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_reached_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_working
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_working_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_working_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_ignore
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_in
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_in
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/calibrate
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/calibrate_done
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/sync_to_data_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/pci_ce_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/BUSY_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT2_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DOUT_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/TOUT_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/BUSY_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT2_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DOUT_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/TOUT_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CAL_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CE_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CLK_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDATAIN_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/INC_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK0_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK1_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ODATAIN_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/RST_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/T_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CAL_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CE_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CLK_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDATAIN_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/INC_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK0_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK1_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ODATAIN_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/RST_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/T_INDELAY
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {53004000000 fs} 0}
WaveRestoreCursors {{Cursor 1} {9101898590 fs} 0}
configure wave -namecolwidth 183
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......
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