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FMC DEL 1ns 4cha
Commit 3e17d062 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'master' of ohwr.org:fmc-projects/fmc-delay-1ns-8cha

parents cc9cdb55 de052457
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hdl/.gitignore
View file @ 3e17d062
......@@ -8,5 +8,7 @@ modelsim.ini
*.vstf
work
*.bak
hdl/syn/spec_1_1/*
syn/spec_1_1/*
syn/spec_wr_demo/*
syn/tests
transcript
\ No newline at end of file
hdl/include/fine_delay_regs.v
View file @ 3e17d062
......@@ -11,6 +11,10 @@
`define FD_GCR_CSYNC_WR 32'h00000008
`define FD_GCR_WR_READY_OFFSET 4
`define FD_GCR_WR_READY 32'h00000010
`define FD_GCR_WR_LOCK_EN_OFFSET 5
`define FD_GCR_WR_LOCK_EN 32'h00000020
`define FD_GCR_WR_LOCKED_OFFSET 6
`define FD_GCR_WR_LOCKED 32'h00000040
`define ADDR_FD_TAR 8'hc
`define FD_TAR_DATA_OFFSET 0
`define FD_TAR_DATA 32'h0fffffff
......@@ -29,33 +33,55 @@
`define FD_TDCSR_LOAD 32'h00000010
`define FD_TDCSR_EMPTY_OFFSET 5
`define FD_TDCSR_EMPTY 32'h00000020
`define FD_TDCSR_START_DIS_OFFSET 6
`define FD_TDCSR_START_DIS 32'h00000040
`define FD_TDCSR_START_EN_OFFSET 7
`define FD_TDCSR_START_EN 32'h00000080
`define FD_TDCSR_STOP_DIS_OFFSET 8
`define FD_TDCSR_STOP_DIS 32'h00000100
`define FD_TDCSR_STOP_EN_OFFSET 9
`define FD_TDCSR_STOP_EN 32'h00000200
`define ADDR_FD_ADSFR 8'h14
`define ADDR_FD_ATMCR 8'h18
`define FD_TDCSR_STOP_EN_OFFSET 6
`define FD_TDCSR_STOP_EN 32'h00000040
`define FD_TDCSR_START_DIS_OFFSET 7
`define FD_TDCSR_START_DIS 32'h00000080
`define FD_TDCSR_START_EN_OFFSET 8
`define FD_TDCSR_START_EN 32'h00000100
`define FD_TDCSR_STOP_DIS_OFFSET 9
`define FD_TDCSR_STOP_DIS 32'h00000200
`define FD_TDCSR_ALUTRIG_OFFSET 10
`define FD_TDCSR_ALUTRIG 32'h00000400
`define ADDR_FD_CALR 8'h14
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
`define FD_CALR_PSEL_OFFSET 1
`define FD_CALR_PSEL 32'h0000001e
`define ADDR_FD_ADSFR 8'h18
`define ADDR_FD_ATMCR 8'h1c
`define FD_ATMCR_C_THR_OFFSET 0
`define FD_ATMCR_C_THR 32'h0000000f
`define FD_ATMCR_F_THR_OFFSET 4
`define FD_ATMCR_F_THR 32'h07fffff0
`define ADDR_FD_ASOR 8'h1c
`define ADDR_FD_ASOR 8'h20
`define FD_ASOR_OFFSET_OFFSET 0
`define FD_ASOR_OFFSET 32'h007fffff
`define ADDR_FD_IECRAW 8'h20
`define ADDR_FD_IECTAG 8'h24
`define ADDR_FD_IEPD 8'h28
`define ADDR_FD_IECRAW 8'h24
`define ADDR_FD_IECTAG 8'h28
`define ADDR_FD_IEPD 8'h2c
`define FD_IEPD_RST_STAT_OFFSET 0
`define FD_IEPD_RST_STAT 32'h00000001
`define FD_IEPD_PDELAY_OFFSET 1
`define FD_IEPD_PDELAY 32'h000001fe
`define ADDR_FD_RCRR 8'h2c
`define ADDR_FD_RCFR 8'h30
`define ADDR_FD_TSBCR 8'h34
`define ADDR_FD_SCR 8'h30
`define FD_SCR_DATA_OFFSET 0
`define FD_SCR_DATA 32'h00ffffff
`define FD_SCR_SEL_DAC_OFFSET 24
`define FD_SCR_SEL_DAC 32'h01000000
`define FD_SCR_SEL_PLL_OFFSET 25
`define FD_SCR_SEL_PLL 32'h02000000
`define FD_SCR_SEL_GPIO_OFFSET 26
`define FD_SCR_SEL_GPIO 32'h04000000
`define FD_SCR_READY_OFFSET 27
`define FD_SCR_READY 32'h08000000
`define FD_SCR_CPOL_OFFSET 28
`define FD_SCR_CPOL 32'h10000000
`define FD_SCR_START_OFFSET 29
`define FD_SCR_START 32'h20000000
`define ADDR_FD_RCRR 8'h34
`define ADDR_FD_RCFR 8'h38
`define ADDR_FD_TSBCR 8'h3c
`define FD_TSBCR_ENABLE_OFFSET 0
`define FD_TSBCR_ENABLE 32'h00000001
`define FD_TSBCR_PURGE_OFFSET 1
......@@ -66,9 +92,9 @@
`define FD_TSBCR_FULL 32'h00000008
`define FD_TSBCR_EMPTY_OFFSET 4
`define FD_TSBCR_EMPTY 32'h00000010
`define ADDR_FD_TSBR_U 8'h38
`define ADDR_FD_TSBR_C 8'h3c
`define ADDR_FD_TSBR_FID 8'h40
`define ADDR_FD_TSBR_U 8'h40
`define ADDR_FD_TSBR_C 8'h44
`define ADDR_FD_TSBR_FID 8'h48
`define FD_TSBR_FID_FINE_OFFSET 0
`define FD_TSBR_FID_FINE 32'h00000fff
`define FD_TSBR_FID_SEQID_OFFSET 16
......@@ -86,8 +112,8 @@
`define FD_DCR1_UPDATE 32'h00000010
`define FD_DCR1_UPD_DONE_OFFSET 5
`define FD_DCR1_UPD_DONE 32'h00000020
`define FD_DCR1_FORCE_CP_OFFSET 6
`define FD_DCR1_FORCE_CP 32'h00000040
`define FD_DCR1_FORCE_DLY_OFFSET 6
`define FD_DCR1_FORCE_DLY 32'h00000040
`define FD_DCR1_POL_OFFSET 7
`define FD_DCR1_POL 32'h00000080
`define ADDR_FD_FRR1 8'h64
......@@ -110,8 +136,8 @@
`define FD_DCR2_UPDATE 32'h00000010
`define FD_DCR2_UPD_DONE_OFFSET 5
`define FD_DCR2_UPD_DONE 32'h00000020
`define FD_DCR2_FORCE_CP_OFFSET 6
`define FD_DCR2_FORCE_CP 32'h00000040
`define FD_DCR2_FORCE_DLY_OFFSET 6
`define FD_DCR2_FORCE_DLY 32'h00000040
`define FD_DCR2_POL_OFFSET 7
`define FD_DCR2_POL 32'h00000080
`define ADDR_FD_FRR2 8'h84
......@@ -134,8 +160,8 @@
`define FD_DCR3_UPDATE 32'h00000010
`define FD_DCR3_UPD_DONE_OFFSET 5
`define FD_DCR3_UPD_DONE 32'h00000020
`define FD_DCR3_FORCE_CP_OFFSET 6
`define FD_DCR3_FORCE_CP 32'h00000040
`define FD_DCR3_FORCE_DLY_OFFSET 6
`define FD_DCR3_FORCE_DLY 32'h00000040
`define FD_DCR3_POL_OFFSET 7
`define FD_DCR3_POL 32'h00000080
`define ADDR_FD_FRR3 8'ha4
......@@ -158,8 +184,8 @@
`define FD_DCR4_UPDATE 32'h00000010
`define FD_DCR4_UPD_DONE_OFFSET 5
`define FD_DCR4_UPD_DONE 32'h00000020
`define FD_DCR4_FORCE_CP_OFFSET 6
`define FD_DCR4_FORCE_CP 32'h00000040
`define FD_DCR4_FORCE_DLY_OFFSET 6
`define FD_DCR4_FORCE_DLY 32'h00000040
`define FD_DCR4_POL_OFFSET 7
`define FD_DCR4_POL 32'h00000080
`define ADDR_FD_FRR4 8'hc4
......
hdl/rtl/Manifest.py
View file @ 3e17d062
......@@ -20,7 +20,6 @@ fetchto = "../ip_cores"
modules = {
"git" : [
"git@ohwr.org:hdl-core-lib/wr-cores.git",
"git@ohwr.org:hdl-core-lib/general-cores.git" ],
"git@ohwr.org:hdl-core-lib/general-cores.git::wishbone_with_adapter" ],
"svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
};
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
View file @ 3e17d062
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2011-10-20
-- Last update: 2011-10-31
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -96,7 +96,7 @@ architecture behavioral of fd_acam_timestamp_postprocessor is
-- timestamp
constant c_SCALER_SHIFT : integer := 12;
signal pp_pipe : std_logic_vector(3 downto 0);
signal pp_pipe : std_logic_vector(4 downto 0);
signal post_tag_coarse : unsigned(27 downto 0);
signal post_tag_frac : unsigned(g_frac_bits-1 downto 0);
......@@ -159,28 +159,31 @@ begin -- behavioral
-- rescale the fractional part to our internal time base
pp_pipe(2) <= pp_pipe(1);
--post_frac_multiplied <= resize(signed(post_frac_start_adj) * signed(regs_i.adsfr_o), post_frac_multiplied'length);
-- post_frac_multiplied_d0 <= post_frac_multiplied;
post_frac_multiplied <= resize(signed(post_frac_start_adj) * adsfr_d0, post_frac_multiplied'length);
-- pipeline stage 4: pass the multiplication result through another register
-- (timing improvement)
pp_pipe(3) <= pp_pipe(2);
post_frac_multiplied_d0 <= post_frac_multiplied;
-- pipeline stage 4:
-- - split the rescaled fractional part into the (mod 4096) tag_frac_o and add
-- the rest to the coarse part, along with the start-to-timescale offset
pp_pipe(3) <= pp_pipe(2);
pp_pipe(4) <= pp_pipe(3);
tag_utc_o <= std_logic_vector(post_tag_utc);
tag_coarse_o <= std_logic_vector(
signed(post_tag_coarse) -- index of start pulse (mod 16 = 0)
+ signed(acam_subcycle_offset_i) -- start-to-timescale offset
+ signed(post_frac_multiplied(post_frac_multiplied'left downto c_SCALER_SHIFT + g_frac_bits)));
+ signed(post_frac_multiplied_d0(post_frac_multiplied_d0'left downto c_SCALER_SHIFT + g_frac_bits)));
-- extra coarse counts from ACAM's frac part after rescaling
tag_frac_o <= std_logic_vector(post_frac_multiplied(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_valid_o <= pp_pipe(3);
tag_valid_o <= pp_pipe(4);
end if;
end if;
......
hdl/rtl/fd_spi_master.vhd
View file @ 3e17d062
......@@ -40,137 +40,110 @@ architecture behavioral of fd_spi_master is
signal busy : std_logic;
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(23 downto 0);
signal bitCounter : std_logic_vector(25 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider : unsigned(11 downto 0);
signal divider_muxed : std_logic;
signal cs_sel_dac : std_logic;
signal cs_sel_gpio : std_logic;
signal cs_sel_pll : std_logic;
signal sreg : std_logic_vector(23 downto 0);
signal rx_sreg : std_logic_vector(23 downto 0);
-- signal data_in_reg : std_logic_vector(23 downto 0);
signal data_out_reg : std_logic_vector(23 downto 0);
begin -- rtl
type t_state is (IDLE, TX_CS, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal state : t_state;
signal sclk : std_logic;
signal counter : unsigned(4 downto 0);
divider_muxed <= divider(g_div_ratio_log2); -- sclk = clk_i/64
iValidValue <= start_i;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
begin -- rtl
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if iValidValue = '1' then
if rst_n_i = '0' then
divider <= (others => '0');
elsif sendingData = '1' then
if(divider_muxed = '1') then
else
if(start_i = '1' or divider_muxed = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (others => '0');
end if;
end if;
end process;
divider_muxed <= divider(g_div_ratio_log2); -- sclk = clk_i/64
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
state <= IDLE;
sclk <= '0';
spi_cs_gpio_n_o <= '1';
spi_cs_pll_n_o <= '1';
spi_cs_dac_n_o <= '1';
sreg <= (others => '0');
rx_sreg <= (others => '0');
spi_mosi_o <= '0';
counter <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
cs_sel_dac <= sel_dac_i;
cs_sel_gpio <= sel_gpio_i;
cs_sel_pll <= sel_pll_i;
dataSh <= data_i; --data_in_reg;
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= spi_miso_i; --dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
case state is
when IDLE =>
sclk <= '1';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
state <= TX_CS;
spi_cs_dac_n_o <= not sel_dac_i;
spi_cs_pll_n_o <= not sel_pll_i;
spi_cs_gpio_n_o <= not sel_gpio_i;
spi_mosi_o <= data_i(sreg'high);
end if;
when TX_CS =>
if divider_muxed = '1' then
state <= TX_SCK1;
end if;
when TX_SCK1 =>
if(divider_muxed = '1') then
sclk <= not sclk;
spi_mosi_o <= sreg(sreg'high);
sreg <= sreg(sreg'high-1 downto 0) & '0';
counter <= counter + 1;
state <= TX_SCK2;
end if;
when TX_SCK2 =>
if(divider_muxed = '1') then
sclk <= not sclk;
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
if(counter = 24) then
state <= TX_CS2;
else
state <= TX_SCK1;
end if;
end if;
when TX_CS2 =>
if(divider_muxed = '1') then
state <= TX_GAP;
spi_cs_gpio_n_o <= '1';
spi_cs_pll_n_o <= '1';
spi_cs_dac_n_o <= '1';
data_o <= rx_sreg;
end if;
when TX_GAP =>
if (divider_muxed = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
ready_o <= not SendingData;
data_o <= dataSh;
spi_mosi_o <= dataSh(dataSh'left);
spi_cs_pll_n_o <= not(sendingData) or (not cs_sel_pll);
spi_cs_dac_n_o <= not(sendingData) or (not cs_sel_dac);
spi_cs_gpio_n_o <= not(sendingData) or (not cs_sel_gpio);
p_drive_sclk : process(iDacClk, cpol_i)
begin
if(cpol_i = '0') then
spi_sclk_o <= (iDacClk);
else
spi_sclk_o <= not (iDacClk);
end if;
end process;
ready_o <= '1' when state = IDLE else '0';
spi_sclk_o <= sclk xor cpol_i;
end behavioral;
hdl/rtl/fine_delay_core.vhd
View file @ 3e17d062
......@@ -103,7 +103,7 @@ entity fine_delay_core is
tm_utc_i : in std_logic_vector(39 downto 0);
tm_clk_aux_lock_en_o : out std_logic;
tm_clk_aux_locked_i : in std_logic;
tm_dac_value_i : in std_logic_vector(31 downto 0);
tm_dac_value_i : in std_logic_vector(23 downto 0);
tm_dac_wr_i : in std_logic;
---------------------------------------------------------------------------
......@@ -113,6 +113,14 @@ entity fine_delay_core is
owr_en_o : out std_logic;
owr_i : in std_logic;
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_o : out std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
---------------------------------------------------------------------------
-- Wishbone (classic)
---------------------------------------------------------------------------
......@@ -339,7 +347,7 @@ architecture rtl of fine_delay_core is
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers);
end component;
signal tag_frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
signal tag_coarse : std_logic_vector(27 downto 0);
signal tag_utc : std_logic_vector(31 downto 0);
......@@ -380,7 +388,7 @@ architecture rtl of fine_delay_core is
signal regs_fromwb : t_fd_out_registers;
signal regs_towb_csync : t_fd_in_registers;
signal regs_towb_spi : t_fd_in_registers;
signal regs_towb_spi : t_fd_in_registers;
signal regs_towb_tsu : t_fd_in_registers;
signal regs_towb_rbuf : t_fd_in_registers;
signal regs_towb_local : t_fd_in_registers := c_fd_in_registers_init_value;
......@@ -395,6 +403,9 @@ architecture rtl of fine_delay_core is
signal gen_cal_pulse : std_logic_vector(3 downto 0);
signal cal_pulse_mask : std_logic_vector(3 downto 0);
signal cal_pulse_trigger : std_logic;
signal tm_dac_val_int : std_logic_vector(31 downto 0);
begin -- rtl
......@@ -408,6 +419,7 @@ begin -- rtl
wb_ack_o <= wb_out.ack;
wb_dat_o <= wb_out.dat;
tm_dac_val_int <= x"00" & tm_dac_value_i;
U_WB_Fanout : xwb_bus_fanout
generic map (
......@@ -446,36 +458,31 @@ begin -- rtl
regs_o => regs_towb_csync);
regs_towb_local.gcr_wr_locked_i <= tm_clk_aux_locked_i;
tm_clk_aux_lock_en_o <= regs_fromwb.gcr_wr_lock_en_o;
--U_SPI_Master : xwb_spi
-- generic map (
-- g_interface_mode => CLASSIC)
-- port map (
-- clk_sys_i => clk_sys_i,
-- rst_n_i => rst_n_i,
-- slave_i => fan_out(1),
-- slave_o => fan_in(1),
-- pad_cs_o => spi_cs_vec,
-- pad_sclk_o => spi_sclk_o,
-- pad_mosi_o => spi_mosi_o,
-- pad_miso_i => spi_miso_i);
--spi_cs_dac_n_o <= spi_cs_vec(0);
--spi_cs_pll_n_o <= spi_cs_vec(1);
--spi_cs_gpio_n_o <= spi_cs_vec(2);
fan_in(1).ack <= '1';
fan_in(1).err <= '0';
fan_in(1).rty <= '0';
U_SPI_Arbiter: fd_spi_dac_arbiter
tm_clk_aux_lock_en_o <= regs_fromwb.gcr_wr_lock_en_o;
U_I2C_Master : xwb_i2c_master
generic map (
g_interface_mode => CLASSIC)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => fan_out(1),
slave_o => fan_in(1),
scl_pad_o => i2c_scl_o,
scl_padoen_o => i2c_scl_oen_o,
scl_pad_i => i2c_scl_i,
sda_pad_o => i2c_sda_o,
sda_padoen_o => i2c_sda_oen_o,
sda_pad_i => i2c_sda_i);
U_SPI_Arbiter : fd_spi_dac_arbiter
generic map (
g_div_ratio_log2 => 10)
g_div_ratio_log2 => 4)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys,
tm_dac_value_i => tm_dac_value_i,
tm_dac_value_i => tm_dac_val_int,
tm_dac_wr_i => tm_dac_wr_i,
spi_cs_dac_n_o => spi_cs_dac_n_o,
spi_cs_pll_n_o => spi_cs_pll_n_o,
......@@ -485,7 +492,7 @@ begin -- rtl
spi_miso_i => spi_miso_i,
regs_i => regs_fromwb,
regs_o => regs_towb_spi);
U_Onewire : xwb_onewire_master
generic map (
......
hdl/syn/spec_1_1/Makefile deleted 100644 → 0
View file @ cc9cdb55
####################################
# This file was generated by hdlmake
# http://ohwr.org/projects/hdl-make/
####################################
PROJECT := finedelay_spec_1_1.xise
ISE_CRAP := *.bgn *.html *.tcl *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.unroutes *.ut *.xpi *.xst *_bitgen.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.html *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER := $(HDLMAKE_USER)
SERVER := $(HDLMAKE_SERVER)
R_NAME := finedelay_spec_1_1
CWD := $(shell pwd)
FILES := ../../top/spec_1_1/spec_top_finedelay.vhd \
../../top/spec_1_1/spec_top_finedelay.ucf \
../../top/spec_1_1/wb_gpio_port_notristates.vhd \
../../rtl/fd_acam_timestamper.vhd \
../../rtl/fd_cal_pulse_gen.vhd \
../../rtl/fd_delay_line_driver.vhd \
../../rtl/fd_wbgen2_pkg.vhd \
../../rtl/fine_delay_core.vhd \
../../rtl/fine_delay_pkg.vhd \
../../rtl/fine_delay_wb.vhd \
../../ip_cores/rtl/clock_generator_ddr_s2_diff.vhd \
../../ip_cores/rtl/clock_generator_pll_s2_diff.vhd \
../../ip_cores/rtl/dma_controller.vhd \
../../ip_cores/rtl/dma_controller_wb_slave.vhd \
../../ip_cores/rtl/gn4124_core_pkg.vhd \
../../ip_cores/rtl/l2p_arbiter.vhd \
../../ip_cores/rtl/l2p_dma_master.vhd \
../../ip_cores/rtl/p2l_decode32.vhd \
../../ip_cores/rtl/p2l_dma_master.vhd \
../../ip_cores/rtl/serdes_1_to_n_clk_ddr_s2_diff.vhd \
../../ip_cores/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/rtl/serdes_1_to_n_data_ddr_s2_se.vhd \
../../ip_cores/rtl/serdes_1_to_n_data_s2_se.vhd \
../../ip_cores/rtl/serdes_n_to_1_ddr_s2_diff.vhd \
../../ip_cores/rtl/serdes_n_to_1_ddr_s2_se.vhd \
../../ip_cores/rtl/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/rtl/serdes_n_to_1_s2_se.vhd \
../../ip_cores/rtl/wbmaster32.vhd \
../../ip_cores/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/rtl/spartan6/gn4124_core_private_pkg.vhd \
../../ip_cores/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/rtl/spartan6/p2l_des.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_cpu_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.wb \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd \
../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/wr-cores/modules/wr_softpll/softpll_wb.vhd \
../../ip_cores/wr-cores/modules/wr_softpll/wr_softpll.vhd \
../../ip_cores/wr-cores/modules/wrc_lm32/wrc_lm32.vhd \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_cpu.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_addsub.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_top.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_instruction_unit.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_decoder.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_load_store_unit.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_adder.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_logic_op.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_shifter.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_multiplier.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_interrupt.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_dp_ram.v \
../../ip_cores/wr-cores/modules/wrsw_endpoint/endpoint_pkg.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_enc_8b10b.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_dec_8b10b.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_autonegotiation.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_1000basex_pcs.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_crc_size_check.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_deframer.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_framer.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_flow_control.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_timestamping_unit.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rmon_counters.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_buffer.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_sync_detect.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_wishbone_controller.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_ts_counter.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/wrsw_endpoint.vhd \
../../ip_cores/wr-cores/modules/wrsw_pps_gen/pps_gen_wb.vhd \
../../ip_cores/wr-cores/modules/wrsw_pps_gen/wrsw_pps_gen.vhd \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v \
../../ip_cores/wr-cores/modules/wrc_lm32/system_conf.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
finedelay_spec_1_1.xise
#target for running simulation in the remote location
remote: __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
hdl/syn/spec_1_1/finedelay_spec_1_1.xise deleted 100644 → 0
View file @ cc9cdb55
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
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<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
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<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
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<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
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<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
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<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
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<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="finedelay_spec_1_1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-01T17:22:55" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F847B25A7A1F69D9DE3E99AD4776B79D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</libraries>
<files>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
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hdl/syn/spec_1_1/spec_fine_delay.xise
View file @ 3e17d062
......@@ -45,7 +45,7 @@
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -121,7 +121,7 @@
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
......@@ -704,7 +704,7 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../rtl/fd_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -716,7 +716,7 @@
<file xil_pn:name="../../rtl/fd_ts_normalizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../rtl/fd_reset_generator.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../rtl/fd_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../rtl/fd_csync_generator.vhd" xil_pn:type="FILE_VHDL">
......@@ -737,389 +737,224 @@
<file xil_pn:name="../../rtl/fd_rearm_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../rtl/fd_acam_timestamper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../rtl/fd_reset_generator.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../top/spec_1_1/spec_top.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../rtl/fd_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
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<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
</files>
......
hdl/testbench/top/Makefile
View file @ 3e17d062
####################################
# This file was generated by hdlmake
# http://ohwr.org/projects/hdl-make/
####################################
#######################################################################
# This makefile has been automatically generated by hdl-make
# on Wed, 01 Jun 2011 15:20:51
#######################################################################
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
WORK_NAME := work
MODELSIM_INI_PATH := /opt/modelsim_65e/modeltech
MODELSIM_INI_PATH := /opt/modelsim_10
VCOM_FLAGS := -nologo -quiet -93 -modelsimini ./modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -nologo -quiet -sv -modelsimini $(PWD)/modelsim.ini +incdir+../../include
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC := main.sv \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_cpu.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_addsub.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_top.v \
......@@ -32,129 +24,282 @@ VERILOG_SRC := main.sv \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_multiplier.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_interrupt.v \
../../ip_cores/wr-cores/modules/wrc_lm32/lm32_dp_ram.v \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
VERILOG_OBJ := work/main/.main \
work/spi_clgen/.spi_clgen \
work/spi_shift/.spi_shift \
work/spi_top/.spi_top \
work/lm32_cpu/.lm32_cpu \
work/lm32_addsub/.lm32_addsub \
work/lm32_top/.lm32_top \
work/lm32_instruction_unit/.lm32_instruction_unit \
work/lm32_decoder/.lm32_decoder \
work/lm32_load_store_unit/.lm32_load_store_unit \
work/lm32_adder/.lm32_adder \
work/lm32_logic_op/.lm32_logic_op \
work/lm32_shifter/.lm32_shifter \
work/lm32_multiplier/.lm32_multiplier \
work/lm32_interrupt/.lm32_interrupt \
work/lm32_dp_ram/.lm32_dp_ram \
VHDL_OBJ := work/wbgen2_pkg/.wbgen2_pkg \
work/fd_cal_pulse_gen/.fd_cal_pulse_gen \
work/fine_delay_pkg/.fine_delay_pkg \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg \
work/fine_delay_core/.fine_delay_core \
work/fd_delay_line_driver/.fd_delay_line_driver \
work/fd_acam_timestamper/.fd_acam_timestamper \
work/clock_generator_ddr_s2_diff/.clock_generator_ddr_s2_diff \
work/clock_generator_pll_s2_diff/.clock_generator_pll_s2_diff \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/dma_controller_wb_slave/.dma_controller_wb_slave \
work/gn4124_core_pkg/.gn4124_core_pkg \
work/l2p_arbiter/.l2p_arbiter \
work/genram_pkg/.genram_pkg \
work/p2l_decode32/.p2l_decode32 \
work/p2l_dma_master/.p2l_dma_master \
work/serdes_1_to_n_clk_ddr_s2_diff/.serdes_1_to_n_clk_ddr_s2_diff \
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff \
work/serdes_1_to_n_data_ddr_s2_se/.serdes_1_to_n_data_ddr_s2_se \
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se \
work/serdes_n_to_1_ddr_s2_diff/.serdes_n_to_1_ddr_s2_diff \
work/serdes_n_to_1_ddr_s2_se/.serdes_n_to_1_ddr_s2_se \
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff \
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se \
work/wbmaster32/.wbmaster32 \
work/gn4124_core/.gn4124_core \
work/dma_controller/.dma_controller \
work/l2p_ser/.l2p_ser \
work/p2l_des/.p2l_des \
work/gencores_pkg/.gencores_pkg \
work/gc_crc_gen/.gc_crc_gen \
work/gc_moving_average/.gc_moving_average \
work/gc_extend_pulse/.gc_extend_pulse \
work/gc_delay_gen/.gc_delay_gen \
work/gc_dual_pi_controller/.gc_dual_pi_controller \
work/gc_serial_dac/.gc_serial_dac \
work/gc_sync_ffs/.gc_sync_ffs \
work/l2p_dma_master/.l2p_dma_master \
work/wishbone_pkg/.wishbone_pkg \
work/wb_cpu_bridge/.wb_cpu_bridge \
work/wb_conmax_pri_dec/.wb_conmax_pri_dec \
work/wb_conmax_pri_enc/.wb_conmax_pri_enc \
work/wb_conmax_arb/.wb_conmax_arb \
work/wb_conmax_msel/.wb_conmax_msel \
work/wbconmax_pkg/.wbconmax_pkg \
work/wb_conmax_slave_if/.wb_conmax_slave_if \
work/wb_conmax_master_if/.wb_conmax_master_if \
work/wb_conmax_rf/.wb_conmax_rf \
work/wb_conmax_top/.wb_conmax_top \
work/wb_gpio_port/.wb_gpio_port \
work/wb_tics/.wb_tics \
work/uart_async_rx/.uart_async_rx \
work/uart_async_tx/.uart_async_tx \
work/uart_baud_gen/.uart_baud_gen \
work/uart_wb_slave/.uart_wb_slave \
work/wb_simple_uart/.wb_simple_uart \
work/vic_prio_enc/.vic_prio_enc \
work/wb_vic/.wb_vic \
work/wb_virtual_uart/.wb_virtual_uart \
work/wb_virtual_uart_slave/.wb_virtual_uart_slave \
work/wbgen2_dpssram/.wbgen2_dpssram \
work/wbgen2_eic/.wbgen2_eic \
work/wbgen2_fifo_async/.wbgen2_fifo_async \
work/wbgen2_fifo_sync/.wbgen2_fifo_sync \
work/fine_delay_wb/.fine_delay_wb \
work/generic_async_fifo/.generic_async_fifo \
work/generic_dpram/.generic_dpram \
work/generic_spram/.generic_spram \
work/generic_sync_fifo/.generic_sync_fifo \
work/gtp_bitslide/.gtp_bitslide \
work/gtp_phase_align/.gtp_phase_align \
work/whiterabbitgtp_wrapper/.whiterabbitgtp_wrapper \
work/whiterabbitgtp_wrapper_tile/.whiterabbitgtp_wrapper_tile \
work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6 \
work/dmtd_phase_meas/.dmtd_phase_meas \
work/dmtd_with_deglitcher/.dmtd_with_deglitcher \
work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher \
work/hpll_period_detect/.hpll_period_detect \
work/minic_packet_buffer/.minic_packet_buffer \
work/minic_wb_slave/.minic_wb_slave \
work/endpoint_pkg/.endpoint_pkg \
work/softpll_wb/.softpll_wb \
work/wr_softpll/.wr_softpll \
work/wrc_lm32/.wrc_lm32 \
work/wr_mini_nic/.wr_mini_nic \
work/ep_enc_8b10b/.ep_enc_8b10b \
work/ep_dec_8b10b/.ep_dec_8b10b \
work/ep_rx_pcs_tbi/.ep_rx_pcs_tbi \
work/ep_tx_pcs_tbi/.ep_tx_pcs_tbi \
work/ep_autonegotiation/.ep_autonegotiation \
work/ep_pcs_tbi_mdio_wb/.ep_pcs_tbi_mdio_wb \
work/ep_1000basex_pcs/.ep_1000basex_pcs \
work/ep_rx_crc_size_check/.ep_rx_crc_size_check \
work/ep_rx_deframer/.ep_rx_deframer \
work/ep_tx_framer/.ep_tx_framer \
work/ep_flow_control/.ep_flow_control \
work/ep_timestamping_unit/.ep_timestamping_unit \
work/ep_rmon_counters/.ep_rmon_counters \
work/ep_rx_buffer/.ep_rx_buffer \
work/ep_sync_detect/.ep_sync_detect \
work/ep_wishbone_controller/.ep_wishbone_controller \
work/ep_ts_counter/.ep_ts_counter \
work/wrsw_endpoint/.wrsw_endpoint \
work/pps_gen_wb/.pps_gen_wb \
work/wrsw_pps_gen/.wrsw_pps_gen \
VERILOG_OBJ := work/main/.main_sv \
work/lm32_cpu/.lm32_cpu_v \
work/lm32_addsub/.lm32_addsub_v \
work/lm32_top/.lm32_top_v \
work/lm32_instruction_unit/.lm32_instruction_unit_v \
work/lm32_decoder/.lm32_decoder_v \
work/lm32_load_store_unit/.lm32_load_store_unit_v \
work/lm32_adder/.lm32_adder_v \
work/lm32_logic_op/.lm32_logic_op_v \
work/lm32_shifter/.lm32_shifter_v \
work/lm32_multiplier/.lm32_multiplier_v \
work/lm32_interrupt/.lm32_interrupt_v \
work/lm32_dp_ram/.lm32_dp_ram_v \
work/sockit_owm/.sockit_owm_v \
work/spi_clgen/.spi_clgen_v \
work/spi_shift/.spi_shift_v \
work/spi_top/.spi_top_v \
VHDL_SRC := ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../rtl/fd_ts_adder.vhd \
../../rtl/fd_ts_normalizer.vhd \
../../rtl/fd_wbgen2_pkg.vhd \
../../rtl/fd_csync_generator.vhd \
../../rtl/fd_timestamper_stat_unit.vhd \
../../rtl/fd_acam_timestamp_postprocessor.vhd \
../../rtl/fine_delay_pkg.vhd \
../../rtl/fd_delay_line_arbiter.vhd \
../../rtl/fd_rearm_generator.vhd \
../../rtl/fd_reset_generator.vhd \
../../rtl/fd_spi_master.vhd \
../../rtl/fd_spi_dac_arbiter.vhd \
../../rtl/fd_delay_channel_driver.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core_private_pkg.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller_wb_slave.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/gn4124_core_pkg.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/l2p_arbiter.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/l2p_dma_master.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/p2l_decode32.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/p2l_dma_master.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/wbmaster32.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd \
../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd \
../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/endpoint_pkg.vhd \
../../ip_cores/wr-cores/modules/wr_softpll/softpll_wb.vhd \
../../ip_cores/wr-cores/modules/wr_softpll/wr_softpll.vhd \
../../ip_cores/wr-cores/modules/wrc_lm32/wrc_lm32.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd \
../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_enc_8b10b.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_dec_8b10b.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_autonegotiation.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_1000basex_pcs.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_crc_size_check.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_deframer.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_framer.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_flow_control.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_timestamping_unit.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rmon_counters.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_buffer.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_sync_detect.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_wishbone_controller.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_ts_counter.vhd \
../../ip_cores/wr-cores/modules/wrsw_endpoint/wrsw_endpoint.vhd \
../../ip_cores/wr-cores/modules/wrsw_pps_gen/pps_gen_wb.vhd \
../../ip_cores/wr-cores/modules/wrsw_pps_gen/wrsw_pps_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd \
../../rtl/fd_acam_timestamper.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../rtl/fd_ring_buffer.vhd \
../../rtl/fine_delay_core.vhd \
../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd \
../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../rtl/fd_wishbone_slave.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/p2l_des.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
VHDL_OBJ := work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/fd_ts_adder/.fd_ts_adder_vhd \
work/fd_ts_normalizer/.fd_ts_normalizer_vhd \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg_vhd \
work/fd_csync_generator/.fd_csync_generator_vhd \
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit_vhd \
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor_vhd \
work/fine_delay_pkg/.fine_delay_pkg_vhd \
work/fd_delay_line_arbiter/.fd_delay_line_arbiter_vhd \
work/fd_rearm_generator/.fd_rearm_generator_vhd \
work/fd_reset_generator/.fd_reset_generator_vhd \
work/fd_spi_master/.fd_spi_master_vhd \
work/fd_spi_dac_arbiter/.fd_spi_dac_arbiter_vhd \
work/fd_delay_channel_driver/.fd_delay_channel_driver_vhd \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg_vhd \
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd \
work/gn4124_core_pkg/.gn4124_core_pkg_vhd \
work/l2p_arbiter/.l2p_arbiter_vhd \
work/l2p_dma_master/.l2p_dma_master_vhd \
work/p2l_decode32/.p2l_decode32_vhd \
work/p2l_dma_master/.p2l_dma_master_vhd \
work/wbmaster32/.wbmaster32_vhd \
work/gtp_bitslide/.gtp_bitslide_vhd \
work/gtp_phase_align/.gtp_phase_align_vhd \
work/whiterabbitgtp_wrapper_tile/.whiterabbitgtp_wrapper_tile_vhd \
work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6_vhd \
work/dmtd_phase_meas/.dmtd_phase_meas_vhd \
work/dmtd_with_deglitcher/.dmtd_with_deglitcher_vhd \
work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher_vhd \
work/hpll_period_detect/.hpll_period_detect_vhd \
work/minic_packet_buffer/.minic_packet_buffer_vhd \
work/minic_wb_slave/.minic_wb_slave_vhd \
work/endpoint_pkg/.endpoint_pkg_vhd \
work/softpll_wb/.softpll_wb_vhd \
work/wr_softpll/.wr_softpll_vhd \
work/wrc_lm32/.wrc_lm32_vhd \
work/dec_8b10b/.dec_8b10b_vhd \
work/enc_8b10b/.enc_8b10b_vhd \
work/wr_tbi_phy/.wr_tbi_phy_vhd \
work/wr_mini_nic/.wr_mini_nic_vhd \
work/ep_enc_8b10b/.ep_enc_8b10b_vhd \
work/ep_dec_8b10b/.ep_dec_8b10b_vhd \
work/ep_rx_pcs_tbi/.ep_rx_pcs_tbi_vhd \
work/ep_tx_pcs_tbi/.ep_tx_pcs_tbi_vhd \
work/ep_autonegotiation/.ep_autonegotiation_vhd \
work/ep_pcs_tbi_mdio_wb/.ep_pcs_tbi_mdio_wb_vhd \
work/ep_1000basex_pcs/.ep_1000basex_pcs_vhd \
work/ep_rx_crc_size_check/.ep_rx_crc_size_check_vhd \
work/ep_rx_deframer/.ep_rx_deframer_vhd \
work/ep_tx_framer/.ep_tx_framer_vhd \
work/ep_flow_control/.ep_flow_control_vhd \
work/ep_timestamping_unit/.ep_timestamping_unit_vhd \
work/ep_rmon_counters/.ep_rmon_counters_vhd \
work/ep_rx_buffer/.ep_rx_buffer_vhd \
work/ep_sync_detect/.ep_sync_detect_vhd \
work/ep_wishbone_controller/.ep_wishbone_controller_vhd \
work/ep_ts_counter/.ep_ts_counter_vhd \
work/wrsw_endpoint/.wrsw_endpoint_vhd \
work/pps_gen_wb/.pps_gen_wb_vhd \
work/wrsw_pps_gen/.wrsw_pps_gen_vhd \
work/wbconmax_pkg/.wbconmax_pkg_vhd \
work/wrc_dpram/.wrc_dpram_vhd \
work/wrcore_pkg/.wrcore_pkg_vhd \
work/wrc_periph/.wrc_periph_vhd \
work/wb_reset/.wb_reset_vhd \
work/fd_acam_timestamper/.fd_acam_timestamper_vhd \
work/gc_crc_gen/.gc_crc_gen_vhd \
work/gc_moving_average/.gc_moving_average_vhd \
work/gc_extend_pulse/.gc_extend_pulse_vhd \
work/gc_delay_gen/.gc_delay_gen_vhd \
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd \
work/gc_serial_dac/.gc_serial_dac_vhd \
work/gc_sync_ffs/.gc_sync_ffs_vhd \
work/fd_ring_buffer/.fd_ring_buffer_vhd \
work/fine_delay_core/.fine_delay_core_vhd \
work/generic_async_fifo/.generic_async_fifo_vhd \
work/generic_dpram/.generic_dpram_vhd \
work/generic_spram/.generic_spram_vhd \
work/generic_sync_fifo/.generic_sync_fifo_vhd \
work/wb_onewire_master/.wb_onewire_master_vhd \
work/xwb_onewire_master/.xwb_onewire_master_vhd \
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd \
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd \
work/i2c_master_top/.i2c_master_top_vhd \
work/wb_i2c_master/.wb_i2c_master_vhd \
work/xwb_i2c_master/.xwb_i2c_master_vhd \
work/xwb_bus_fanout/.xwb_bus_fanout_vhd \
work/wb_conmax_pri_dec/.wb_conmax_pri_dec_vhd \
work/wb_conmax_pri_enc/.wb_conmax_pri_enc_vhd \
work/wb_conmax_arb/.wb_conmax_arb_vhd \
work/wb_conmax_msel/.wb_conmax_msel_vhd \
work/wr_core/.wr_core_vhd \
work/wb_conmax_slave_if/.wb_conmax_slave_if_vhd \
work/wb_conmax_master_if/.wb_conmax_master_if_vhd \
work/wb_conmax_rf/.wb_conmax_rf_vhd \
work/wb_conmax_top/.wb_conmax_top_vhd \
work/wb_gpio_port/.wb_gpio_port_vhd \
work/xwb_gpio_port/.xwb_gpio_port_vhd \
work/wb_tics/.wb_tics_vhd \
work/uart_async_rx/.uart_async_rx_vhd \
work/uart_async_tx/.uart_async_tx_vhd \
work/uart_baud_gen/.uart_baud_gen_vhd \
work/uart_wb_slave/.uart_wb_slave_vhd \
work/wb_simple_uart/.wb_simple_uart_vhd \
work/vic_prio_enc/.vic_prio_enc_vhd \
work/wb_vic/.wb_vic_vhd \
work/wb_spi/.wb_spi_vhd \
work/xwb_spi/.xwb_spi_vhd \
work/wb_virtual_uart/.wb_virtual_uart_vhd \
work/wb_virtual_uart_slave/.wb_virtual_uart_slave_vhd \
work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
work/wbgen2_eic/.wbgen2_eic_vhd \
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
work/fd_wishbone_slave/.fd_wishbone_slave_vhd \
work/gn4124_core/.gn4124_core_vhd \
work/dma_controller/.dma_controller_vhd \
work/l2p_ser/.l2p_ser_vhd \
work/p2l_des/.p2l_des_vhd \
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd \
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd \
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd \
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd \
LIBS := work
LIB_IND := work/.work
......@@ -166,556 +311,984 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< .
clean:
rm -rf ./modelsim.ini $(LIBS) $(WORK_NAME)
rm -rf ./modelsim.ini $(LIBS)
.PHONY: clean
work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/main/.main: main.sv
vlog -work work $(VLOG_FLAGS) +incdir+. $< && mkdir -p work/main && touch work/main/.main
work/spi_clgen/.spi_clgen: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $< && mkdir -p work/spi_clgen && touch work/spi_clgen/.spi_clgen
work/spi_shift/.spi_shift: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $< && mkdir -p work/spi_shift && touch work/spi_shift/.spi_shift
work/spi_top/.spi_top: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $< && mkdir -p work/spi_top && touch work/spi_top/.spi_top
work/lm32_cpu/.lm32_cpu: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_cpu.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_cpu && touch work/lm32_cpu/.lm32_cpu
work/lm32_addsub/.lm32_addsub: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_addsub.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_addsub && touch work/lm32_addsub/.lm32_addsub
work/lm32_top/.lm32_top: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_top.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_top && touch work/lm32_top/.lm32_top
work/lm32_instruction_unit/.lm32_instruction_unit: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_instruction_unit.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_instruction_unit && touch work/lm32_instruction_unit/.lm32_instruction_unit
work/lm32_decoder/.lm32_decoder: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_decoder.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_decoder && touch work/lm32_decoder/.lm32_decoder
work/lm32_load_store_unit/.lm32_load_store_unit: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_load_store_unit.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_load_store_unit && touch work/lm32_load_store_unit/.lm32_load_store_unit
work/lm32_adder/.lm32_adder: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_adder.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_adder && touch work/lm32_adder/.lm32_adder
work/lm32_logic_op/.lm32_logic_op: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_logic_op.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_logic_op && touch work/lm32_logic_op/.lm32_logic_op
work/lm32_shifter/.lm32_shifter: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_shifter.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_shifter && touch work/lm32_shifter/.lm32_shifter
work/lm32_multiplier/.lm32_multiplier: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_multiplier.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_multiplier && touch work/lm32_multiplier/.lm32_multiplier
work/lm32_interrupt/.lm32_interrupt: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_interrupt.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_interrupt && touch work/lm32_interrupt/.lm32_interrupt
work/lm32_dp_ram/.lm32_dp_ram: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_dp_ram.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $< && mkdir -p work/lm32_dp_ram && touch work/lm32_dp_ram/.lm32_dp_ram
work/wbgen2_pkg/.wbgen2_pkg: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd && mkdir -p work/wbgen2_pkg && touch work/wbgen2_pkg/.wbgen2_pkg
work/fd_cal_pulse_gen/.fd_cal_pulse_gen: ../../rtl/fd_cal_pulse_gen.vhd
vcom $(VCOM_FLAGS) -work work ../../rtl/fd_cal_pulse_gen.vhd && mkdir -p work/fd_cal_pulse_gen && touch work/fd_cal_pulse_gen/.fd_cal_pulse_gen
work/fine_delay_pkg/.fine_delay_pkg: ../../rtl/fine_delay_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../rtl/fine_delay_pkg.vhd && mkdir -p work/fine_delay_pkg && touch work/fine_delay_pkg/.fine_delay_pkg
work/fd_wbgen2_pkg/.fd_wbgen2_pkg: ../../rtl/fd_wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../rtl/fd_wbgen2_pkg.vhd && mkdir -p work/fd_wbgen2_pkg && touch work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/main/.main_sv: main.sv ../../include/random_pulse_gen.sv ../../include/jittery_delay.sv ../../include/ideal_timestamper.sv ../../include/acam_model.sv ../../include/mc100ep195.sv ../../include/fine_delay_regs.v ../../include/tunable_clock_gen.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+. +incdir+../../include +incdir+../../include/wb $<
@mkdir -p $(dir $@) && touch $@
work/fd_wbgen2_pkg/.fd_wbgen2_pkg: \
work/wbgen2_pkg/.wbgen2_pkg
work/fine_delay_core/.fine_delay_core: ../../rtl/fine_delay_core.vhd
vcom $(VCOM_FLAGS) -work work ../../rtl/fine_delay_core.vhd && mkdir -p work/fine_delay_core && touch work/fine_delay_core/.fine_delay_core
work/lm32_cpu/.lm32_cpu_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_cpu.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/fine_delay_core/.fine_delay_core: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/fd_delay_line_driver/.fd_delay_line_driver: ../../rtl/fd_delay_line_driver.vhd
vcom $(VCOM_FLAGS) -work work ../../rtl/fd_delay_line_driver.vhd && mkdir -p work/fd_delay_line_driver && touch work/fd_delay_line_driver/.fd_delay_line_driver
work/lm32_addsub/.lm32_addsub_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_addsub.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/fd_delay_line_driver/.fd_delay_line_driver: \
work/fine_delay_pkg/.fine_delay_pkg
work/fd_acam_timestamper/.fd_acam_timestamper: ../../rtl/fd_acam_timestamper.vhd
vcom $(VCOM_FLAGS) -work work ../../rtl/fd_acam_timestamper.vhd && mkdir -p work/fd_acam_timestamper && touch work/fd_acam_timestamper/.fd_acam_timestamper
work/lm32_top/.lm32_top_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_top.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/fd_acam_timestamper/.fd_acam_timestamper: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/clock_generator_ddr_s2_diff/.clock_generator_ddr_s2_diff: ../../ip_cores/rtl/clock_generator_ddr_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/clock_generator_ddr_s2_diff.vhd && mkdir -p work/clock_generator_ddr_s2_diff && touch work/clock_generator_ddr_s2_diff/.clock_generator_ddr_s2_diff
work/lm32_instruction_unit/.lm32_instruction_unit_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_instruction_unit.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/clock_generator_pll_s2_diff/.clock_generator_pll_s2_diff: ../../ip_cores/rtl/clock_generator_pll_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/clock_generator_pll_s2_diff.vhd && mkdir -p work/clock_generator_pll_s2_diff && touch work/clock_generator_pll_s2_diff/.clock_generator_pll_s2_diff
work/gn4124_core_private_pkg/.gn4124_core_private_pkg: ../../ip_cores/rtl/spartan6/gn4124_core_private_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/spartan6/gn4124_core_private_pkg.vhd && mkdir -p work/gn4124_core_private_pkg && touch work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/lm32_decoder/.lm32_decoder_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_decoder.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/dma_controller_wb_slave/.dma_controller_wb_slave: ../../ip_cores/rtl/dma_controller_wb_slave.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/dma_controller_wb_slave.vhd && mkdir -p work/dma_controller_wb_slave && touch work/dma_controller_wb_slave/.dma_controller_wb_slave
work/gn4124_core_pkg/.gn4124_core_pkg: ../../ip_cores/rtl/gn4124_core_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/gn4124_core_pkg.vhd && mkdir -p work/gn4124_core_pkg && touch work/gn4124_core_pkg/.gn4124_core_pkg
work/lm32_load_store_unit/.lm32_load_store_unit_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_load_store_unit.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_functions.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/l2p_arbiter/.l2p_arbiter: ../../ip_cores/rtl/l2p_arbiter.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/l2p_arbiter.vhd && mkdir -p work/l2p_arbiter && touch work/l2p_arbiter/.l2p_arbiter
work/l2p_arbiter/.l2p_arbiter: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/lm32_adder/.lm32_adder_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_adder.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/genram_pkg/.genram_pkg: ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd && mkdir -p work/genram_pkg && touch work/genram_pkg/.genram_pkg
work/p2l_decode32/.p2l_decode32: ../../ip_cores/rtl/p2l_decode32.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/p2l_decode32.vhd && mkdir -p work/p2l_decode32 && touch work/p2l_decode32/.p2l_decode32
work/lm32_logic_op/.lm32_logic_op_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_logic_op.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/p2l_decode32/.p2l_decode32: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/p2l_dma_master/.p2l_dma_master: ../../ip_cores/rtl/p2l_dma_master.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/p2l_dma_master.vhd && mkdir -p work/p2l_dma_master && touch work/p2l_dma_master/.p2l_dma_master
work/lm32_shifter/.lm32_shifter_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_shifter.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/p2l_dma_master/.p2l_dma_master: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/genram_pkg/.genram_pkg
work/serdes_1_to_n_clk_ddr_s2_diff/.serdes_1_to_n_clk_ddr_s2_diff: ../../ip_cores/rtl/serdes_1_to_n_clk_ddr_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/serdes_1_to_n_clk_ddr_s2_diff.vhd && mkdir -p work/serdes_1_to_n_clk_ddr_s2_diff && touch work/serdes_1_to_n_clk_ddr_s2_diff/.serdes_1_to_n_clk_ddr_s2_diff
work/lm32_multiplier/.lm32_multiplier_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_multiplier.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff: ../../ip_cores/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd && mkdir -p work/serdes_1_to_n_clk_pll_s2_diff && touch work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff
work/serdes_1_to_n_data_ddr_s2_se/.serdes_1_to_n_data_ddr_s2_se: ../../ip_cores/rtl/serdes_1_to_n_data_ddr_s2_se.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/serdes_1_to_n_data_ddr_s2_se.vhd && mkdir -p work/serdes_1_to_n_data_ddr_s2_se && touch work/serdes_1_to_n_data_ddr_s2_se/.serdes_1_to_n_data_ddr_s2_se
work/lm32_interrupt/.lm32_interrupt_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_interrupt.v ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_include.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se: ../../ip_cores/rtl/serdes_1_to_n_data_s2_se.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/serdes_1_to_n_data_s2_se.vhd && mkdir -p work/serdes_1_to_n_data_s2_se && touch work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se
work/serdes_n_to_1_ddr_s2_diff/.serdes_n_to_1_ddr_s2_diff: ../../ip_cores/rtl/serdes_n_to_1_ddr_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/serdes_n_to_1_ddr_s2_diff.vhd && mkdir -p work/serdes_n_to_1_ddr_s2_diff && touch work/serdes_n_to_1_ddr_s2_diff/.serdes_n_to_1_ddr_s2_diff
work/lm32_dp_ram/.lm32_dp_ram_v: ../../ip_cores/wr-cores/modules/wrc_lm32/lm32_dp_ram.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/wr-cores/modules/wrc_lm32 $<
@mkdir -p $(dir $@) && touch $@
work/serdes_n_to_1_ddr_s2_se/.serdes_n_to_1_ddr_s2_se: ../../ip_cores/rtl/serdes_n_to_1_ddr_s2_se.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/serdes_n_to_1_ddr_s2_se.vhd && mkdir -p work/serdes_n_to_1_ddr_s2_se && touch work/serdes_n_to_1_ddr_s2_se/.serdes_n_to_1_ddr_s2_se
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff: ../../ip_cores/rtl/serdes_n_to_1_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/serdes_n_to_1_s2_diff.vhd && mkdir -p work/serdes_n_to_1_s2_diff && touch work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff
work/sockit_owm/.sockit_owm_v: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master $<
@mkdir -p $(dir $@) && touch $@
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se: ../../ip_cores/rtl/serdes_n_to_1_s2_se.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/serdes_n_to_1_s2_se.vhd && mkdir -p work/serdes_n_to_1_s2_se && touch work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se
work/wbmaster32/.wbmaster32: ../../ip_cores/rtl/wbmaster32.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/wbmaster32.vhd && mkdir -p work/wbmaster32 && touch work/wbmaster32/.wbmaster32
work/spi_clgen/.spi_clgen_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/wbmaster32/.wbmaster32: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/genram_pkg/.genram_pkg
work/gn4124_core/.gn4124_core: ../../ip_cores/rtl/spartan6/gn4124_core.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/spartan6/gn4124_core.vhd && mkdir -p work/gn4124_core && touch work/gn4124_core/.gn4124_core
work/spi_shift/.spi_shift_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/gn4124_core/.gn4124_core: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/dma_controller/.dma_controller: ../../ip_cores/rtl/dma_controller.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/dma_controller.vhd && mkdir -p work/dma_controller && touch work/dma_controller/.dma_controller
work/spi_top/.spi_top_v: ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog -work work $(VLOG_FLAGS) +incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/dma_controller/.dma_controller: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/l2p_ser/.l2p_ser: ../../ip_cores/rtl/spartan6/l2p_ser.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/spartan6/l2p_ser.vhd && mkdir -p work/l2p_ser && touch work/l2p_ser/.l2p_ser
work/l2p_ser/.l2p_ser: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/p2l_des/.p2l_des: ../../ip_cores/rtl/spartan6/p2l_des.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/spartan6/p2l_des.vhd && mkdir -p work/p2l_des && touch work/p2l_des/.p2l_des
work/p2l_des/.p2l_des: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/gencores_pkg/.gencores_pkg_vhd: ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gencores_pkg/.gencores_pkg: ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd && mkdir -p work/gencores_pkg && touch work/gencores_pkg/.gencores_pkg
work/gc_crc_gen/.gc_crc_gen: ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd && mkdir -p work/gc_crc_gen && touch work/gc_crc_gen/.gc_crc_gen
work/genram_pkg/.genram_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_crc_gen/.gc_crc_gen: \
work/gencores_pkg/.gencores_pkg
work/gc_moving_average/.gc_moving_average: ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd && mkdir -p work/gc_moving_average && touch work/gc_moving_average/.gc_moving_average
work/gc_moving_average/.gc_moving_average: \
work/gencores_pkg/.gencores_pkg
work/fd_ts_adder/.fd_ts_adder_vhd: ../../rtl/fd_ts_adder.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_extend_pulse/.gc_extend_pulse: ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd && mkdir -p work/gc_extend_pulse && touch work/gc_extend_pulse/.gc_extend_pulse
work/gc_extend_pulse/.gc_extend_pulse: \
work/gencores_pkg/.gencores_pkg
work/fd_ts_normalizer/.fd_ts_normalizer_vhd: ../../rtl/fd_ts_normalizer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_delay_gen/.gc_delay_gen: ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd && mkdir -p work/gc_delay_gen && touch work/gc_delay_gen/.gc_delay_gen
work/gc_delay_gen/.gc_delay_gen: \
work/gencores_pkg/.gencores_pkg
work/fd_wbgen2_pkg/.fd_wbgen2_pkg_vhd: ../../rtl/fd_wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_dual_pi_controller/.gc_dual_pi_controller: ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd && mkdir -p work/gc_dual_pi_controller && touch work/gc_dual_pi_controller/.gc_dual_pi_controller
work/gc_dual_pi_controller/.gc_dual_pi_controller: \
work/gencores_pkg/.gencores_pkg
work/fd_wbgen2_pkg/.fd_wbgen2_pkg: \
work/wbgen2_pkg/.wbgen2_pkg
work/gc_serial_dac/.gc_serial_dac: ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd && mkdir -p work/gc_serial_dac && touch work/gc_serial_dac/.gc_serial_dac
work/fd_csync_generator/.fd_csync_generator_vhd: ../../rtl/fd_csync_generator.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_sync_ffs/.gc_sync_ffs: ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd && mkdir -p work/gc_sync_ffs && touch work/gc_sync_ffs/.gc_sync_ffs
work/l2p_dma_master/.l2p_dma_master: ../../ip_cores/rtl/l2p_dma_master.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/rtl/l2p_dma_master.vhd && mkdir -p work/l2p_dma_master && touch work/l2p_dma_master/.l2p_dma_master
work/fd_csync_generator/.fd_csync_generator: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/l2p_dma_master/.l2p_dma_master: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/genram_pkg/.genram_pkg
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit_vhd: ../../rtl/fd_timestamper_stat_unit.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wishbone_pkg/.wishbone_pkg: ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd && mkdir -p work/wishbone_pkg && touch work/wishbone_pkg/.wishbone_pkg
work/wb_cpu_bridge/.wb_cpu_bridge: ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_cpu_bridge.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_cpu_bridge.vhd && mkdir -p work/wb_cpu_bridge && touch work/wb_cpu_bridge/.wb_cpu_bridge
work/fd_timestamper_stat_unit/.fd_timestamper_stat_unit: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/wb_cpu_bridge/.wb_cpu_bridge: \
work/gencores_pkg/.gencores_pkg \
work/wishbone_pkg/.wishbone_pkg
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor_vhd: ../../rtl/fd_acam_timestamp_postprocessor.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_pri_dec/.wb_conmax_pri_dec: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd && mkdir -p work/wb_conmax_pri_dec && touch work/wb_conmax_pri_dec/.wb_conmax_pri_dec
work/wb_conmax_pri_enc/.wb_conmax_pri_enc: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd && mkdir -p work/wb_conmax_pri_enc && touch work/wb_conmax_pri_enc/.wb_conmax_pri_enc
work/fd_acam_timestamp_postprocessor/.fd_acam_timestamp_postprocessor: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/wb_conmax_arb/.wb_conmax_arb: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd && mkdir -p work/wb_conmax_arb && touch work/wb_conmax_arb/.wb_conmax_arb
work/fine_delay_pkg/.fine_delay_pkg_vhd: ../../rtl/fine_delay_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_msel/.wb_conmax_msel: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd && mkdir -p work/wb_conmax_msel && touch work/wb_conmax_msel/.wb_conmax_msel
work/wbconmax_pkg/.wbconmax_pkg: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd && mkdir -p work/wbconmax_pkg && touch work/wbconmax_pkg/.wbconmax_pkg
work/fd_delay_line_arbiter/.fd_delay_line_arbiter_vhd: ../../rtl/fd_delay_line_arbiter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_slave_if/.wb_conmax_slave_if: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd && mkdir -p work/wb_conmax_slave_if && touch work/wb_conmax_slave_if/.wb_conmax_slave_if
work/wb_conmax_slave_if/.wb_conmax_slave_if: \
work/wbconmax_pkg/.wbconmax_pkg
work/fd_rearm_generator/.fd_rearm_generator_vhd: ../../rtl/fd_rearm_generator.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_master_if/.wb_conmax_master_if: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd && mkdir -p work/wb_conmax_master_if && touch work/wb_conmax_master_if/.wb_conmax_master_if
work/wb_conmax_master_if/.wb_conmax_master_if: \
work/wbconmax_pkg/.wbconmax_pkg
work/fd_reset_generator/.fd_reset_generator_vhd: ../../rtl/fd_reset_generator.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_rf/.wb_conmax_rf: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd && mkdir -p work/wb_conmax_rf && touch work/wb_conmax_rf/.wb_conmax_rf
work/wb_conmax_rf/.wb_conmax_rf: \
work/wbconmax_pkg/.wbconmax_pkg
work/fd_reset_generator/.fd_reset_generator: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/wb_conmax_top/.wb_conmax_top: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd && mkdir -p work/wb_conmax_top && touch work/wb_conmax_top/.wb_conmax_top
work/fd_spi_master/.fd_spi_master_vhd: ../../rtl/fd_spi_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_top/.wb_conmax_top: \
work/wbconmax_pkg/.wbconmax_pkg
work/wb_gpio_port/.wb_gpio_port: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd && mkdir -p work/wb_gpio_port && touch work/wb_gpio_port/.wb_gpio_port
work/fd_spi_dac_arbiter/.fd_spi_dac_arbiter_vhd: ../../rtl/fd_spi_dac_arbiter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_gpio_port/.wb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/wb_tics/.wb_tics: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd && mkdir -p work/wb_tics && touch work/wb_tics/.wb_tics
work/fd_spi_dac_arbiter/.fd_spi_dac_arbiter: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/uart_async_rx/.uart_async_rx: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd && mkdir -p work/uart_async_rx && touch work/uart_async_rx/.uart_async_rx
work/fd_delay_channel_driver/.fd_delay_channel_driver_vhd: ../../rtl/fd_delay_channel_driver.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_tx/.uart_async_tx: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd && mkdir -p work/uart_async_tx && touch work/uart_async_tx/.uart_async_tx
work/uart_baud_gen/.uart_baud_gen: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd && mkdir -p work/uart_baud_gen && touch work/uart_baud_gen/.uart_baud_gen
work/fd_delay_channel_driver/.fd_delay_channel_driver: \
work/fine_delay_pkg/.fine_delay_pkg
work/uart_wb_slave/.uart_wb_slave: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd && mkdir -p work/uart_wb_slave && touch work/uart_wb_slave/.uart_wb_slave
work/wishbone_pkg/.wishbone_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_simple_uart/.wb_simple_uart: ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd && mkdir -p work/wb_simple_uart && touch work/wb_simple_uart/.wb_simple_uart
work/vic_prio_enc/.vic_prio_enc: ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd && mkdir -p work/vic_prio_enc && touch work/vic_prio_enc/.vic_prio_enc
work/gn4124_core_private_pkg/.gn4124_core_private_pkg_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core_private_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_vic/.wb_vic: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd && mkdir -p work/wb_vic && touch work/wb_vic/.wb_vic
work/wb_vic/.wb_vic: \
work/wishbone_pkg/.wishbone_pkg
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller_wb_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_virtual_uart/.wb_virtual_uart: ../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd && mkdir -p work/wb_virtual_uart && touch work/wb_virtual_uart/.wb_virtual_uart
work/wb_virtual_uart_slave/.wb_virtual_uart_slave: ../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd && mkdir -p work/wb_virtual_uart_slave && touch work/wb_virtual_uart_slave/.wb_virtual_uart_slave
work/gn4124_core_pkg/.gn4124_core_pkg_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/gn4124_core_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_virtual_uart_slave/.wb_virtual_uart_slave: \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_dpssram/.wbgen2_dpssram: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd && mkdir -p work/wbgen2_dpssram && touch work/wbgen2_dpssram/.wbgen2_dpssram
work/l2p_arbiter/.l2p_arbiter_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/l2p_arbiter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_dpssram/.wbgen2_dpssram: \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_eic/.wbgen2_eic: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd && mkdir -p work/wbgen2_eic && touch work/wbgen2_eic/.wbgen2_eic
work/l2p_arbiter/.l2p_arbiter: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/wbgen2_eic/.wbgen2_eic: \
work/wbgen2_pkg/.wbgen2_pkg
work/l2p_dma_master/.l2p_dma_master_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/l2p_dma_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_fifo_async/.wbgen2_fifo_async: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd && mkdir -p work/wbgen2_fifo_async && touch work/wbgen2_fifo_async/.wbgen2_fifo_async
work/wbgen2_fifo_async/.wbgen2_fifo_async: \
work/genram_pkg/.genram_pkg \
work/wbgen2_pkg/.wbgen2_pkg
work/l2p_dma_master/.l2p_dma_master: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/genram_pkg/.genram_pkg
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd && mkdir -p work/wbgen2_fifo_sync && touch work/wbgen2_fifo_sync/.wbgen2_fifo_sync
work/p2l_decode32/.p2l_decode32_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/p2l_decode32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
work/wbgen2_pkg/.wbgen2_pkg
work/fine_delay_wb/.fine_delay_wb: ../../rtl/fine_delay_wb.vhd
vcom $(VCOM_FLAGS) -work work ../../rtl/fine_delay_wb.vhd && mkdir -p work/fine_delay_wb && touch work/fine_delay_wb/.fine_delay_wb
work/p2l_decode32/.p2l_decode32: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/fine_delay_wb/.fine_delay_wb: \
work/wbgen2_pkg/.wbgen2_pkg \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg
work/p2l_dma_master/.p2l_dma_master_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/p2l_dma_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_async_fifo/.generic_async_fifo: ../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd && mkdir -p work/generic_async_fifo && touch work/generic_async_fifo/.generic_async_fifo
work/generic_async_fifo/.generic_async_fifo: \
work/p2l_dma_master/.p2l_dma_master: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/genram_pkg/.genram_pkg
work/generic_dpram/.generic_dpram: ../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd && mkdir -p work/generic_dpram && touch work/generic_dpram/.generic_dpram
work/generic_dpram/.generic_dpram: \
work/genram_pkg/.genram_pkg
work/wbmaster32/.wbmaster32_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/wbmaster32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_spram/.generic_spram: ../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd && mkdir -p work/generic_spram && touch work/generic_spram/.generic_spram
work/generic_spram/.generic_spram: \
work/wbmaster32/.wbmaster32: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg \
work/genram_pkg/.genram_pkg
work/generic_sync_fifo/.generic_sync_fifo: ../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd && mkdir -p work/generic_sync_fifo && touch work/generic_sync_fifo/.generic_sync_fifo
work/gtp_bitslide/.gtp_bitslide_vhd: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_sync_fifo/.generic_sync_fifo: \
work/genram_pkg/.genram_pkg
work/gtp_bitslide/.gtp_bitslide: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd && mkdir -p work/gtp_bitslide && touch work/gtp_bitslide/.gtp_bitslide
work/gtp_phase_align/.gtp_phase_align_vhd: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gtp_phase_align/.gtp_phase_align: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd && mkdir -p work/gtp_phase_align && touch work/gtp_phase_align/.gtp_phase_align
work/whiterabbitgtp_wrapper_tile/.whiterabbitgtp_wrapper_tile_vhd: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/whiterabbitgtp_wrapper/.whiterabbitgtp_wrapper: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd && mkdir -p work/whiterabbitgtp_wrapper && touch work/whiterabbitgtp_wrapper/.whiterabbitgtp_wrapper
work/whiterabbitgtp_wrapper_tile/.whiterabbitgtp_wrapper_tile: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd && mkdir -p work/whiterabbitgtp_wrapper_tile && touch work/whiterabbitgtp_wrapper_tile/.whiterabbitgtp_wrapper_tile
work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6_vhd: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6: ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd && mkdir -p work/wr_gtp_phy_spartan6 && touch work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6
work/wr_gtp_phy_spartan6/.wr_gtp_phy_spartan6: \
work/gencores_pkg/.gencores_pkg
work/dmtd_phase_meas/.dmtd_phase_meas: ../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd && mkdir -p work/dmtd_phase_meas && touch work/dmtd_phase_meas/.dmtd_phase_meas
work/dmtd_phase_meas/.dmtd_phase_meas_vhd: ../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dmtd_phase_meas/.dmtd_phase_meas: \
work/gencores_pkg/.gencores_pkg
work/dmtd_with_deglitcher/.dmtd_with_deglitcher: ../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd && mkdir -p work/dmtd_with_deglitcher && touch work/dmtd_with_deglitcher/.dmtd_with_deglitcher
work/dmtd_with_deglitcher/.dmtd_with_deglitcher_vhd: ../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dmtd_with_deglitcher/.dmtd_with_deglitcher: \
work/gencores_pkg/.gencores_pkg
work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher: ../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd && mkdir -p work/multi_dmtd_with_deglitcher && touch work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher
work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher_vhd: ../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/multi_dmtd_with_deglitcher/.multi_dmtd_with_deglitcher: \
work/gencores_pkg/.gencores_pkg
work/hpll_period_detect/.hpll_period_detect: ../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd && mkdir -p work/hpll_period_detect && touch work/hpll_period_detect/.hpll_period_detect
work/hpll_period_detect/.hpll_period_detect_vhd: ../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/hpll_period_detect/.hpll_period_detect: \
work/gencores_pkg/.gencores_pkg
work/minic_packet_buffer/.minic_packet_buffer: ../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd && mkdir -p work/minic_packet_buffer && touch work/minic_packet_buffer/.minic_packet_buffer
work/minic_packet_buffer/.minic_packet_buffer_vhd: ../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/minic_packet_buffer/.minic_packet_buffer: \
work/genram_pkg/.genram_pkg
work/minic_wb_slave/.minic_wb_slave: ../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd && mkdir -p work/minic_wb_slave && touch work/minic_wb_slave/.minic_wb_slave
work/minic_wb_slave/.minic_wb_slave_vhd: ../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/minic_wb_slave/.minic_wb_slave: \
work/wbgen2_pkg/.wbgen2_pkg
work/endpoint_pkg/.endpoint_pkg: ../../ip_cores/wr-cores/modules/wrsw_endpoint/endpoint_pkg.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/endpoint_pkg.vhd && mkdir -p work/endpoint_pkg && touch work/endpoint_pkg/.endpoint_pkg
work/endpoint_pkg/.endpoint_pkg_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/endpoint_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/softpll_wb/.softpll_wb_vhd: ../../ip_cores/wr-cores/modules/wr_softpll/softpll_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/softpll_wb/.softpll_wb: ../../ip_cores/wr-cores/modules/wr_softpll/softpll_wb.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wr_softpll/softpll_wb.vhd && mkdir -p work/softpll_wb && touch work/softpll_wb/.softpll_wb
work/softpll_wb/.softpll_wb: \
work/wbgen2_pkg/.wbgen2_pkg
work/wr_softpll/.wr_softpll: ../../ip_cores/wr-cores/modules/wr_softpll/wr_softpll.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wr_softpll/wr_softpll.vhd && mkdir -p work/wr_softpll && touch work/wr_softpll/.wr_softpll
work/wr_softpll/.wr_softpll_vhd: ../../ip_cores/wr-cores/modules/wr_softpll/wr_softpll.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_softpll/.wr_softpll: \
work/gencores_pkg/.gencores_pkg
work/wrc_lm32/.wrc_lm32: ../../ip_cores/wr-cores/modules/wrc_lm32/wrc_lm32.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrc_lm32/wrc_lm32.vhd && mkdir -p work/wrc_lm32 && touch work/wrc_lm32/.wrc_lm32
work/wrc_lm32/.wrc_lm32_vhd: ../../ip_cores/wr-cores/modules/wrc_lm32/wrc_lm32.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dec_8b10b/.dec_8b10b_vhd: ../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/enc_8b10b/.enc_8b10b_vhd: ../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_tbi_phy/.wr_tbi_phy_vhd: ../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_tbi_phy/.wr_tbi_phy: \
work/gencores_pkg/.gencores_pkg
work/wr_mini_nic/.wr_mini_nic_vhd: ../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_mini_nic/.wr_mini_nic: ../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd && mkdir -p work/wr_mini_nic && touch work/wr_mini_nic/.wr_mini_nic
work/wr_mini_nic/.wr_mini_nic: \
work/endpoint_pkg/.endpoint_pkg
work/ep_enc_8b10b/.ep_enc_8b10b: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_enc_8b10b.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_enc_8b10b.vhd && mkdir -p work/ep_enc_8b10b && touch work/ep_enc_8b10b/.ep_enc_8b10b
work/ep_enc_8b10b/.ep_enc_8b10b_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_enc_8b10b.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_dec_8b10b/.ep_dec_8b10b_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_dec_8b10b.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_dec_8b10b/.ep_dec_8b10b: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_dec_8b10b.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_dec_8b10b.vhd && mkdir -p work/ep_dec_8b10b && touch work/ep_dec_8b10b/.ep_dec_8b10b
work/ep_rx_pcs_tbi/.ep_rx_pcs_tbi: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd && mkdir -p work/ep_rx_pcs_tbi && touch work/ep_rx_pcs_tbi/.ep_rx_pcs_tbi
work/ep_rx_pcs_tbi/.ep_rx_pcs_tbi_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_pcs_tbi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rx_pcs_tbi/.ep_rx_pcs_tbi: \
work/gencores_pkg/.gencores_pkg \
work/endpoint_pkg/.endpoint_pkg \
work/genram_pkg/.genram_pkg \
work/endpoint_pkg/.endpoint_pkg
work/gencores_pkg/.gencores_pkg
work/ep_tx_pcs_tbi/.ep_tx_pcs_tbi_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_tx_pcs_tbi/.ep_tx_pcs_tbi: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_pcs_tbi.vhd && mkdir -p work/ep_tx_pcs_tbi && touch work/ep_tx_pcs_tbi/.ep_tx_pcs_tbi
work/ep_tx_pcs_tbi/.ep_tx_pcs_tbi: \
work/gencores_pkg/.gencores_pkg \
work/endpoint_pkg/.endpoint_pkg \
work/genram_pkg/.genram_pkg \
work/endpoint_pkg/.endpoint_pkg
work/gencores_pkg/.gencores_pkg
work/ep_autonegotiation/.ep_autonegotiation_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_autonegotiation.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_autonegotiation/.ep_autonegotiation: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_autonegotiation.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_autonegotiation.vhd && mkdir -p work/ep_autonegotiation && touch work/ep_autonegotiation/.ep_autonegotiation
work/ep_autonegotiation/.ep_autonegotiation: \
work/endpoint_pkg/.endpoint_pkg
work/ep_pcs_tbi_mdio_wb/.ep_pcs_tbi_mdio_wb: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd && mkdir -p work/ep_pcs_tbi_mdio_wb && touch work/ep_pcs_tbi_mdio_wb/.ep_pcs_tbi_mdio_wb
work/ep_pcs_tbi_mdio_wb/.ep_pcs_tbi_mdio_wb_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_pcs_tbi_mdio_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_1000basex_pcs/.ep_1000basex_pcs_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_1000basex_pcs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_1000basex_pcs/.ep_1000basex_pcs: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_1000basex_pcs.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_1000basex_pcs.vhd && mkdir -p work/ep_1000basex_pcs && touch work/ep_1000basex_pcs/.ep_1000basex_pcs
work/ep_1000basex_pcs/.ep_1000basex_pcs: \
work/endpoint_pkg/.endpoint_pkg
work/ep_rx_crc_size_check/.ep_rx_crc_size_check: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_crc_size_check.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_crc_size_check.vhd && mkdir -p work/ep_rx_crc_size_check && touch work/ep_rx_crc_size_check/.ep_rx_crc_size_check
work/ep_rx_crc_size_check/.ep_rx_crc_size_check_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_crc_size_check.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rx_crc_size_check/.ep_rx_crc_size_check: \
work/gencores_pkg/.gencores_pkg \
work/endpoint_pkg/.endpoint_pkg
work/endpoint_pkg/.endpoint_pkg \
work/gencores_pkg/.gencores_pkg
work/ep_rx_deframer/.ep_rx_deframer_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_deframer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rx_deframer/.ep_rx_deframer: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_deframer.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_deframer.vhd && mkdir -p work/ep_rx_deframer && touch work/ep_rx_deframer/.ep_rx_deframer
work/ep_rx_deframer/.ep_rx_deframer: \
work/endpoint_pkg/.endpoint_pkg
work/ep_tx_framer/.ep_tx_framer: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_framer.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_framer.vhd && mkdir -p work/ep_tx_framer && touch work/ep_tx_framer/.ep_tx_framer
work/ep_tx_framer/.ep_tx_framer_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_tx_framer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_tx_framer/.ep_tx_framer: \
work/gencores_pkg/.gencores_pkg \
work/endpoint_pkg/.endpoint_pkg
work/endpoint_pkg/.endpoint_pkg \
work/gencores_pkg/.gencores_pkg
work/ep_flow_control/.ep_flow_control_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_flow_control.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_flow_control/.ep_flow_control: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_flow_control.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_flow_control.vhd && mkdir -p work/ep_flow_control && touch work/ep_flow_control/.ep_flow_control
work/ep_flow_control/.ep_flow_control: \
work/endpoint_pkg/.endpoint_pkg
work/ep_timestamping_unit/.ep_timestamping_unit: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_timestamping_unit.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_timestamping_unit.vhd && mkdir -p work/ep_timestamping_unit && touch work/ep_timestamping_unit/.ep_timestamping_unit
work/ep_timestamping_unit/.ep_timestamping_unit_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_timestamping_unit.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_timestamping_unit/.ep_timestamping_unit: \
work/gencores_pkg/.gencores_pkg \
work/endpoint_pkg/.endpoint_pkg
work/endpoint_pkg/.endpoint_pkg \
work/gencores_pkg/.gencores_pkg
work/ep_rmon_counters/.ep_rmon_counters_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rmon_counters.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rmon_counters/.ep_rmon_counters: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rmon_counters.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rmon_counters.vhd && mkdir -p work/ep_rmon_counters && touch work/ep_rmon_counters/.ep_rmon_counters
work/ep_rmon_counters/.ep_rmon_counters: \
work/endpoint_pkg/.endpoint_pkg
work/ep_rx_buffer/.ep_rx_buffer: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_buffer.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_buffer.vhd && mkdir -p work/ep_rx_buffer && touch work/ep_rx_buffer/.ep_rx_buffer
work/ep_rx_buffer/.ep_rx_buffer_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_rx_buffer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_rx_buffer/.ep_rx_buffer: \
work/endpoint_pkg/.endpoint_pkg \
work/genram_pkg/.genram_pkg
work/ep_sync_detect/.ep_sync_detect: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_sync_detect.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_sync_detect.vhd && mkdir -p work/ep_sync_detect && touch work/ep_sync_detect/.ep_sync_detect
work/ep_sync_detect/.ep_sync_detect_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_sync_detect.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_sync_detect/.ep_sync_detect: \
work/endpoint_pkg/.endpoint_pkg
work/ep_wishbone_controller/.ep_wishbone_controller: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_wishbone_controller.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_wishbone_controller.vhd && mkdir -p work/ep_wishbone_controller && touch work/ep_wishbone_controller/.ep_wishbone_controller
work/ep_wishbone_controller/.ep_wishbone_controller_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_wishbone_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_wishbone_controller/.ep_wishbone_controller: \
work/wbgen2_pkg/.wbgen2_pkg
work/ep_ts_counter/.ep_ts_counter: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_ts_counter.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_ts_counter.vhd && mkdir -p work/ep_ts_counter && touch work/ep_ts_counter/.ep_ts_counter
work/ep_ts_counter/.ep_ts_counter_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/ep_ts_counter.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ep_ts_counter/.ep_ts_counter: \
work/endpoint_pkg/.endpoint_pkg
work/wrsw_endpoint/.wrsw_endpoint: ../../ip_cores/wr-cores/modules/wrsw_endpoint/wrsw_endpoint.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_endpoint/wrsw_endpoint.vhd && mkdir -p work/wrsw_endpoint && touch work/wrsw_endpoint/.wrsw_endpoint
work/wrsw_endpoint/.wrsw_endpoint_vhd: ../../ip_cores/wr-cores/modules/wrsw_endpoint/wrsw_endpoint.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrsw_endpoint/.wrsw_endpoint: \
work/gencores_pkg/.gencores_pkg \
work/endpoint_pkg/.endpoint_pkg
work/endpoint_pkg/.endpoint_pkg \
work/gencores_pkg/.gencores_pkg
work/pps_gen_wb/.pps_gen_wb_vhd: ../../ip_cores/wr-cores/modules/wrsw_pps_gen/pps_gen_wb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/pps_gen_wb/.pps_gen_wb: ../../ip_cores/wr-cores/modules/wrsw_pps_gen/pps_gen_wb.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_pps_gen/pps_gen_wb.vhd && mkdir -p work/pps_gen_wb && touch work/pps_gen_wb/.pps_gen_wb
work/wrsw_pps_gen/.wrsw_pps_gen: ../../ip_cores/wr-cores/modules/wrsw_pps_gen/wrsw_pps_gen.vhd
vcom $(VCOM_FLAGS) -work work ../../ip_cores/wr-cores/modules/wrsw_pps_gen/wrsw_pps_gen.vhd && mkdir -p work/wrsw_pps_gen && touch work/wrsw_pps_gen/.wrsw_pps_gen
work/wrsw_pps_gen/.wrsw_pps_gen_vhd: ../../ip_cores/wr-cores/modules/wrsw_pps_gen/wrsw_pps_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrsw_pps_gen/.wrsw_pps_gen: \
work/gencores_pkg/.gencores_pkg
work/wbconmax_pkg/.wbconmax_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrc_dpram/.wrc_dpram_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrc_dpram/.wrc_dpram: \
work/genram_pkg/.genram_pkg
work/wrcore_pkg/.wrcore_pkg_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrcore_pkg/.wrcore_pkg: \
work/genram_pkg/.genram_pkg \
work/wbconmax_pkg/.wbconmax_pkg
work/wrc_periph/.wrc_periph_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wrc_periph/.wrc_periph: \
work/wrcore_pkg/.wrcore_pkg
work/wb_reset/.wb_reset_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_acam_timestamper/.fd_acam_timestamper_vhd: ../../rtl/fd_acam_timestamper.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_acam_timestamper/.fd_acam_timestamper: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg \
work/gencores_pkg/.gencores_pkg
work/gc_crc_gen/.gc_crc_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_crc_gen/.gc_crc_gen: \
work/gencores_pkg/.gencores_pkg
work/gc_moving_average/.gc_moving_average_vhd: ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_moving_average/.gc_moving_average: \
work/gencores_pkg/.gencores_pkg
work/gc_extend_pulse/.gc_extend_pulse_vhd: ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_extend_pulse/.gc_extend_pulse: \
work/gencores_pkg/.gencores_pkg
work/gc_delay_gen/.gc_delay_gen_vhd: ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_delay_gen/.gc_delay_gen: \
work/gencores_pkg/.gencores_pkg
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_dual_pi_controller/.gc_dual_pi_controller: \
work/gencores_pkg/.gencores_pkg
work/gc_serial_dac/.gc_serial_dac_vhd: ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gc_sync_ffs/.gc_sync_ffs_vhd: ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_ring_buffer/.fd_ring_buffer_vhd: ../../rtl/fd_ring_buffer.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_ring_buffer/.fd_ring_buffer: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg \
work/genram_pkg/.genram_pkg
work/fine_delay_core/.fine_delay_core_vhd: ../../rtl/fine_delay_core.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fine_delay_core/.fine_delay_core: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/generic_async_fifo/.generic_async_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_async_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_async_fifo/.generic_async_fifo: \
work/genram_pkg/.genram_pkg
work/generic_dpram/.generic_dpram_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram/.generic_dpram: \
work/genram_pkg/.genram_pkg
work/generic_spram/.generic_spram_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_spram/.generic_spram: \
work/genram_pkg/.genram_pkg
work/generic_sync_fifo/.generic_sync_fifo_vhd: ../../ip_cores/general-cores/modules/genrams/altera/generic_sync_fifo.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/generic_sync_fifo/.generic_sync_fifo: \
work/genram_pkg/.genram_pkg
work/wb_onewire_master/.wb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_onewire_master/.wb_onewire_master: \
work/gencores_pkg/.gencores_pkg
work/xwb_onewire_master/.xwb_onewire_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_onewire_master/.xwb_onewire_master: \
work/wishbone_pkg/.wishbone_pkg
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/i2c_master_top/.i2c_master_top_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_i2c_master/.wb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_i2c_master/.wb_i2c_master: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_i2c_master/.xwb_i2c_master_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_i2c_master/.xwb_i2c_master: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_bus_fanout/.xwb_bus_fanout: \
work/wishbone_pkg/.wishbone_pkg
work/wb_conmax_pri_dec/.wb_conmax_pri_dec_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_pri_enc/.wb_conmax_pri_enc_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_arb/.wb_conmax_arb_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_msel/.wb_conmax_msel_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_core/.wr_core_vhd: ../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wr_core/.wr_core: \
work/genram_pkg/.genram_pkg \
work/wbconmax_pkg/.wbconmax_pkg \
work/wrcore_pkg/.wrcore_pkg
work/wb_conmax_slave_if/.wb_conmax_slave_if_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_slave_if/.wb_conmax_slave_if: \
work/wbconmax_pkg/.wbconmax_pkg
work/wb_conmax_master_if/.wb_conmax_master_if_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_master_if/.wb_conmax_master_if: \
work/wbconmax_pkg/.wbconmax_pkg
work/wb_conmax_rf/.wb_conmax_rf_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_rf/.wb_conmax_rf: \
work/wbconmax_pkg/.wbconmax_pkg
work/wb_conmax_top/.wb_conmax_top_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_conmax_top/.wb_conmax_top: \
work/wbconmax_pkg/.wbconmax_pkg
work/wb_gpio_port/.wb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_gpio_port/.wb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg \
work/gencores_pkg/.gencores_pkg
work/xwb_gpio_port/.xwb_gpio_port_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_gpio_port/.xwb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg
work/wb_tics/.wb_tics_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_rx/.uart_async_rx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_tx/.uart_async_tx_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_baud_gen/.uart_baud_gen_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/uart_wb_slave/.uart_wb_slave_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_wb_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_simple_uart/.wb_simple_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/vic_prio_enc/.vic_prio_enc_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_vic/.wb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_vic/.wb_vic: \
work/wishbone_pkg/.wishbone_pkg
work/wb_spi/.wb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_spi/.wb_spi: \
work/wishbone_pkg/.wishbone_pkg
work/xwb_spi/.xwb_spi_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_spi/.xwb_spi: \
work/wishbone_pkg/.wishbone_pkg
work/wb_virtual_uart/.wb_virtual_uart_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_virtual_uart_slave/.wb_virtual_uart_slave_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_virtual_uart_slave/.wb_virtual_uart_slave: \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_dpssram/.wbgen2_dpssram: \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_eic/.wbgen2_eic_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_eic/.wbgen2_eic: \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_fifo_async/.wbgen2_fifo_async: \
work/genram_pkg/.genram_pkg \
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
work/wbgen2_pkg/.wbgen2_pkg
work/fd_wishbone_slave/.fd_wishbone_slave_vhd: ../../rtl/fd_wishbone_slave.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/fd_wishbone_slave/.fd_wishbone_slave: \
work/fd_wbgen2_pkg/.fd_wbgen2_pkg \
work/wbgen2_pkg/.wbgen2_pkg
work/gn4124_core/.gn4124_core_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/gn4124_core.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gn4124_core/.gn4124_core: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/dma_controller/.dma_controller_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/dma_controller.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/dma_controller/.dma_controller: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/l2p_ser/.l2p_ser_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/l2p_ser.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/l2p_ser/.l2p_ser: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/p2l_des/.p2l_des_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/p2l_des.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/p2l_des/.p2l_des: \
work/gn4124_core_private_pkg/.gn4124_core_private_pkg
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd: ../../ip_cores/gn4124-core/branches/hdlmake-compliant/rtl/spartan6/serdes_n_to_1_s2_se.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
hdl/testbench/top/main.sv
View file @ 3e17d062
......@@ -217,7 +217,9 @@ class CSimDrv_FineDelay;
task force_cal_pulse(int channel, int delay_setpoint);
m_acc.write(`ADDR_FD_FRR1 + (channel * 'h20), delay_setpoint);
m_acc.write(`ADDR_FD_DCR1 + (channel * 'h20), `FD_DCR1_FORCE_CP | `FD_DCR1_POL);
m_acc.write(`ADDR_FD_DCR1 + (channel * 'h20), `FD_DCR1_FORCE_DLY | `FD_DCR1_POL);
m_acc.write(`ADDR_FD_TDCSR, `FD_TDCSR_CAL_PULSE);
endtask // force_cal_pulse
endclass // CSimDrv_FineDelay
......@@ -540,12 +542,12 @@ module main;
fd_drv = new(wb);
fd_drv.init();
fd_drv.config_output(0,1, 1000000, 200000);
// fd_drv.config_output(0,1, 1000000, 200000);
// fd_drv.config_output(1,1, 1100500, 200000);
// fd_drv.config_output(2,1, 1100900, 200000);
// fd_drv.config_output(3,1, 1110100, 200000);
// fd_drv.force_cal_pulse(0, 100);
fd_drv.force_cal_pulse(0, 100);
// #(320ns);
// fd_drv.force_cal_pulse(0, 200);
......
hdl/testbench/top/wave.do
View file @ 3e17d062
......@@ -4,11 +4,6 @@ add wave -noupdate /main/DUT/clk_ref_i
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/trig_a_n_i
add wave -noupdate /main/DUT/delay_pulse_o(0)
add wave -noupdate /main/DUT/chx_rearm
add wave -noupdate -expand /main/DUT/U_Acam_TSU/trig_d
add wave -noupdate /main/DUT/U_Acam_TSU/trig_pulse
add wave -noupdate /main/DUT/U_Acam_TSU/tag_enable
add wave -noupdate /main/DUT/trig_cal_o
add wave -noupdate /main/DUT/tdc_start_i
add wave -noupdate /main/DUT/led_trig_o
......@@ -33,7 +28,7 @@ add wave -noupdate /main/DUT/spi_mosi_o
add wave -noupdate /main/DUT/spi_miso_i
add wave -noupdate /main/DUT/delay_len_o
add wave -noupdate /main/DUT/delay_val_o
add wave -noupdate -expand /main/DUT/delay_pulse_o
add wave -noupdate /main/DUT/delay_pulse_o
add wave -noupdate /main/DUT/wr_time_valid_i
add wave -noupdate /main/DUT/wr_coarse_i
add wave -noupdate /main/DUT/wr_utc_i
......@@ -66,6 +61,7 @@ add wave -noupdate /main/DUT/tdc_rearm_p1
add wave -noupdate /main/DUT/tdc_start_p1
add wave -noupdate /main/DUT/dcr_enable_vec
add wave -noupdate /main/DUT/dcr_mode_vec
add wave -noupdate /main/DUT/chx_rearm
add wave -noupdate /main/DUT/chx_delay_pulse
add wave -noupdate /main/DUT/chx_delay_value
add wave -noupdate /main/DUT/chx_delay_load
......@@ -83,8 +79,10 @@ add wave -noupdate /main/DUT/regs_towb
add wave -noupdate /main/DUT/spi_cs_vec
add wave -noupdate /main/DUT/owr_en_int
add wave -noupdate /main/DUT/owr_int
add wave -noupdate /main/DUT/dbg
add wave -noupdate /main/DUT/gen_cal_pulse
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8140001510 fs} 0}
WaveRestoreCursors {{Cursor 1} {3716002840 fs} 0}
configure wave -namecolwidth 413
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -99,4 +97,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {16800 ns}
WaveRestoreZoom {3191002840 fs} {4241002840 fs}
hdl/top/spec_1_1/spec_top.vhd
View file @ 3e17d062
......@@ -96,6 +96,7 @@ entity spec_top is
fd_delay_val_o : out std_logic_vector(9 downto 0);
fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fmc_scl_b : inout std_logic;
fmc_sda_b : inout std_logic;
onewire_b : inout std_logic
......@@ -320,48 +321,58 @@ architecture rtl of spec_top is
component fine_delay_core
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
trig_a_n_i : in std_logic;
trig_cal_o : out std_logic;
tdc_start_i : in std_logic;
acam_a_o : out std_logic_vector(3 downto 0);
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oen_o : out std_logic;
acam_err_i : in std_logic;
acam_int_i : in std_logic;
acam_emptyf_i : in std_logic;
acam_alutrigger_o : out std_logic;
acam_cs_n_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_stop_dis_o : out std_logic;
led_trig_o : out std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
delay_len_o : out std_logic_vector(3 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_pulse_o : out std_logic_vector(3 downto 0);
owr_en_o : out std_logic;
owr_i : in std_logic;
wr_time_valid_i : in std_logic;
wr_coarse_i : in std_logic_vector(27 downto 0);
wr_utc_i : in std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic);
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
trig_a_n_i : in std_logic;
trig_cal_o : out std_logic;
tdc_start_i : in std_logic;
acam_a_o : out std_logic_vector(3 downto 0);
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oen_o : out std_logic;
acam_err_i : in std_logic;
acam_int_i : in std_logic;
acam_emptyf_i : in std_logic;
acam_alutrigger_o : out std_logic;
acam_cs_n_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_stop_dis_o : out std_logic;
led_trig_o : out std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
delay_len_o : out std_logic_vector(3 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_pulse_o : out std_logic_vector(3 downto 0);
owr_en_o : out std_logic;
owr_i : in std_logic;
tm_time_valid_i : in std_logic := '0';
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
tm_utc_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_clk_aux_lock_en_o : out std_logic;
tm_clk_aux_locked_i : in std_logic := '0';
tm_dac_value_i : in std_logic_vector(23 downto 0) := x"000000";
tm_dac_wr_i : in std_logic := '0';
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_o : out std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic);
end component;
signal rst_n : std_logic;
......@@ -590,7 +601,6 @@ begin
end if;
end process;
--fd_tdc_oe_n_o <= '1';
......@@ -630,35 +640,19 @@ begin
master_o => cnx_out);
cnx_in(2).int <= '0';
cnx_in(2).ack <= '0';
cnx_in(2).ack <= '1';
cnx_in(2).rty <= '0';
cnx_in(2).err <= '0';
cnx_in(0).int <= '0';
cnx_in(0).ack <= '1';
cnx_in(0).rty <= '0';
cnx_in(0).err <= '0';
U_I2C : xwb_i2c_master
generic map (
g_interface_mode => CLASSIC)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n,
slave_i => cnx_out(0),
slave_o => cnx_in(0),
desc_o => open,
scl_pad_i => scl_pad_in,
scl_pad_o => scl_pad_out,
scl_padoen_o => scl_pad_oen,
sda_pad_i => sda_pad_in,
sda_pad_o => sda_pad_out,
sda_padoen_o => sda_pad_oen);
fmc_scl_b <= scl_pad_out when scl_pad_oen = '0' else 'Z';
fmc_sda_b <= sda_pad_out when sda_pad_oen = '0' else 'Z';
scl_pad_in <= fmc_scl_b;
sda_pad_in <= fmc_sda_b;
U_DELAY_CORE : fine_delay_core
port map (
......@@ -682,9 +676,7 @@ begin
acam_rd_n_o => fd_tdc_rd_n_o,
acam_start_dis_o => fd_tdc_start_dis_o,
acam_stop_dis_o => fd_tdc_stop_dis_o,
wr_time_valid_i => '0',
wr_utc_i => x"00000000",
wr_coarse_i => x"0000000",
tm_time_valid_i=>'0',
spi_cs_dac_n_o => fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd_spi_cs_gpio_n_o,
......@@ -694,6 +686,12 @@ begin
delay_len_o => fd_delay_len_o,
delay_val_o => fd_delay_val_o,
delay_pulse_o => fd_delay_pulse_o,
i2c_scl_i => fmc_scl_b,
i2c_scl_o => scl_pad_out,
i2c_scl_oen_o => scl_pad_oen,
i2c_sda_i => fmc_sda_b,
i2c_sda_o => sda_pad_out,
i2c_sda_oen_o => sda_pad_oen,
owr_i => onewire_b,
owr_en_o => onewire_en,
wb_adr_i => cnx_out(1).adr(7 downto 0),
......
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