Commit 3df0b32d authored by Federico Vaga's avatar Federico Vaga

Merge branch 'release/v3.0.8' into master

parents dc471ac5 a26f0d6f
......@@ -16,9 +16,6 @@
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
[submodule "vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
......
......@@ -6,6 +6,14 @@
Changelog
=========
3.0.8 - 2021-03-17
==================
Changed
-------
- hdl: svec-base updated to 2.0, for the FD there are no incompatible changes
- sw,hdl: compact memory map [we know, do not ask]
3.0.7 - 2021-02-24
==================
......
Subproject commit 7afd1ca9d7413b360f96ebacf6d976f13cadebe1
Subproject commit 577b31c8b1dc530aa145a8a49ab10dff7e9483b1
......@@ -303,7 +303,7 @@ architecture arch of svec_top is
constant c_WB_SLAVE_FD1 : integer := 2;
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
constant c_METADATA_ADDR : t_wishbone_address := x"0000_4000";
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
......@@ -414,7 +414,7 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0002", -- SVEC + 2xFineDelay
g_VERSION => x"0300_0004",
g_VERSION => x"0300_0008",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => sourceid_svec_fine_delay_top_pkg.sourceid)
port map (
......
......@@ -10,10 +10,10 @@
#include <linux/fmc.h>
enum fd_svec_dev_offsets {
FD_SVEC_FDT1_MEM_START = 0x0000E000,
FD_SVEC_FDT1_MEM_END = 0x0000E1FF,
FD_SVEC_FDT2_MEM_START = 0x0001E000,
FD_SVEC_FDT2_MEM_END = 0x0001E1FF,
FD_SVEC_FDT1_MEM_START = 0x0000C000,
FD_SVEC_FDT1_MEM_END = 0x0000C1FF,
FD_SVEC_FDT2_MEM_START = 0x0001C000,
FD_SVEC_FDT2_MEM_END = 0x0001C1FF,
};
/* MFD devices */
......
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