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FMC DEL 1ns 4cha
Commits
3b69f101
Commit
3b69f101
authored
Dec 02, 2020
by
Tomasz Wlostowski
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hdl: keep IODELAY adjustments in clk_ref clock domain, increase taps register length to 8 bits
parent
ecd0bb00
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4 changed files
with
60 additions
and
29 deletions
+60
-29
fd_main_wbgen2_pkg.vhd
hdl/rtl/fd_main_wbgen2_pkg.vhd
+3
-3
fd_main_wishbone_slave.vhd
hdl/rtl/fd_main_wishbone_slave.vhd
+3
-5
fd_main_wishbone_slave.wb
hdl/rtl/fd_main_wishbone_slave.wb
+1
-1
fine_delay_core.vhd
hdl/rtl/fine_delay_core.vhd
+53
-20
No files found.
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @
3b69f101
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : T
ue Oct 22 18:06:55 2019
-- Created : T
hu May 28 16:19:19 2020
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...
@@ -57,7 +57,7 @@ package fd_main_wbgen2_pkg is
...
@@ -57,7 +57,7 @@ package fd_main_wbgen2_pkg is
tder1_vcxo_freq_i
:
std_logic_vector
(
31
downto
0
);
tder1_vcxo_freq_i
:
std_logic_vector
(
31
downto
0
);
tsbr_debug_i
:
std_logic_vector
(
31
downto
0
);
tsbr_debug_i
:
std_logic_vector
(
31
downto
0
);
fmc_slot_id_slot_id_i
:
std_logic_vector
(
3
downto
0
);
fmc_slot_id_slot_id_i
:
std_logic_vector
(
3
downto
0
);
iodelay_adj_n_taps_i
:
std_logic_vector
(
5
downto
0
);
iodelay_adj_n_taps_i
:
std_logic_vector
(
7
downto
0
);
end
record
;
end
record
;
constant
c_fd_main_in_registers_init_value
:
t_fd_main_in_registers
:
=
(
constant
c_fd_main_in_registers_init_value
:
t_fd_main_in_registers
:
=
(
...
@@ -157,7 +157,7 @@ package fd_main_wbgen2_pkg is
...
@@ -157,7 +157,7 @@ package fd_main_wbgen2_pkg is
i2cr_sda_out_o
:
std_logic
;
i2cr_sda_out_o
:
std_logic
;
tder2_pelt_drive_o
:
std_logic_vector
(
31
downto
0
);
tder2_pelt_drive_o
:
std_logic_vector
(
31
downto
0
);
tsbr_advance_adv_o
:
std_logic
;
tsbr_advance_adv_o
:
std_logic
;
iodelay_adj_n_taps_o
:
std_logic_vector
(
5
downto
0
);
iodelay_adj_n_taps_o
:
std_logic_vector
(
7
downto
0
);
iodelay_adj_n_taps_load_o
:
std_logic
;
iodelay_adj_n_taps_load_o
:
std_logic
;
end
record
;
end
record
;
...
...
hdl/rtl/fd_main_wishbone_slave.vhd
View file @
3b69f101
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : T
ue Oct 22 18:06:55 2019
-- Created : T
hu May 28 16:19:19 2020
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...
@@ -1219,9 +1219,7 @@ begin
...
@@ -1219,9 +1219,7 @@ begin
if
(
wb_we_i
=
'1'
)
then
if
(
wb_we_i
=
'1'
)
then
regs_o
.
iodelay_adj_n_taps_load_o
<=
'1'
;
regs_o
.
iodelay_adj_n_taps_load_o
<=
'1'
;
end
if
;
end
if
;
rddata_reg
(
5
downto
0
)
<=
regs_i
.
iodelay_adj_n_taps_i
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
iodelay_adj_n_taps_i
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
...
@@ -2114,7 +2112,7 @@ end process;
...
@@ -2114,7 +2112,7 @@ end process;
-- Slot ID
-- Slot ID
-- Number of delay line taps.
-- Number of delay line taps.
regs_o
.
iodelay_adj_n_taps_o
<=
wrdata_reg
(
5
downto
0
);
regs_o
.
iodelay_adj_n_taps_o
<=
wrdata_reg
(
7
downto
0
);
-- extra code for reg/fifo/mem: Interrupt disable register
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int
(
2
downto
0
)
<=
wrdata_reg
(
2
downto
0
);
eic_idr_int
(
2
downto
0
)
<=
wrdata_reg
(
2
downto
0
);
-- extra code for reg/fifo/mem: Interrupt enable register
-- extra code for reg/fifo/mem: Interrupt enable register
...
...
hdl/rtl/fd_main_wishbone_slave.wb
View file @
3b69f101
...
@@ -1065,7 +1065,7 @@ peripheral {
...
@@ -1065,7 +1065,7 @@ peripheral {
name = "Number of delay line taps.";
name = "Number of delay line taps.";
prefix = "N_TAPS";
prefix = "N_TAPS";
type = SLV;
type = SLV;
size =
6
;
size =
8
;
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
load = LOAD_EXT;
...
...
hdl/rtl/fine_delay_core.vhd
View file @
3b69f101
...
@@ -17,7 +17,7 @@
...
@@ -17,7 +17,7 @@
--
--
-- This source file is free software; you can redistribute it
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software F
s
oundation;
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- later version.
--
--
...
@@ -215,6 +215,7 @@ entity fine_delay_core is
...
@@ -215,6 +215,7 @@ entity fine_delay_core is
idelay_cal_o
:
out
std_logic
;
idelay_cal_o
:
out
std_logic
;
idelay_ce_o
:
out
std_logic
;
idelay_ce_o
:
out
std_logic
;
idelay_rst_o
:
out
std_logic
;
idelay_rst_o
:
out
std_logic
;
idelay_busy_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
...
@@ -307,7 +308,7 @@ architecture rtl of fine_delay_core is
...
@@ -307,7 +308,7 @@ architecture rtl of fine_delay_core is
signal
rst_n_sys
,
rst_n_ref
:
std_logic
;
signal
rst_n_sys
,
rst_n_ref
:
std_logic
;
signal
tsbcr_read_ack
,
fid_read_ack
:
std_logic
;
signal
tsbcr_read_ack
,
fid_read_ack
:
std_logic
;
signal
irq_rbuf
,
irq_s
pll
,
irq_s
ync
:
std_logic
;
signal
irq_rbuf
,
irq_sync
:
std_logic
;
type
t_delay_channel
is
record
type
t_delay_channel
is
record
idle
:
std_logic
;
idle
:
std_logic
;
...
@@ -367,12 +368,15 @@ architecture rtl of fine_delay_core is
...
@@ -367,12 +368,15 @@ architecture rtl of fine_delay_core is
signal
dmtd_tag_stb
,
dbg_tag_in
,
dbg_tag_out
:
std_logic
;
signal
dmtd_tag_stb
,
dbg_tag_in
,
dbg_tag_out
:
std_logic
;
signal
iodelay_ntaps
:
std_logic_vector
(
5
downto
0
);
signal
iodelay_ntaps
:
std_logic_vector
(
7
downto
0
);
signal
iodelay_cnt
:
unsigned
(
5
downto
0
);
signal
iodelay_cnt
:
unsigned
(
7
downto
0
);
signal
iodelay_div
:
unsigned
(
4
downto
0
);
signal
iodelay_div
:
unsigned
(
6
downto
0
);
signal
iodelay_tick
:
std_logic
;
signal
iodelay_tick
:
std_logic
;
signal
iodelay_cal_done
:
std_logic
;
signal
iodelay_cal_done
:
std_logic
;
signal
iodelay_cal_in_progress
:
std_logic
;
signal
iodelay_n_taps_load_refclk_p
:
std_logic
;
signal
iodelay_busy_synced
:
std_logic
;
signal
iodelay_latch_reset
:
std_logic
;
begin
-- rtl
begin
-- rtl
U_WB_Adapter
:
wb_slave_adapter
U_WB_Adapter
:
wb_slave_adapter
...
@@ -858,10 +862,42 @@ begin -- rtl
...
@@ -858,10 +862,42 @@ begin -- rtl
dbg_o
<=
(
others
=>
'0'
);
dbg_o
<=
(
others
=>
'0'
);
end
generate
gen_without_dbg_out
;
end
generate
gen_without_dbg_out
;
p_handle_iodelay
:
process
(
clk_sys_i
)
U_Sync_Busy
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_0_i
,
rst_n_i
=>
rst_n_ref
,
data_i
=>
idelay_busy_i
,
synced_o
=>
iodelay_busy_synced
);
U_Sync_taps_load
:
gc_pulse_synchronizer2
port
map
(
clk_in_i
=>
clk_sys_i
,
rst_in_n_i
=>
rst_n_sys
,
clk_out_i
=>
clk_ref_0_i
,
rst_out_n_i
=>
rst_n_ref
,
d_ready_o
=>
open
,
d_ack_p_o
=>
open
,
d_p_i
=>
regs_fromwb
.
iodelay_adj_n_taps_load_o
,
q_p_o
=>
iodelay_n_taps_load_refclk_p
);
p_latch_ntaps
:
process
(
clk_sys_i
)
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_sys
=
'0'
then
if
regs_fromwb
.
iodelay_adj_n_taps_load_o
=
'1'
then
iodelay_ntaps
<=
regs_fromwb
.
iodelay_adj_n_taps_o
;
end
if
;
end
if
;
end
process
;
p_handle_iodelay
:
process
(
clk_ref_0_i
)
begin
if
rising_edge
(
clk_ref_0_i
)
then
if
rst_n_ref
=
'0'
then
idelay_cal_o
<=
'0'
;
idelay_cal_o
<=
'0'
;
idelay_inc_o
<=
'1'
;
idelay_inc_o
<=
'1'
;
idelay_rst_o
<=
'0'
;
idelay_rst_o
<=
'0'
;
...
@@ -874,35 +910,32 @@ begin -- rtl
...
@@ -874,35 +910,32 @@ begin -- rtl
if
iodelay_cal_done
=
'0'
then
if
iodelay_cal_done
=
'0'
then
idelay_cal_o
<=
'1'
;
idelay_cal_o
<=
'1'
;
iodelay_cnt
<=
iodelay_cnt
+
1
;
if
iodelay_cnt
=
15
then
iodelay_cnt
<=
(
others
=>
'0'
);
iodelay_cal_done
<=
'1'
;
iodelay_cal_done
<=
'1'
;
end
if
;
else
else
idelay_cal_o
<=
'0'
;
idelay_cal_o
<=
'0'
;
end
if
;
end
if
;
iodelay_div
<=
iodelay_div
+
1
;
iodelay_div
<=
iodelay_div
+
1
;
if
iodelay_div
=
0
then
if
iodelay_div
=
0
then
iodelay_tick
<=
'1'
;
iodelay_tick
<=
'1'
;
else
else
iodelay_tick
<=
'0'
;
iodelay_tick
<=
'0'
;
end
if
;
end
if
;
if
regs_fromwb
.
iodelay_adj_n_taps_load_o
=
'1'
then
if
iodelay_n_taps_load_refclk_p
=
'1'
then
iodelay_cnt
<=
unsigned
(
regs_fromwb
.
iodelay_adj_n_taps_o
);
iodelay_cnt
<=
unsigned
(
iodelay_ntaps
);
idelay_rst_o
<=
'1'
;
iodelay_latch_reset
<=
'1'
;
iodelay_ntaps
<=
regs_fromwb
.
iodelay_adj_n_taps_o
;
else
idelay_rst_o
<=
'0'
;
end
if
;
end
if
;
if
iodelay_cal_done
=
'1'
and
iodelay_tick
=
'1'
and
iodelay_cnt
/=
0
then
if
iodelay_cal_done
=
'1'
and
iodelay_tick
=
'1'
and
iodelay_cnt
/=
0
then
idelay_ce_o
<=
'1'
;
idelay_rst_o
<=
iodelay_latch_reset
;
idelay_ce_o
<=
not
iodelay_latch_reset
;
iodelay_latch_reset
<=
'0'
;
iodelay_cnt
<=
iodelay_cnt
-
1
;
iodelay_cnt
<=
iodelay_cnt
-
1
;
else
else
idelay_ce_o
<=
'0'
;
idelay_ce_o
<=
'0'
;
idelay_rst_o
<=
'0'
;
end
if
;
end
if
;
...
@@ -910,8 +943,8 @@ begin -- rtl
...
@@ -910,8 +943,8 @@ begin -- rtl
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
end
process
;
regs_towb_local
.
iodelay_adj_n_taps_i
<=
iodelay_ntaps
;
regs_towb_local
.
iodelay_adj_n_taps_i
<=
iodelay_ntaps
;
...
...
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