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FMC DEL 1ns 4cha
Commits
36d42326
Commit
36d42326
authored
Apr 25, 2013
by
Tomasz Wlostowski
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hdl/top/spec: SPEC top level with VIC vector table preinitialization & synthesis descriptor
parent
258f1b82
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4 changed files
with
94 additions
and
33 deletions
+94
-33
Manifest.py
hdl/top/spec/wr/Manifest.py
+1
-1
spec_top.ucf
hdl/top/spec/wr/spec_top.ucf
+9
-0
spec_top.vhd
hdl/top/spec/wr/spec_top.vhd
+27
-32
synthesis_descriptor.vhd
hdl/top/spec/wr/synthesis_descriptor.vhd
+57
-0
No files found.
hdl/top/spec/wr/Manifest.py
View file @
36d42326
files
=
[
"spec_top.vhd"
,
"spec_top.ucf"
,
"spec_serial_dac.vhd"
,
"spec_serial_dac_arb.vhd"
,
"spec_reset_gen.vhd"
]
files
=
[
"s
ynthesis_descriptor.vhd"
,
"s
pec_top.vhd"
,
"spec_top.ucf"
,
"spec_serial_dac.vhd"
,
"spec_serial_dac_arb.vhd"
,
"spec_reset_gen.vhd"
]
fetchto
=
"../../../ip_cores"
fetchto
=
"../../../ip_cores"
...
...
hdl/top/spec/wr/spec_top.ucf
View file @
36d42326
...
@@ -171,6 +171,15 @@ NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
...
@@ -171,6 +171,15 @@ NET "fmc_scl_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" LOC = F8 ;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
NET "fmc_sda_b" IOSTANDARD =LVCMOS25;
#net "led_n_o[0]" loc=c20;
#net "led_n_o[0]" IOSTANDARD=LVCMOS18;
#net "led_n_o[1]" loc=F18;
#net "led_n_o[1]" IOSTANDARD=LVCMOS18;
#net "led_n_o[2]" loc=f20;
#net "led_n_o[2]" IOSTANDARD=LVCMOS18;
#net "led_n_o[3]" loc=G19;
#net "led_n_o[3]" IOSTANDARD=LVCMOS18;
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
...
...
hdl/top/spec/wr/spec_top.vhd
View file @
36d42326
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Company : CERN
-- Created : 2011-08-24
-- Created : 2011-08-24
-- Last update: 2013-0
2-22
-- Last update: 2013-0
4-17
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -50,6 +50,8 @@ use work.fine_delay_pkg.all;
...
@@ -50,6 +50,8 @@ use work.fine_delay_pkg.all;
use
work
.
etherbone_pkg
.
all
;
use
work
.
etherbone_pkg
.
all
;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
synthesis_descriptor
.
all
;
library
UNISIM
;
library
UNISIM
;
use
UNISIM
.
vcomponents
.
all
;
use
UNISIM
.
vcomponents
.
all
;
...
@@ -264,35 +266,26 @@ architecture rtl of spec_top is
...
@@ -264,35 +266,26 @@ architecture rtl of spec_top is
constant
c_MASTER_GENNUM
:
integer
:
=
0
;
constant
c_MASTER_GENNUM
:
integer
:
=
0
;
constant
c_MASTER_ETHERBONE
:
integer
:
=
1
;
constant
c_MASTER_ETHERBONE
:
integer
:
=
1
;
constant
c_SLAVE_FD
:
integer
:
=
0
;
constant
c_SLAVE_FD
:
integer
:
=
0
;
constant
c_SLAVE_WRCORE
:
integer
:
=
1
;
constant
c_SLAVE_WRCORE
:
integer
:
=
1
;
constant
c_SLAVE_VIC
:
integer
:
=
2
;
constant
c_SLAVE_VIC
:
integer
:
=
2
;
constant
c_DESC_SYNTHESIS
:
integer
:
=
3
;
constant
c_DESC_REPO_URL
:
integer
:
=
4
;
constant
c_WRCORE_BRIDGE_SDB
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"0003ffff"
,
x"00030000"
);
constant
c_WRCORE_BRIDGE_SDB
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"0003ffff"
,
x"00030000"
);
constant
c_xwb_vic_sdb
:
t_sdb_device
:
=
(
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_MASTERS
+
1
downto
0
)
:
=
abi_class
=>
x"0000"
,
-- undocumented device
(
c_SLAVE_WRCORE
=>
f_sdb_embed_bridge
(
c_WRCORE_BRIDGE_SDB
,
x"000c0000"
),
abi_ver_major
=>
x"01"
,
c_SLAVE_FD
=>
f_sdb_embed_device
(
c_FD_SDB_DEVICE
,
x"00080000"
),
abi_ver_minor
=>
x"01"
,
c_SLAVE_VIC
=>
f_sdb_embed_device
(
c_xwb_vic_sdb
,
x"00090000"
),
wbd_endian
=>
c_sdb_endian_big
,
c_DESC_SYNTHESIS
=>
f_sdb_embed_synthesis
(
c_sdb_synthesis_info
),
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
c_DESC_REPO_URL
=>
f_sdb_embed_repo_url
(
c_sdb_repo_url
));
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000013"
,
version
=>
x"00000001"
,
date
=>
x"20120113"
,
name
=>
"WB-VIC-Int.Control "
)));
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_MASTERS
-1
downto
0
)
:
=
(
c_SLAVE_WRCORE
=>
f_sdb_embed_bridge
(
c_WRCORE_BRIDGE_SDB
,
x"000c0000"
),
c_SLAVE_FD
=>
f_sdb_embed_device
(
c_FD_SDB_DEVICE
,
x"00080000"
),
c_SLAVE_VIC
=>
f_sdb_embed_device
(
c_xwb_vic_sdb
,
x"00090000"
));
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_VIC_VECTOR_TABLE
:
t_wishbone_address_array
(
0
to
0
)
:
=
(
0
=>
x"00080000"
);
signal
pllout_clk_sys
:
std_logic
;
signal
pllout_clk_sys
:
std_logic
;
signal
pllout_clk_dmtd
:
std_logic
;
signal
pllout_clk_dmtd
:
std_logic
;
signal
pllout_clk_fb_pllref
:
std_logic
;
signal
pllout_clk_fb_pllref
:
std_logic
;
...
@@ -567,7 +560,7 @@ begin
...
@@ -567,7 +560,7 @@ begin
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top level interconnect and interrupt controller
-- Top level interconnect and interrupt controller
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
U_Intercon
:
xwb_sdb_crossbar
U_Intercon
:
xwb_sdb_crossbar
generic
map
(
generic
map
(
g_num_masters
=>
c_NUM_WB_SLAVES
,
g_num_masters
=>
c_NUM_WB_SLAVES
,
...
@@ -588,7 +581,8 @@ begin
...
@@ -588,7 +581,8 @@ begin
generic
map
(
generic
map
(
g_interface_mode
=>
PIPELINED
,
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_address_granularity
=>
BYTE
,
g_num_interrupts
=>
1
)
g_num_interrupts
=>
1
,
g_init_vectors
=>
c_VIC_VECTOR_TABLE
)
port
map
(
port
map
(
clk_sys_i
=>
clk_sys
,
clk_sys_i
=>
clk_sys
,
rst_n_i
=>
local_reset_n
,
rst_n_i
=>
local_reset_n
,
...
@@ -626,10 +620,11 @@ begin
...
@@ -626,10 +620,11 @@ begin
g_with_external_clock_input
=>
false
,
g_with_external_clock_input
=>
false
,
g_aux_clks
=>
1
,
g_aux_clks
=>
1
,
g_ep_rxbuf_size
=>
1024
,
g_ep_rxbuf_size
=>
1024
,
g_dpram_initf
=>
"
wrc.ram
"
,
g_dpram_initf
=>
"
none
"
,
g_dpram_size
=>
90112
/
4
,
g_dpram_size
=>
90112
/
4
,
g_interface_mode
=>
PIPELINED
,
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
)
g_address_granularity
=>
BYTE
,
g_softpll_enable_debugger
=>
false
)
port
map
(
port
map
(
clk_sys_i
=>
clk_sys
,
clk_sys_i
=>
clk_sys
,
clk_dmtd_i
=>
clk_dmtd
,
clk_dmtd_i
=>
clk_dmtd
,
...
@@ -655,7 +650,7 @@ begin
...
@@ -655,7 +650,7 @@ begin
phy_rst_o
=>
phy_rst
,
phy_rst_o
=>
phy_rst
,
phy_loopen_o
=>
phy_loopen
,
phy_loopen_o
=>
phy_loopen
,
led_act_o
=>
LED_RED
,
led_act_o
=>
LED_RED
,
led_link_o
=>
LED_GREEN
,
led_link_o
=>
LED_GREEN
,
scl_o
=>
wrc_scl_out
,
scl_o
=>
wrc_scl_out
,
...
@@ -687,9 +682,9 @@ begin
...
@@ -687,9 +682,9 @@ begin
tm_link_up_o
=>
tm_link_up
,
tm_link_up_o
=>
tm_link_up
,
tm_dac_value_o
=>
tm_dac_value
,
tm_dac_value_o
=>
tm_dac_value
,
tm_dac_wr_o
=>
tm_dac_wr
,
tm_dac_wr_o
(
0
)
=>
tm_dac_wr
,
tm_clk_aux_lock_en_i
=>
tm_clk_aux_lock_en
,
tm_clk_aux_lock_en_i
(
0
)
=>
tm_clk_aux_lock_en
,
tm_clk_aux_locked_o
=>
tm_clk_aux_locked
,
tm_clk_aux_locked_o
(
0
)
=>
tm_clk_aux_locked
,
tm_time_valid_o
=>
tm_time_valid
,
tm_time_valid_o
=>
tm_time_valid
,
tm_tai_o
=>
tm_utc
,
tm_tai_o
=>
tm_utc
,
tm_cycles_o
=>
tm_cycles
,
tm_cycles_o
=>
tm_cycles
,
...
...
hdl/top/spec/wr/synthesis_descriptor.vhd
0 → 100644
View file @
36d42326
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SPEC (Simple PCIe FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
synthesis_descriptor
is
constant
c_sdb_synthesis_info
:
t_sdb_synthesis
:
=
(
syn_module_name
=>
"fine-delay-spec "
,
syn_commit_id
=>
"00000000000000000000000000000000"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"00000133"
,
syn_date
=>
x"00000000"
,
syn_username
=>
"twlostow "
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
(
repo_url
=>
"git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git "
);
end
package
synthesis_descriptor
;
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