platform: uploaded platform-dependend code

354391a9 · Tomasz Wlostowski · 9aef0922 · 354391a9 · 354391a9 · 354391a9
Commit 354391a9 authored Feb 26, 2012 by Tomasz Wlostowski
5 changed files
--- a/hdl/platform/Manifest.py
+++ b/hdl/platform/Manifest.py
+files =["chipscope_icon.ngc",  "chipscope_ila.ngc", "fd_ddr_driver.vhd", "fd_ddr_pll.vhd" ]
--- a/hdl/platform/chipscope_icon.ngc
+++ b/hdl/platform/chipscope_icon.ngc
--- a/hdl/platform/chipscope_ila.ngc
+++ b/hdl/platform/chipscope_ila.ngc
--- a/hdl/platform/fd_ddr_driver.vhd
+++ b/hdl/platform/fd_ddr_driver.vhd
+-------------------------------------------------------------------------------
+-- Title      : Xilinx DDR driver
+-- Project    : Fine Delay FMC (fmc-delay-1ns-4cha)
+-------------------------------------------------------------------------------
+-- File       : fd_ddr_driver.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Created    : 2011-08-24
+-- Last update: 2012-02-24
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Wrapper for Xilinx ODDR2 primitive. Configured to latch input
+-- data at the rising edge of clk0_i.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2012-02-10  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity fd_ddr_driver is
+  
+  port (
+    clk0_i : in  std_logic;
+    clk1_i : in  std_logic;
+    d0_i   : in  std_logic;
+    d1_i   : in  std_logic;
+    q_o    : out std_logic);
+
+end fd_ddr_driver;
+
+architecture wrapper of fd_ddr_driver is
+
+  component ODDR2
+    generic (
+      DDR_ALIGNMENT : string := "C0";
+      SRTYPE : string := "ASYNC");
+    port (
+      Q  : out std_ulogic;
+      CE : in  std_ulogic := '1';
+      R  : in  std_ulogic := '0';
+      S  : in  std_ulogic := '0';
+      C0 : in  std_ulogic;
+      C1 : in  std_ulogic;
+      D0 : in  std_ulogic;
+      D1 : in  std_ulogic);
+  end component;
+  
+begin  -- wrapper
+
+  U_Wrapped_ODDR2 : ODDR2
+    port map (
+      Q  => q_o,
+      C0 => clk0_i,
+      C1 => clk1_i,
+      D0 => d0_i,
+      D1 => d1_i);
+
+end wrapper;
--- a/hdl/platform/fd_ddr_pll.vhd
+++ b/hdl/platform/fd_ddr_pll.vhd
+-- file: clk_wiz_v3_2.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___125.000______0.000______50.0______161.194____212.907
+-- CLK_OUT2___125.000____180.000______50.0______161.194____212.907
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary_________125.000____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity fd_ddr_pll is
+  port
+    (
+      RST : in std_logic;
+      LOCKED : out std_logic;
+      -- Clock in ports
+      CLK_IN1_P : in  std_logic;
+      CLK_IN1_N : in  std_logic;
+      -- Clock out ports
+      CLK_OUT1  : out std_logic;
+      CLK_OUT2  : out std_logic
+      );
+end fd_ddr_pll;
+
+architecture xilinx of fd_ddr_pll is
+  attribute CORE_GENERATION_INFO           : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v3_2,clk_wiz_v3_2,{component_name=clk_wiz_v3_2,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=8.000,clkin2_period=8.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1                            : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout                          : std_logic;
+  signal clkfbout_buf                      : std_logic;
+  signal clkout0                           : std_logic;
+  signal clkout1                           : std_logic;
+  signal clkout2_unused                    : std_logic;
+  signal clkout3_unused                    : std_logic;
+  signal clkout4_unused                    : std_logic;
+  signal clkout5_unused                    : std_logic;
+  -- Unused status signals
+  signal locked_unused                     : std_logic;
+
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : IBUFGDS
+    generic map
+    (
+      DIFF_TERM    => true,             -- Differential Termination
+      IBUF_LOW_PWR => false,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+      IOSTANDARD   => "LVDS_25")
+    port map
+    (O  => clkin1,
+     I  => CLK_IN1_P,
+     IB => CLK_IN1_N);
+
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the PLL primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  pll_base_inst : PLL_BASE
+    generic map
+    (BANDWIDTH          => "OPTIMIZED",
+     CLK_FEEDBACK       => "CLKFBOUT",
+     COMPENSATION       => "SYSTEM_SYNCHRONOUS",
+     DIVCLK_DIVIDE      => 1,
+     CLKFBOUT_MULT      => 4,
+     CLKFBOUT_PHASE     => 0.000,
+     CLKOUT0_DIVIDE     => 4,
+     CLKOUT0_PHASE      => 0.000,
+     CLKOUT0_DUTY_CYCLE => 0.500,
+     CLKOUT1_DIVIDE     => 4,
+     CLKOUT1_PHASE      => 180.000,
+     CLKOUT1_DUTY_CYCLE => 0.500,
+     CLKIN_PERIOD       => 8.000,
+     REF_JITTER         => 0.010)
+    port map
+    -- Output clocks
+    (CLKFBOUT => clkfbout,
+     CLKOUT0  => clkout0,
+     CLKOUT1  => clkout1,
+     CLKOUT2  => clkout2_unused,
+     CLKOUT3  => clkout3_unused,
+     CLKOUT4  => clkout4_unused,
+     CLKOUT5  => clkout5_unused,
+     LOCKED   => LOCKED,
+     RST      => RST,
+     -- Input clock control
+     CLKFBIN  => clkfbout_buf,
+     CLKIN    => clkin1);
+
+  -- Output buffering
+  -------------------------------------
+  clkf_buf : BUFG
+    port map
+    (O => clkfbout_buf,
+     I => clkfbout);
+
+
+  clkout1_buf : BUFG
+    port map
+    (O => CLK_OUT1,
+     I => clkout0);
+
+
+
+  clkout2_buf : BUFG
+    port map
+    (O => CLK_OUT2,
+     I => clkout1);
+
+end xilinx;