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FMC DEL 1ns 4cha
Commit 351c88a7 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: correct generation of source ids

parent ca5f16b7
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Showing with 518 additions and 452 deletions
hdl/syn/spec/Manifest.py
View file @ 351c88a7
......@@ -17,7 +17,7 @@ spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [ "buildinfo_pkg.vhd", "sourceid_spec_fine_delay_top_pkg.vhd" ]
modules = {
"local" : [ "../../top/spec" ]
......@@ -29,4 +29,14 @@ try:
except:
pass
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'spec_fine_delay_top'})
except Exception as e:
print("Error: cannot generate source id file")
raise
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/svec/Manifest.py
View file @ 351c88a7
......@@ -15,7 +15,7 @@ if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
"buildinfo_pkg.vhd", "sourceid_svec_fine_delay_top_pkg.vhd"
]
modules = {
......@@ -30,6 +30,16 @@ try:
except:
pass
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'svec_fine_delay_top'})
except Exception as e:
print("Error: cannot generate source id file")
raise
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
......
hdl/syn/svec/svec_fine_delay.xise
View file @ 351c88a7
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hdl/top/spec/spec_fine_delay_top.vhd
View file @ 351c88a7
......@@ -34,6 +34,8 @@ use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all;
use work.sourceid_spec_fine_delay_top_pkg;
library unisim;
use unisim.vcomponents.all;
......@@ -305,9 +307,9 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0001", -- SPEC + 1xFine Delay
g_VERSION => x"0100_0000",
g_VERSION => x"0003_0004",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
g_COMMIT_ID => sourceid_spec_fine_delay_top_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......
hdl/top/svec/svec_fine_delay_top.vhd
View file @ 351c88a7
......@@ -39,6 +39,7 @@ use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all;
use work.sourceid_svec_fine_delay_top_pkg;
library unisim;
use unisim.vcomponents.all;
......@@ -413,9 +414,9 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574f_0002", -- SVEC + 2xFineDelay
g_VERSION => x"0100_0000",
g_VERSION => x"0003_0004",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
g_COMMIT_ID => sourceid_svec_fine_delay_top_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......
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