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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
2da9c9db
Commit
2da9c9db
authored
Apr 11, 2012
by
Tomasz Wlostowski
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software/include: register definitions synced up with the latest HDL
parent
94dbf96b
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2 changed files
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23 additions
and
12 deletions
+23
-12
fd_channel_regs.h
software/include/fd_channel_regs.h
+1
-1
fd_main_regs.h
software/include/fd_main_regs.h
+22
-11
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software/include/fd_channel_regs.h
View file @
2da9c9db
...
...
@@ -3,7 +3,7 @@
* File : fd_channel_regs.h
* Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
* Created : Wed
Feb 29 12:04:0
2 2012
* Created : Wed
Apr 11 11:05:2
2 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
...
...
software/include/fd_main_regs.h
View file @
2da9c9db
...
...
@@ -3,7 +3,7 @@
* File : fd_main_regs.h
* Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
* Created : Wed
Feb 29 12:04:0
2 2012
* Created : Wed
Apr 11 11:05:2
2 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
...
...
@@ -64,6 +64,9 @@
/* definitions for field: PLL Locked in reg: Global Control Register */
#define FD_GCR_DDR_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Mezzanice Present in reg: Global Control Register */
#define FD_GCR_FMC_PRESENT WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Timing Control Register */
/* definitions for field: DMTD Clock Status in reg: Timing Control Register */
...
...
@@ -325,17 +328,21 @@
/* definitions for field: SDA Line in in reg: I2C bitbanged IO register */
#define FD_I2CR_SDA_IN WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Debug in in reg: I2C bitbanged IO register */
#define FD_I2CR_DBG_MASK WBGEN2_GEN_MASK(4, 4)
#define FD_I2CR_DBG_SHIFT 4
#define FD_I2CR_DBG_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define FD_I2CR_DBG_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for register: Test/Debug register 1 */
/* definitions for field: VCXO Frequency in reg: Test/Debug register 1 */
#define FD_TDER1_VCXO_FREQ_MASK WBGEN2_GEN_MASK(0, 32)
#define FD_TDER1_VCXO_FREQ_SHIFT 0
#define FD_TDER1_VCXO_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define FD_TDER1_VCXO_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Test/Debug register 1 */
/* definitions for field:
Debug out in reg: I2C bitbanged IO register
*/
#define FD_
I2CR_DBGOUT_MASK WBGEN2_GEN_MASK(8, 1
2)
#define FD_
I2CR_DBGOUT_SHIFT 8
#define FD_
I2CR_DBGOUT_W(value) WBGEN2_GEN_WRITE(value, 8, 1
2)
#define FD_
I2CR_DBGOUT_R(reg) WBGEN2_GEN_READ(reg, 8, 1
2)
/* definitions for field:
Peltier PWM drive in reg: Test/Debug register 1
*/
#define FD_
TDER2_PELT_DRIVE_MASK WBGEN2_GEN_MASK(0, 3
2)
#define FD_
TDER2_PELT_DRIVE_SHIFT 0
#define FD_
TDER2_PELT_DRIVE_W(value) WBGEN2_GEN_WRITE(value, 0, 3
2)
#define FD_
TDER2_PELT_DRIVE_R(reg) WBGEN2_GEN_READ(reg, 0, 3
2)
/* definitions for register: Interrupt disable register */
...
...
@@ -434,6 +441,10 @@
#define FD_REG_TSBR_FID 0x00000064
/* [0x68]: REG I2C bitbanged IO register */
#define FD_REG_I2CR 0x00000068
/* [0x6c]: REG Test/Debug register 1 */
#define FD_REG_TDER1 0x0000006c
/* [0x70]: REG Test/Debug register 1 */
#define FD_REG_TDER2 0x00000070
/* [0x80]: REG Interrupt disable register */
#define FD_REG_EIC_IDR 0x00000080
/* [0x84]: REG Interrupt enable register */
...
...
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