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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
2d9c8d9c
Commit
2d9c8d9c
authored
May 02, 2012
by
Tomasz Wlostowski
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Plain Diff
software/lib: WR mode added
parent
a298a3e9
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3 changed files
with
66 additions
and
49 deletions
+66
-49
fdelay_lib.c
software/lib/fdelay_lib.c
+18
-43
fdelay_test.c
software/lib/fdelay_test.c
+45
-3
spec_common.c
software/lib/spec_common.c
+3
-3
No files found.
software/lib/fdelay_lib.c
View file @
2d9c8d9c
...
...
@@ -986,6 +986,9 @@ int fdelay_init(fdelay_device_t *dev)
/* Switch the ACAM to be driven by the delay core instead of the host */
fd_writel
(
0
,
FD_REG_GCR
);
/* Disable external synchronization (i.e. WR) */
fd_writel
(
0
,
FD_REG_TCR
);
/* Clear and disable the timestamp readout buffer */
fd_writel
(
FD_TSBCR_PURGE
|
FD_TSBCR_RST_SEQ
,
FD_REG_TSBCR
);
...
...
@@ -1102,8 +1105,11 @@ int64_t fdelay_to_picos(const fdelay_time_t t)
static
int
poll_rbuf
(
fdelay_device_t
*
dev
)
{
fd_decl_private
(
dev
)
uint32_t
tsbcr
=
fd_readl
(
FD_REG_TSBCR
);
// fprintf(stderr,"Count %d empty %d\n", FD_TSBCR_COUNT_R(tsbcr), tsbcr & FD_TSBCR_EMPTY ? 1 : 0);
if
((
fd_readl
(
FD_REG_TSBCR
)
&
FD_TSBCR_EMPTY
)
==
0
)
if
((
tsbcr
&
FD_TSBCR_EMPTY
)
==
0
)
return
1
;
return
0
;
}
...
...
@@ -1308,8 +1314,6 @@ int fdelay_get_time(fdelay_device_t *dev, fdelay_time_t *t)
return
0
;
}
#if 0
/* To be rewritten to use interrupts and new WR FSM (see TCR register description).
Use the API provided in fdelay_lib.h */
...
...
@@ -1320,59 +1324,30 @@ int fdelay_configure_sync(fdelay_device_t *dev, int mode)
if
(
mode
==
FDELAY_SYNC_LOCAL
)
{
fd_writel
(
0
,
FD_REG_GCR
);
// fd_writel(FD_GCR_CSYNC_INT, FD_REG_G
CR);
fd_writel
(
0
,
FD_REG_T
CR
);
hw
->
wr_enabled
=
0
;
}
else
{
fd_writel
(
0
,
FD_REG_GCR
);
fd_writel
(
FD_TCR_WR_ENABLE
,
FD_REG_TCR
);
hw
->
wr_enabled
=
1
;
hw->wr_state = FDELAY_WR_OFFLINE;
}
}
int fdelay_
get_sync_status
(fdelay_device_t *dev)
int
fdelay_
check_sync
(
fdelay_device_t
*
dev
)
{
fd_decl_private
(
dev
)
if(!hw->wr_enabled) return FDELAY_FREE_RUNNING;
switch(hw->wr_state)
{
case FDELAY_WR_OFFLINE:
if(fd_readl(FD_REG_GCR) & FD_GCR_WR_READY)
{
dbg("-> WR Core synced\n");
hw->wr_state = FDELAY_WR_READY;
}
break;
case FDELAY_WR_READY:
fd_writel(FD_GCR_WR_LOCK_EN, FD_REG_GCR);
hw->wr_state = FDELAY_WR_SYNCING;
break;
fprintf
(
stderr
,
"TCR %x
\n
"
,
fd_readl
(
FD_REG_TCR
)
&
FD_TCR_WR_LOCKED
);
case FDELAY_WR_SYNCING:
if(fd_readl(FD_REG_GCR) & FD_GCR_WR_LOCKED)
{
fd_writel(FD_GCR_WR_LOCK_EN | FD_GCR_CSYNC_WR, FD_REG_GCR);
fd_writel(FD_GCR_WR_LOCK_EN , FD_REG_GCR);
fd_writel(FD_GCR_WR_LOCK_EN | FD_GCR_INPUT_EN, FD_REG_GCR);
hw->wr_state = FDELAY_WR_SYNCED;
}
break;
case FDELAY_WR_SYNCED:
if((fd_readl(FD_REG_GCR) & FD_GCR_WR_LOCKED) == 0)
hw->wr_state = FDELAY_WR_OFFLINE;
break;
}
if
(
hw
->
wr_enabled
&&
(
fd_readl
(
FD_REG_TCR
)
&
FD_TCR_WR_LOCKED
))
return
1
;
else
if
(
!
hw
->
wr_enabled
)
return
1
;
return hw->wr_state
;
return
0
;
}
#endif
# if 0
/* We might implement SPLL-based DMTD calibration, but not now - don't include in the driver */
...
...
software/lib/fdelay_test.c
View file @
2d9c8d9c
...
...
@@ -8,6 +8,7 @@ extern int spec_fdelay_init(int argc, char *argv[], fdelay_device_t *dev);
main
(
int
argc
,
char
*
argv
[])
{
fdelay_device_t
dev
;
fdelay_time_t
t
;
/* Initialize the fine delay generator */
if
(
spec_fdelay_init
(
argc
,
argv
,
&
dev
)
<
0
)
...
...
@@ -17,12 +18,53 @@ main(int argc, char *argv[])
}
/* Enable trigger input and 50 ohm termination */
fdelay_configure_trigger
(
&
dev
,
1
,
1
);
/* Enable all outputs and set them to 500 ns delay, 100 ns pulse width, single output pulse per trigger */
fdelay_configure_output
(
&
dev
,
1
,
1
,
500000
,
100000
,
100000
,
1
);
/* fdelay_configure_output(&dev,1,1,500000, 100000, 100000, 1);
fdelay_configure_output(&dev,2,1,500000, 100000, 100000, 1);
fdelay_configure_output(&dev,3,1,500000, 100000, 100000, 1);
fdelay_configure_output
(
&
dev
,
4
,
1
,
500000
,
100000
,
100000
,
1
);
fdelay_configure_output(&dev,4,1,500000, 100000, 100000, 1);*/
t
.
utc
=
0
;
t
.
coarse
=
0
;
fdelay_set_time
(
&
dev
,
t
);
fdelay_configure_sync
(
&
dev
,
FDELAY_SYNC_WR
);
fprintf
(
stderr
,
"Syncing with WR Timebase...
\n
"
);
while
(
!
fdelay_check_sync
(
&
dev
))
fprintf
(
stderr
,
"."
);
fprintf
(
stderr
,
" locked!
\n
"
);
fdelay_configure_trigger
(
&
dev
,
1
,
0
);
fdelay_configure_readout
(
&
dev
,
1
);
//int enable)
int
seq_prev
=
0
;
int64_t
t_prev
=
0
;
#if 1
for
(;;)
{
fdelay_time_t
ts
;
int64_t
ts_i
;
if
(
fdelay_read
(
&
dev
,
&
ts
,
1
)
==
1
)
{
ts_i
=
fdelay_to_picos
(
ts
);
fprintf
(
stderr
,
"ts = %-20lld ps, delta = %-20lld, seq = %-6d seq_delta=%-6d
\n
"
,
ts_i
,
ts_i
-
t_prev
,
ts
.
seq_id
,
ts
.
seq_id
-
seq_prev
);
seq_prev
=
ts
.
seq_id
;
t_prev
=
ts_i
;
}
}
#endif
// fdelay_
for
(;;)
{
}
}
software/lib/spec_common.c
View file @
2d9c8d9c
...
...
@@ -50,13 +50,13 @@ int spec_fdelay_init(int argc, char *argv[], fdelay_device_t *dev)
dev
->
writel
=
spec_writel
;
dev
->
readl
=
spec_readl
;
dev
->
base_addr
=
0x8
4
000
;
dev
->
base_addr
=
0x8
0
000
;
if
(
rr_load_bitstream_from_file
(
fw_name
)
<
0
)
/*
if(rr_load_bitstream_from_file(fw_name) < 0)
{
fprintf(stderr,"Failed to load FPGA bitstream.\n");
return -1;
}
}
*/
if
(
fdelay_init
(
dev
)
<
0
)
return
-
1
;
...
...
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