rtl: always report WR time valid status.

Minor cleanup

rtl: always report WR time valid status.
Minor cleanup
2bdeecbd · Tristan Gingold · c9c85ebf · 2bdeecbd · 2bdeecbd
Commit 2bdeecbd authored Mar 25, 2021 by Tristan Gingold
Show whitespace changes
Inline Side-by-side

Showing with 3 additions and 5 deletions

fd_csync_generator.vhd hdl/rtl/fd_csync_generator.vhd +2 -3

fine_delay_core.vhd hdl/rtl/fine_delay_core.vhd +1 -2

No files found.
--- a/hdl/rtl/fd_csync_generator.vhd
+++ b/hdl/rtl/fd_csync_generator.vhd
@@ -124,7 +124,6 @@ architecture behavioral of fd_csync_generator is
  signal utc, utc_sys       : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);

  signal csync_int : std_logic;
-  signal csync_wr  : std_logic;

  signal tmo_restart, tmo_hit : std_logic;

@@ -322,7 +321,7 @@ begin  -- behavioral

    regs_o.tcr_dmtd_stat_i <= dmtd_stat;
    regs_o.tcr_wr_locked_i <= '1' when wr_state = WR_SYNCED else '0';
-    regs_o.tcr_wr_ready_i  <= '1' when (wr_state = WR_SYNCING or wr_state = WR_SYNCED) else '0';
+    regs_o.tcr_wr_ready_i  <= wr_time_valid_i;
    regs_o.tcr_wr_link_i   <= wr_link_up_i;
  end generate gen_with_wr_core;


--- a/hdl/rtl/fine_delay_core.vhd
+++ b/hdl/rtl/fine_delay_core.vhd
@@ -366,14 +366,13 @@ architecture rtl of fine_delay_core is

  signal spi_cs_dac_n, spi_cs_pll_n, spi_cs_gpio_n, spi_mosi : std_logic;

-  signal dmtd_tag_stb, dbg_tag_in, dbg_tag_out : std_logic;
+  signal dbg_tag_in, dbg_tag_out : std_logic;
  
  signal iodelay_ntaps : std_logic_vector(7 downto 0);
  signal iodelay_cnt : unsigned(7 downto 0);
  signal iodelay_div : unsigned(6 downto 0);
  signal iodelay_tick : std_logic;
  signal iodelay_cal_done : std_logic;
-  signal iodelay_cal_in_progress : std_logic;  
  signal iodelay_n_taps_load_refclk_p : std_logic;
  signal iodelay_busy_synced: std_logic;
  signal iodelay_latch_reset : std_logic;