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FMC DEL 1ns 4cha
Commit 23700973 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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spec: update WRPC to v4.0

parent 585895e2
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general-cores @ c0614a39
Subproject commit b7cfb53c1930b3a79f9c0a55d52409a9a413054d Subproject commit c0614a39698510b3faf0d42adf7a7f7c073b08fc
wr-cores @ 20e019e0
Subproject commit 598a2f6ccbf1ac937ff589c0797cd2a487306efe Subproject commit 20e019e07e2d7794d1f6c619d1f3672e53a2b3e7
hdl/syn/spec/Manifest.py
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target = "xilinx" target = "xilinx"
action = "synthesis" action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6slx45t" syn_device = "xc6slx45t"
syn_grade = "-3" syn_grade = "-3"
syn_package = "fgg484" syn_package = "fgg484"
syn_top = "spec_top" syn_top = "spec_top"
syn_project = "spec_fine_delay.xise" syn_project = "spec_fine_delay.xise"
modules = { "local" : [ "../../top/spec", "../../platform" ] } modules = { "local" : [ "../../top/spec", "../../platform" ] }
files = "wrc-release.ram"
\ No newline at end of file
hdl/syn/spec/spec_fine_delay.xise
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hdl/syn/spec/wrc-release.ram deleted 100644 → 0
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hdl/top/spec/spec_top.ucf
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...@@ -204,6 +204,18 @@ NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25"; ...@@ -204,6 +204,18 @@ NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18; NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25"; NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
###########################################################################
## Flash memory SPI interface
###########################################################################
NET "flash_ncs_o" LOC = AA3;
NET "flash_ncs_o" IOSTANDARD = "LVCMOS25";
NET "flash_sclk_o" LOC = Y20;
NET "flash_sclk_o" IOSTANDARD = "LVCMOS25";
NET "flash_mosi_o" LOC = AB20;
NET "flash_mosi_o" IOSTANDARD = "LVCMOS25";
NET "flash_miso_i" LOC = AA20;
NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
#################################################################################### ####################################################################################
# FineDelay V3/V4 pins # FineDelay V3/V4 pins
#################################################################################### ####################################################################################
...@@ -433,8 +445,6 @@ PIN "U_DDR_PLL/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; ...@@ -433,8 +445,6 @@ PIN "U_DDR_PLL/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2014/08/01 #Created by Constraints Editor (xc6slx45t-fgg484-3) - 2014/08/01
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>; NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%; TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtck" TNM_NET = U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtck;
TIMESPEC TS_U_WR_CORE_WRPC_LM32_CORE_gen_profile_medium_icache_debug_U_Wrapped_LM32_jtck = PERIOD "U_WR_CORE/WRPC/LM32_CORE/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtck" 20 ns HIGH 50%;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%; TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback; NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%; TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
......
hdl/top/spec/spec_top.vhd
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...@@ -148,6 +148,14 @@ entity spec_top is ...@@ -148,6 +148,14 @@ entity spec_top is
sfp_tx_disable_o : out std_logic; sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0'; sfp_los_i : in std_logic := '0';
-------------------------------------------------------------------------
-- Flash memory pins
-------------------------------------------------------------------------
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_ncs_o : out std_logic;
flash_miso_i : in std_logic;
------------------------------------------------------------------------- -------------------------------------------------------------------------
-- Fine Delay Pins -- Fine Delay Pins
------------------------------------------------------------------------- -------------------------------------------------------------------------
...@@ -302,16 +310,18 @@ architecture rtl of spec_top is ...@@ -302,16 +310,18 @@ architecture rtl of spec_top is
signal dac_dpll_data : std_logic_vector(15 downto 0); signal dac_dpll_data : std_logic_vector(15 downto 0);
signal phy_tx_data : std_logic_vector(7 downto 0); signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic; signal phy_tx_k : std_logic_vector(0 downto 0);
signal phy_tx_disparity : std_logic; signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic; signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0); signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic; signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic; signal phy_rx_k : std_logic_vector(0 downto 0);
signal phy_rx_enc_err : std_logic; signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0); signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic; signal phy_rst : std_logic;
signal phy_loopen : std_logic; signal phy_loopen : std_logic;
signal phy_loopen_vec : std_logic_vector(2 downto 0);
signal phy_rdy : std_logic;
signal local_reset_n : std_logic; signal local_reset_n : std_logic;
...@@ -623,7 +633,7 @@ begin ...@@ -623,7 +633,7 @@ begin
g_virtual_uart => true, g_virtual_uart => true,
g_with_external_clock_input => false, g_with_external_clock_input => false,
g_aux_clks => 1, g_aux_clks => 1,
g_dpram_initf => "wrc-release.ram", g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_softpll_enable_debugger => false) g_softpll_enable_debugger => false)
...@@ -651,6 +661,8 @@ begin ...@@ -651,6 +661,8 @@ begin
phy_rx_bitslide_i => phy_rx_bitslide, phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst, phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen, phy_loopen_o => phy_loopen,
phy_loopen_vec_o => phy_loopen_vec,
phy_rdy_i => phy_rdy,
led_act_o => LED_RED, led_act_o => LED_RED,
led_link_o => LED_GREEN, led_link_o => LED_GREEN,
...@@ -665,6 +677,11 @@ begin ...@@ -665,6 +677,11 @@ begin
sfp_sda_i => sfp_sda_in, sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b, sfp_det_i => sfp_mod_def0_b,
spi_sclk_o => flash_sclk_o,
spi_ncs_o => flash_ncs_o,
spi_mosi_o => flash_mosi_o,
spi_miso_i => flash_miso_i,
uart_rxd_i => uart_rxd_i, uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
...@@ -721,16 +738,18 @@ begin ...@@ -721,16 +738,18 @@ begin
ch1_ref_clk_i => clk_125m_pllref, ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data, ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k, ch1_tx_k_i => phy_tx_k(0),
ch1_tx_disparity_o => phy_tx_disparity, ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err, ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data, ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk, ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k, ch1_rx_k_o => phy_rx_k(0),
ch1_rx_enc_err_o => phy_rx_enc_err, ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide, ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst, ch1_rst_i => phy_rst,
ch1_loopen_i => '0', --phy_loopen, ch1_loopen_i => phy_loopen,
ch1_loopen_vec_i => phy_loopen_vec,
ch1_rdy_o => phy_rdy,
pad_txn0_o => open, pad_txn0_o => open,
pad_txp0_o => open, pad_txp0_o => open,
pad_rxn0_i => '0', pad_rxn0_i => '0',
......
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