Commit 1c399c91 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/rtl/fd_main_wishbone_slave.vhd: I2C outputs should be set to ones upon reset

parent 7f430c0e
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd -- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Mon Jun 4 13:42:20 2012 -- Created : Fri Dec 14 11:28:02 2012
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd -- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb -- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Oct 24 15:07:30 2012 -- Created : Fri Dec 14 11:28:02 2012
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......
...@@ -849,6 +849,7 @@ write 0: DMTD pattern generation disabled."; ...@@ -849,6 +849,7 @@ write 0: DMTD pattern generation disabled.";
name = "SCL Line out"; name = "SCL Line out";
prefix = "SCL_OUT"; prefix = "SCL_OUT";
type = BIT; type = BIT;
reset_value = 1;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -856,6 +857,7 @@ write 0: DMTD pattern generation disabled."; ...@@ -856,6 +857,7 @@ write 0: DMTD pattern generation disabled.";
name = "SDA Line out"; name = "SDA Line out";
prefix = "SDA_OUT"; prefix = "SDA_OUT";
type = BIT; type = BIT;
reset_value = 1;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
......
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