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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
198cf18b
Commit
198cf18b
authored
Apr 02, 2019
by
Tomasz Wlostowski
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hdl: don't sample start with the falling clock edge
parent
63e28db7
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-13
fd_acam_timestamper.vhd
hdl/rtl/fd_acam_timestamper.vhd
+2
-13
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hdl/rtl/fd_acam_timestamper.vhd
View file @
198cf18b
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Company : CERN
-- Created : 2011-08-24
-- Created : 2011-08-24
-- Last update: 201
3-07-02
-- Last update: 201
9-03-21
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -423,21 +423,10 @@ begin -- behave
...
@@ -423,21 +423,10 @@ begin -- behave
-- Input: tdc_start_i
-- Input: tdc_start_i
-- Output: tdc_start_d
-- Output: tdc_start_d
--
--
-- A synchronizer chain for detecting the relation between clk_tdc_i
-- and clk_ref_i. Since both clocks are almost in phase, the first stage
-- reacts to the falling edge of the reference clock to satisfy setup/hold
-- requirements.
--
p_sync_tdclk_fedge
:
process
(
clk_ref_i
)
begin
if
falling_edge
(
clk_ref_i
)
then
tdc_start_d
(
0
)
<=
tdc_start_i
;
end
if
;
end
process
;
p_sync_tdclk_redge
:
process
(
clk_ref_i
)
p_sync_tdclk_redge
:
process
(
clk_ref_i
)
begin
begin
if
rising_edge
(
clk_ref_i
)
then
if
rising_edge
(
clk_ref_i
)
then
tdc_start_d
(
0
)
<=
tdc_start_i
;
tdc_start_d
(
1
)
<=
tdc_start_d
(
0
);
tdc_start_d
(
1
)
<=
tdc_start_d
(
0
);
tdc_start_d
(
2
)
<=
tdc_start_d
(
1
);
tdc_start_d
(
2
)
<=
tdc_start_d
(
1
);
end
if
;
end
if
;
...
...
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