Merge branch '14-migrate-to-common-ci-and-build-bitstreams' into 'master'

Resolve "migrate to common CI and build bitstreams" Closes #14 See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!3

Merge branch '14-migrate-to-common-ci-and-build-bitstreams' into 'master'
Resolve "migrate to common CI and build bitstreams" Closes #14 See merge request be-cem-edl/fec/hardware-modules/fmc-delay-1ns-8cha!3
16e34dec · Dimitris Lampridis · e1c5c633 · d87e8037 · 16e34dec · 16e34dec
Commit 16e34dec authored Dec 12, 2022 by Dimitris Lampridis
8 changed files
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -4,12 +4,15 @@

 variables:
  GIT_SUBMODULE_STRATEGY: normal
+  EDL_CI_DOC_SRC_PATH: 'doc'
+  EDL_CI_DOC_DST_PATH: '$EDL_CI_EOS_OUTPUT_DIR/doc'

 include:
  - project: 'be-cem-edl/evergreen/gitlab-ci'
    ref: master
    file:
      - 'edl-gitlab-ci.yml'
+  - local: 'hdl/syn/.gitlab-ci.yml'

 cppcheck:
  stage: analyse
@@ -25,18 +28,6 @@ flawfinder:
  script:
    - make -C software/tools flawfinder

-documentation:
-  stage: build
-  image:
-    name: gitlab-registry.cern.ch/coht/common-containers/documentation:latest
-  script:
-    - make -C doc html
-    - mkdir -p $EDL_CI_EOS_OUTPUT_DIR
-    - cp -a doc/_build/html/* $EDL_CI_EOS_OUTPUT_DIR
-  artifacts:
-    paths:
-      - $EDL_CI_EOS_OUTPUT_DIR
-
 .script_fetch_kernel_dep: &script_fetch_kernel_dep
  - git clone -b v1.1.5 --depth 1 https://ohwr.org/project/fmc-sw.git ~/git/fmc
  - export FMC=~/git/fmc

--- a/doc/.gitignore
+++ b/doc/.gitignore
@@ -12,7 +12,6 @@ fine-delay.pdf
 *.texi
 *.toc
 *.tp
-/*.txt
 *.vr
 _build
 .doxystamp

--- a/doc/requirements.txt
+++ b/doc/requirements.txt
+sphinx
+sphinx_rtd_theme
+breathe
--- a/hdl/syn/.gitlab-ci.yml
+++ b/hdl/syn/.gitlab-ci.yml
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+
+variables:
+  _FMC_DELAY_BITSTREAM_DEST: $CI_PROJECT_DIR/$EDL_CI_EOS_OUTPUT_DIR/bitstreams
+
+.syn_template: &syn_template
+  interruptible: true
+  stage: build
+  needs: []
+  tags:
+    - xilinx_ise
+    - "14.7"
+  script:
+    - git submodule init && git submodule update
+    - cd hdl/syn/"$SYN_NAME"/
+    - hdlmake
+    - make
+    - |
+      if [[ $(cat *.par | grep -c "All constraints were met") = 0 ]]
+      then
+        echo -e "\e[31mTiming errors detected in PAR report. Aborting...\e[0m"
+        exit 1
+      fi
+    - tar -cJf $SYN_NAME.tar.xz *.syr *.par *.twr *.bit *.bin
+    - mkdir -p $_FMC_DELAY_BITSTREAM_DEST
+    - cp $SYN_NAME.tar.xz $_FMC_DELAY_BITSTREAM_DEST
+  artifacts:
+    name: "$SYN_NAME-synthesis-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    paths:
+      - $_FMC_DELAY_BITSTREAM_DEST/*
+
+SPEC synthesis:
+  variables:
+    SYN_NAME: "spec"
+  <<: *syn_template
+
+SVEC synthesis:
+  variables:
+    SYN_NAME: "svec"
+  <<: *syn_template
--- a/hdl/.gitignore
+++ b/hdl/.gitignore
@@ -2,24 +2,8 @@
 #
 # SPDX-License-Identifier: CERN-OHL-W-2.0+

-*.*\#
-\#*
-.\#*
-*.*~
-ip_cores/*
-modelsim.ini
-*.wlf
-*.vstf
-work
-*.bak
-syn/*
-transcript
-*.orig
-*#
-*~
-*.out
-*.bk
-transcript
-*.wlf
-*.ram
-*.bmp
+*
+!.gitignore
+!Manifest.py
+!*.ucf
+!syn_extra_steps.tcl
--- a/hdl/syn/spec/syn_extra_steps.tcl
+++ b/hdl/syn/spec/syn_extra_steps.tcl
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
+
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+#xilinx::project set "Keep Hierarchy" "Yes"
+
+xilinx::project save
+
+xilinx::project close
--- a/hdl/syn/svec/.gitignore
+++ b/hdl/syn/svec/.gitignore
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+*
+!.gitignore
+!Manifest.py
+!*.ucf
+!syn_extra_steps.tcl
--- a/hdl/syn/svec/syn_extra_steps.tcl
+++ b/hdl/syn/svec/syn_extra_steps.tcl
+# SPDX-FileCopyrightText: 2020 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC0-1.0
+
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+#xilinx::project set "Keep Hierarchy" "Yes"
+
+xilinx::project save
+
+xilinx::project close