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FMC DEL 1ns 4cha
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FMC DEL 1ns 4cha
Commits
0cae1105
Commit
0cae1105
authored
Nov 06, 2011
by
Tomasz Wlostowski
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software: updated regisers layout
parent
79672157
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2 changed files
with
41 additions
and
4 deletions
+41
-4
fdelay_lib.h
software/include/fdelay_lib.h
+24
-3
fdelay_regs.h
software/include/fdelay_regs.h
+17
-1
No files found.
software/include/fdelay_lib.h
View file @
0cae1105
...
...
@@ -7,6 +7,19 @@
#define FDELAY_FRAC_BITS 12
/* fdelay_get_timing_status() return values: */
#define FDELAY_FREE_RUNNING 0x10
/* attached WR core is offline */
#define FDELAY_WR_OFFLINE 0x8
/* attached WR core is offline */
#define FDELAY_WR_READY 0x1
/* attached WR core is synchronized, we can sync the fine delay core anytime */
#define FDELAY_WR_SYNCING 0x2
/* local oscillator is being synchronized with WR clock */
#define FDELAY_WR_SYNCED 0x4
/* we are synced. */
/* fdelay_configure_sync() flags */
#define FDELAY_SYNC_LOCAL 0x1
/* use local oscillator */
#define FDELAY_SYNC_WR 0x2
/* use White Rabbit */
/* Hardware "handle" structure */
typedef
struct
fdelay_device
{
...
...
@@ -24,9 +37,9 @@ typedef struct fdelay_device
typedef
struct
{
u
int32_t
utc
;
u
int32_t
coarse
;
u
int32_t
frac
;
int32_t
utc
;
int32_t
coarse
;
int32_t
frac
;
uint16_t
seq_id
;
}
fdelay_time_t
;
...
...
@@ -36,6 +49,10 @@ PUBLIC API
--------------------
*/
fdelay_device_t
*
fdelay_create_rawrabbit
(
uint32_t
base_addr
);
fdelay_device_t
*
fdelay_create_minibone
(
char
*
iface
,
char
*
mac_addr
,
uint32_t
base_addr
);
fdelay_time_t
fdelay_from_picos
(
const
uint64_t
ps
);
int64_t
fdelay_to_picos
(
const
fdelay_time_t
t
);
...
...
@@ -45,4 +62,8 @@ int fdelay_read(fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many);
int
fdelay_configure_trigger
(
fdelay_device_t
*
dev
,
int
enable
,
int
termination
);
int
fdelay_configure_output
(
fdelay_device_t
*
dev
,
int
channel
,
int
enable
,
int64_t
delay_ps
,
int64_t
width_ps
);
int
fdelay_configure_sync
(
fdelay_device_t
*
dev
,
int
mode
);
int
fdelay_update_sync_status
(
fdelay_device_t
*
dev
);
#endif
software/include/fdelay_regs.h
View file @
0cae1105
...
...
@@ -3,7 +3,7 @@
* File : fd_core.h
* Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
* Created :
Thu Oct 27 17:38:06
2011
* Created :
Mon Oct 31 17:01:03
2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
...
...
@@ -222,6 +222,20 @@
#define FD_TSBR_FID_SEQID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FD_TSBR_FID_SEQID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: I2C bitbanged IO register */
/* definitions for field: SCL Line out in reg: I2C bitbanged IO register */
#define FD_I2CR_SCL_OUT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: SDA Line out in reg: I2C bitbanged IO register */
#define FD_I2CR_SDA_OUT WBGEN2_GEN_MASK(1, 1)
/* definitions for field: SCL Line in in reg: I2C bitbanged IO register */
#define FD_I2CR_SCL_IN WBGEN2_GEN_MASK(2, 1)
/* definitions for field: SDA Line in in reg: I2C bitbanged IO register */
#define FD_I2CR_SDA_IN WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Delay Control Register (channel 1) */
/* definitions for field: Enable channel in reg: Delay Control Register (channel 1) */
...
...
@@ -460,6 +474,8 @@
#define FD_REG_TSBR_C 0x00000044
/* [0x48]: REG Timestamp Buffer Readout Fine / Seq ID Register */
#define FD_REG_TSBR_FID 0x00000048
/* [0x4c]: REG I2C bitbanged IO register */
#define FD_REG_I2CR 0x0000004c
/* [0x60]: REG Delay Control Register (channel 1) */
#define FD_REG_DCR1 0x00000060
/* [0x64]: REG Fine Range Register (channel 1) */
...
...
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