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FMC DEL 1ns 4cha
Commit 00e5bb85 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fine_delay_core: fully working timestamper

parent 473a40ff
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hdl/rtl/fine_delay_core.vhd
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......@@ -27,7 +27,7 @@ entity fine_delay_core is
trig_cal_o : out std_logic;
-- TDC start signal (copy)
tdc_start_i: in std_logic;
tdc_start_i : in std_logic;
---------------------------------------------------------------------------
-- ACAM TDC-GPX signals (all asynchronous)
......@@ -94,54 +94,73 @@ entity fine_delay_core is
-- WhiteRabbit time sync
---------------------------------------------------------------------------
csync_p1_i : in std_logic;
csync_coarse_i : in std_logic_vector(27 downto 0);
csync_utc_i : in std_logic_vector(31 downto 0);
wr_time_valid_i : in std_logic;
wr_coarse_i : in std_logic_vector(27 downto 0);
wr_utc_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------------------------
-- Wishbone (classic)
---------------------------------------------------------------------------
wb_adr_i : in std_logic_vector(4 downto 0);
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
wb_ack_o : out std_logic;
wb_irq_o : out std_logic
);
end fine_delay_core;
architecture rtl of fine_delay_core is
constant c_RSTR_TRIGGER_VALUE : std_logic_vector(31 downto 0) := x"deadbeef";
constant c_TIMESTAMP_FRAC_BITS : integer := 12;
constant c_RING_BUFFER_SIZE_LOG2 : integer := 8;
constant c_REF_CLK_FREQ : integer := 256;
component fine_delay_wb
component fd_reset_generator
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
clk_ref_i : in std_logic;
regs_b : inout t_fd_registers);
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
rst_n_sys_o : out std_logic;
rst_n_ref_o : out std_logic;
regs_b : inout t_fd_registers);
end component;
component fd_cal_pulse_gen
component fd_gpio
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pulse_o : out std_logic;
pgcr_enable_i : in std_logic;
pgcr_period_i : in std_logic_vector(30 downto 0));
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
regs_b : inout t_fd_registers);
end component;
component fd_wishbone_slave
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
clk_ref_i : in std_logic;
advance_rbuf_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
regs_b : inout t_fd_registers);
end component;
......@@ -169,110 +188,108 @@ architecture rtl of fine_delay_core is
tag_frac_o : out std_logic_vector(g_frac_bits-1 downto 0);
tag_coarse_o : out std_logic_vector(27 downto 0);
tag_utc_o : out std_logic_vector(31 downto 0);
tag_raw_frac_o : out std_logic_vector(22 downto 0);
tag_rearm_p1_i : in std_logic;
tag_valid_p1_o : out std_logic;
tag_valid_o : out std_logic;
csync_coarse_i : in std_logic_vector(27 downto 0);
csync_utc_i : in std_logic_vector(31 downto 0);
csync_p1_i : in std_logic;
regs_b : inout t_fd_registers);
end component;
signal rstn_host_sysclk : std_logic;
signal rstn_host_refclk : std_logic;
signal rstn_host_d0 : std_logic;
signal rstn_host_d1 : std_logic;
signal pulse : std_logic;
signal tag_frac : std_logic_vector(11 downto 0);
signal tag_frac_raw : std_logic_vector(22 downto 0);
component fd_csync_generator
generic (
g_coarse_range : integer;
g_frac_bits : integer);
port (
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
wr_time_valid_i : in std_logic;
wr_utc_i : in std_logic_vector(31 downto 0);
wr_coarse_i : in std_logic_vector(27 downto 0);
csync_p1_o : out std_logic;
csync_utc_o : out std_logic_vector(31 downto 0);
csync_coarse_o : out std_logic_vector(27 downto 0);
regs_b : inout t_fd_registers);
end component;
component fd_ring_buffer
generic (
g_size_log2 : integer;
g_frac_bits : integer);
port (
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
tag_valid_i : in std_logic;
tag_utc_i : in std_logic_vector(31 downto 0);
tag_coarse_i : in std_logic_vector(27 downto 0);
tag_frac_i : in std_logic_vector(g_frac_bits-1 downto 0);
advance_rbuf_i : in std_logic;
buf_irq_o : out std_logic;
regs_b : inout t_fd_registers);
end component;
signal tag_frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
signal tag_coarse : std_logic_vector(27 downto 0);
signal tag_utc : std_logic_vector(31 downto 0);
signal tag_valid_p1 : std_logic;
signal tag_utc : std_logic_vector(31 downto 0);
signal tag_valid : std_logic;
signal regs : t_fd_registers := c_fd_registers_init_value;
signal master_csync_p1 : std_logic;
signal master_csync_utc : std_logic_vector(31 downto 0);
signal master_csync_coarse : std_logic_vector(27 downto 0);
signal rst_n_sys, rst_n_ref : std_logic;
signal regs : t_fd_registers := c_fd_registers_init_value;
signal advance_rbuf : std_logic;
signal rbuf_irq : std_logic;
begin -- rtl
-- drive to 'Z'
-- regs <= c_fd_registers_init_value;
p_soft_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
rstn_host_sysclk <= '0';
else
if(regs.rstr_wr_o = '1' and regs.rstr_o = c_RSTR_TRIGGER_VALUE) then
rstn_host_sysclk <= '0';
else
rstn_host_sysclk <= '1';
end if;
end if;
end if;
end process;
p_sync_reset_refclk : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
rstn_host_refclk <= rst_n_i and rstn_host_sysclk;
rstn_host_d0 <= rstn_host_sysclk;
rstn_host_d1 <= rstn_host_d0;
rstn_host_refclk <= rstn_host_d1;
end if;
end process;
p_gpio_loads : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rstn_host_sysclk = '0') then
spi_cs_dac_n_o <= '1';
spi_cs_pll_n_o <= '1';
spi_cs_gpio_n_o <= '1';
spi_sclk_o <= '0';
spi_mosi_o <= '0';
regs.gprr_miso_i <= '0';
else
if(regs.gpsr_cs_pll_wr_o = '1' and regs.gpsr_cs_pll_o = '1') then
spi_cs_pll_n_o <= '1';
elsif (regs.gpcr_cs_pll_wr_o = '1' and regs.gpcr_cs_pll_o = '1') then
spi_cs_pll_n_o <= '0';
end if;
if(regs.gpsr_cs_gpio_wr_o = '1' and regs.gpsr_cs_gpio_o = '1') then
spi_cs_gpio_n_o <= '1';
elsif (regs.gpcr_cs_gpio_wr_o = '1' and regs.gpcr_cs_gpio_o = '1') then
spi_cs_gpio_n_o <= '0';
end if;
if(regs.gpsr_mosi_wr_o = '1' and regs.gpsr_mosi_o = '1') then
spi_mosi_o <= '1';
elsif (regs.gpcr_mosi_wr_o = '1' and regs.gpcr_mosi_o = '1') then
spi_mosi_o <= '0';
end if;
if(regs.gpsr_sclk_wr_o = '1' and regs.gpsr_sclk_o = '1') then
spi_sclk_o <= '1';
elsif (regs.gpcr_sclk_wr_o = '1' and regs.gpcr_sclk_o = '1') then
spi_sclk_o <= '0';
end if;
regs.gprr_miso_i <= spi_miso_i;
end if;
end if;
end process;
U_WB_SLAVE : fine_delay_wb
U_Reset_Generator : fd_reset_generator
port map (
clk_sys_i => clk_sys_i,
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
rst_n_sys_o => rst_n_sys,
rst_n_ref_o => rst_n_ref,
regs_b => regs);
U_Csync_generator : fd_csync_generator
generic map (
g_coarse_range => c_REF_CLK_FREQ,
g_frac_bits => c_TIMESTAMP_FRAC_BITS)
port map (
rst_n_i => rstn_host_sysclk,
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref,
wr_time_valid_i => wr_time_valid_i,
wr_utc_i => wr_utc_i,
wr_coarse_i => wr_coarse_i,
csync_p1_o => master_csync_p1,
csync_utc_o => master_csync_utc,
csync_coarse_o => master_csync_coarse,
regs_b => regs);
U_GPIO : fd_gpio
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys,
spi_cs_dac_n_o => spi_cs_dac_n_o,
spi_cs_pll_n_o => spi_cs_pll_n_o,
spi_cs_gpio_n_o => spi_cs_gpio_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
regs_b => regs);
U_Wishbon_Slave : fd_wishbone_slave
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_adr_i(4 downto 0),
wb_addr_i => wb_adr_i(5 downto 0),
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
......@@ -282,28 +299,22 @@ begin -- rtl
wb_ack_o => wb_ack_o,
clk_ref_i => clk_ref_i,
regs_b => regs
regs_b => regs,
irq_ts_buf_notempty_i => rbuf_irq,
advance_rbuf_o => advance_rbuf
);
regs.tsfifo_wr_req_i <= not regs.tsfifo_wr_full_o and tag_valid_p1;
regs.tsfifo_utc_i <= tag_utc;
regs.tsfifo_coarse_i <= tag_coarse;
regs.tsfifo_frac_raw_i <= tag_frac_raw;
regs.tsfifo_frac_i <= "00000000000" & tag_frac;
U_Acam_TSU : fd_acam_timestamper
generic map (
g_min_pulse_width => 3,
g_clk_ref_freq => 125000000,
g_frac_bits => 12)
g_clk_ref_freq => c_REF_CLK_FREQ,
g_frac_bits => c_TIMESTAMP_FRAC_BITS)
port map (
clk_ref_i => clk_ref_i,
rst_n_i => rstn_host_refclk,
rst_n_i => rst_n_ref,
tdc_start_i => tdc_start_i,
trig_a_n_i => trig_a_n_i,
trig_a_n_i => trig_a_n_i,
acam_d_o => acam_d_o,
acam_d_i => acam_d_i,
......@@ -317,41 +328,41 @@ begin -- rtl
acam_start_dis_o => acam_start_dis_o,
acam_alutrigger_o => acam_alutrigger_o,
tag_frac_o => tag_frac(11 downto 0),
tag_coarse_o => tag_coarse,
tag_utc_o => tag_utc,
tag_frac_o => tag_frac,
tag_coarse_o => tag_coarse,
tag_utc_o => tag_utc,
tag_valid_o => tag_valid,
tag_rearm_p1_i => '1',
tag_raw_frac_o => tag_frac_raw,
tag_valid_p1_o => tag_valid_p1,
csync_coarse_i => csync_coarse_i,
csync_utc_i => csync_utc_i,
csync_p1_i => csync_p1_i,
csync_coarse_i => master_csync_coarse,
csync_utc_i => master_csync_utc,
csync_p1_i => master_csync_p1,
regs_b => regs
);
U_Cal_Pulse_Gen: fd_cal_pulse_gen
U_Ring_Buffer : fd_ring_buffer
generic map (
g_size_log2 => c_RING_BUFFER_SIZE_LOG2,
g_frac_bits => c_TIMESTAMP_FRAC_BITS)
port map (
clk_sys_i => clk_ref_i,
rst_n_i => rstn_host_sysclk,
pulse_o => pulse,
pgcr_enable_i => regs.pgcr_enable_o,
pgcr_period_i => regs.pgcr_period_o);
rst_n_sys_i => rst_n_sys,
rst_n_ref_i => rst_n_ref,
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
tag_valid_i => tag_valid,
tag_utc_i => tag_utc,
tag_coarse_i => tag_coarse,
tag_frac_i => tag_frac,
trig_cal_o <= '0';
advance_rbuf_i => advance_rbuf,
buf_irq_o => rbuf_irq,
regs_b => regs);
trig_cal_o <= '0';
regs.tdcsr_load_i <= '0';
-- regs.tdcsr_err_i <= acam_err_i;
regs.tdcsr_empty_i <= acam_emptyf_i;
delay_len_o <= (others => '0');
delay_pulse_o(0) <= pulse;
delay_pulse_o(1) <= pulse;
delay_pulse_o(2) <= pulse;
delay_pulse_o(3) <= pulse;
delay_val_o <= (others => '0');
end rtl;
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