spec_fine_delay.xise 80.1 KB
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
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    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
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  </header>

15
  <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
16 17

  <files>
18 19 20 21
    <file xil_pn:name="../../../platform/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
    </file>
    <file xil_pn:name="../../../platform/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
22 23
      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
    </file>
24
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
25 26
      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
    </file>
27
    <file xil_pn:name="../../../top/spec/wr/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
    </file>
30
    <file xil_pn:name="../../../top/spec/wr/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
    </file>
33
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
34 35
      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
    </file>
36
    <file xil_pn:name="../../../platform/fd_ddr_driver.vhd" xil_pn:type="FILE_VHDL">
37 38
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    </file>
39
    <file xil_pn:name="../../../platform/fd_ddr_pll.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    </file>
42
    <file xil_pn:name="../../../rtl/fd_channel_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
43 44
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
    </file>
45
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    </file>
48
    <file xil_pn:name="../../../rtl/fd_ts_adder.vhd" xil_pn:type="FILE_VHDL">
49 50
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    </file>
51
    <file xil_pn:name="../../../rtl/fd_main_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
52 53
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    </file>
54
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
55 56
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
    </file>
57
    <file xil_pn:name="../../../rtl/fd_timestamper_stat_unit.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
    </file>
60
    <file xil_pn:name="../../../rtl/fine_delay_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
    </file>
63
    <file xil_pn:name="../../../rtl/fd_csync_generator.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
    </file>
66
    <file xil_pn:name="../../../rtl/fd_delay_line_arbiter.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
    </file>
69
    <file xil_pn:name="../../../rtl/fd_spi_master.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
    </file>
72
    <file xil_pn:name="../../../rtl/fd_spi_dac_arbiter.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
    </file>
75
    <file xil_pn:name="../../../rtl/fd_acam_timestamp_postprocessor.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
    </file>
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    <file xil_pn:name="../../../rtl/fine_delay_core.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
    </file>
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    <file xil_pn:name="../../../rtl/fd_channel_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
    </file>
84
    <file xil_pn:name="../../../rtl/fd_reset_generator.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
    </file>
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    <file xil_pn:name="../../../rtl/fd_delay_channel_driver.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
    </file>
90
    <file xil_pn:name="../../../rtl/fd_acam_timestamper.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
    </file>
93
    <file xil_pn:name="../../../rtl/fd_dmtd_insertion_calibrator.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
    </file>
96
    <file xil_pn:name="../../../rtl/fd_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    </file>
99
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
    </file>
105
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
    </file>
111
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
    </file>
114
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
    </file>
117
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
    </file>
120
    <file xil_pn:name="../../../top/spec/wr/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
    </file>
123
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
    </file>
129
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
    </file>
138
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
    </file>
141
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
    </file>
144
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
    </file>
147
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
    </file>
150
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
    </file>
156
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
    </file>
159
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
    </file>
165
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
    </file>
168
    <file xil_pn:name="../../../rtl/fd_ring_buffer.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
    </file>
171
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
172 173
      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
    </file>
174
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
175 176
      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
    </file>
177
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
178 179
      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
    </file>
183
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
184 185
      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
    </file>
186
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
193 194
      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
    </file>
195
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
196 197
      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
    </file>
198
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
199 200
      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
    </file>
201
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
202 203
      <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
    </file>
204
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
205 206
      <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
    </file>
207
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
208 209
      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
    </file>
210
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
211 212
      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
    </file>
213
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
    </file>
219
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
220 221
      <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
    </file>
222
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
223 224
      <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
    </file>
225
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
226 227
      <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
    </file>
228
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
229 230
      <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
    </file>
231
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
232 233
      <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
235 236
      <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
    </file>
237
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
    </file>
240
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
    </file>
243
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
244 245
      <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
    </file>
246
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
247 248
      <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
    </file>
249
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
250 251
      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
    </file>
252
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
253 254
      <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
    </file>
255
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
    </file>
258
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
259 260
      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
    </file>
261
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
262 263
      <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
    </file>
264
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
265 266
      <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
    </file>
267
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
271 272
      <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
    </file>
273
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
274 275
      <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
    </file>
276
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
277 278
      <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
    </file>
279
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
280 281
      <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
    </file>
282
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
283 284
      <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
    </file>
285
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
286 287
      <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
    </file>
288
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
289 290
      <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
    </file>
291
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
    </file>
303
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
    </file>
321
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
    </file>
324
    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
    </file>
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    <file xil_pn:name="../../../rtl/fd_main_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
    </file>
387
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
    </file>
393
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
    </file>
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    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
    </file>
402
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
403 404
      <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
    </file>
405
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
    </file>
408
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
    </file>
411
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
    </file>
414
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
    </file>
417
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
    </file>
420
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
421 422
      <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
    </file>
423
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL">
424 425
      <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
    </file>
426
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
427 428
      <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
    </file>
429
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
430 431
      <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
    </file>
432
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
433 434
      <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
    </file>
435
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
436 437
      <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
    </file>
438
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
439 440
      <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
    </file>
441
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
442 443
      <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
    </file>
444
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
445 446
      <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
    </file>
447
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
448 449
      <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
    </file>
450
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
451 452
      <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
    </file>
453
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
454 455
      <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
    </file>
456
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
457 458
      <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
    </file>
459
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
460 461
      <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
    </file>
462
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
463 464
      <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
    </file>
465
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
466 467
      <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
    </file>
468
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
469 470
      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
    </file>
471
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
472 473
      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
    </file>
474
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
475 476
      <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
    </file>
477
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
478 479
      <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
    </file>
480
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
481 482
      <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
    </file>
483
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
484 485
      <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
    </file>
486
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
487 488
      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
    </file>
489
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
490 491
      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
    </file>
492
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
493 494
      <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
    </file>
495
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
496 497
      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
    </file>
498
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
499 500
      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
    </file>
501
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL">
502 503
      <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
    </file>
504
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
505 506
      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
    </file>
507
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
508 509
      <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
    </file>
510
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
511 512
      <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
    </file>
513
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
514 515
      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
    </file>
516
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
517 518
      <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
    </file>
519
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
520 521
      <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
    </file>
522
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
523 524
      <association xil_pn:name="Implementation" xil_pn:seqID="169"/>
    </file>
525
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
526 527
      <association xil_pn:name="Implementation" xil_pn:seqID="170"/>
    </file>
528
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
529 530
      <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
    </file>
531
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
532 533
      <association xil_pn:name="Implementation" xil_pn:seqID="172"/>
    </file>
534
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
535 536
      <association xil_pn:name="Implementation" xil_pn:seqID="173"/>
    </file>
537
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
538 539
      <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
    </file>
540
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
541 542
      <association xil_pn:name="Implementation" xil_pn:seqID="175"/>
    </file>
543
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
544 545
      <association xil_pn:name="Implementation" xil_pn:seqID="176"/>
    </file>
546
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
547 548
      <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
    </file>
549
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
550 551
      <association xil_pn:name="Implementation" xil_pn:seqID="178"/>
    </file>
552
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
553 554
      <association xil_pn:name="Implementation" xil_pn:seqID="179"/>
    </file>
555
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
556 557
      <association xil_pn:name="Implementation" xil_pn:seqID="180"/>
    </file>
558
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
559 560
      <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
    </file>
561
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
562 563
      <association xil_pn:name="Implementation" xil_pn:seqID="182"/>
    </file>
564
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
565 566
      <association xil_pn:name="Implementation" xil_pn:seqID="183"/>
    </file>
567
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
568 569
      <association xil_pn:name="Implementation" xil_pn:seqID="184"/>
    </file>
570
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
571 572
      <association xil_pn:name="Implementation" xil_pn:seqID="185"/>
    </file>
573
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
574 575
      <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
    </file>
576
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
577 578
      <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
    </file>
579
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
580 581
      <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
    </file>
582
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
583 584
      <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
    </file>
585
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/wbp_mux.vhd" xil_pn:type="FILE_VHDL">
586 587
      <association xil_pn:name="Implementation" xil_pn:seqID="190"/>
    </file>
588
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
589 590
      <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
    </file>
591
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
592 593
      <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
    </file>
594
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
595 596
      <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
    </file>
597
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
598 599
      <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
    </file>
600
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
601 602
      <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
    </file>
603
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
604 605
      <association xil_pn:name="Implementation" xil_pn:seqID="196"/>
    </file>
606
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
607 608
      <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
    </file>
609
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
610 611
      <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
    </file>
612
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
613 614
      <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
    </file>
615
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
616 617
      <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
    </file>
618
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
619 620
      <association xil_pn:name="Implementation" xil_pn:seqID="201"/>
    </file>
621
    <file xil_pn:name="../../../../../../wr-repos/wr-hdl/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
622 623
      <association xil_pn:name="Implementation" xil_pn:seqID="202"/>
    </file>
624
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
625 626
      <association xil_pn:name="Implementation" xil_pn:seqID="203"/>
    </file>
627
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
628 629
      <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
    </file>
630
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_config.vhd" xil_pn:type="FILE_VHDL">
631 632
      <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
    </file>
633
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
634 635
      <association xil_pn:name="Implementation" xil_pn:seqID="206"/>
    </file>
636
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" xil_pn:type="FILE_VHDL">
637 638
      <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
    </file>
639
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" xil_pn:type="FILE_VHDL">
640 641
      <association xil_pn:name="Implementation" xil_pn:seqID="208"/>
    </file>
642
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" xil_pn:type="FILE_VHDL">
643 644
      <association xil_pn:name="Implementation" xil_pn:seqID="209"/>
    </file>
645
    <file xil_pn:name="../../../top/spec/wr/spec_top.vhd" xil_pn:type="FILE_VHDL">
646 647
      <association xil_pn:name="Implementation" xil_pn:seqID="210"/>
    </file>
648
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/piso_flag.vhd" xil_pn:type="FILE_VHDL">
649 650
      <association xil_pn:name="Implementation" xil_pn:seqID="211"/>
    </file>
651
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" xil_pn:type="FILE_VHDL">
652 653
      <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
    </file>
654
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" xil_pn:type="FILE_VHDL">
655 656
      <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
    </file>
657
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" xil_pn:type="FILE_VHDL">
658 659
      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
    </file>
660
    <file xil_pn:name="../../../../../../wr-repos/etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" xil_pn:type="FILE_VHDL">
661 662
      <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
    </file>
663
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
664 665
      <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
    </file>
666
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
667 668
      <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
    </file>
669
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
670 671
      <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
    </file>
672
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
673 674
      <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
    </file>
675
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
676
      <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
677
    </file>
678
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
679
      <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
680
    </file>
681
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
682
      <association xil_pn:name="Implementation" xil_pn:seqID="222"/>
683
    </file>
684
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
685
      <association xil_pn:name="Implementation" xil_pn:seqID="223"/>
686
    </file>
687
    <file xil_pn:name="../../../../../../wr-repos/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
688
      <association xil_pn:name="Implementation" xil_pn:seqID="224"/>
689
    </file>
690
    <file xil_pn:name="../../../top/spec/wr/spec_top.ucf" xil_pn:type="FILE_UCF">
691
      <association xil_pn:name="Implementation" xil_pn:seqID="225"/>
692 693 694
    </file>
  </files>

695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
  <properties>
    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top|rtl" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../top/spec/wr/spec_top.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Output File Name" xil_pn:value="spec_top" xil_pn:valueState="default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_map.vhd" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_timesim.vhd" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_synthesis.vhd" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_translate.vhd" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="spec_top" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/13.1/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="spec_fine_delay" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-09-01T16:21:56" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AD47E2A8B67702228A4AADB4C2314B92" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
  </properties>

1011 1012
  <bindings/>

1013 1014 1015 1016 1017 1018 1019 1020 1021 1022
  <libraries/>

  <autoManagedFiles>
    <!-- The following files are identified by `include statements in verilog -->
    <!-- source files and are automatically managed by Project Navigator.     -->
    <!--                                                                      -->
    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
    <!-- project is analyzed based on files automatically identified as       -->
    <!-- include files.                                                       -->
  </autoManagedFiles>
1023 1024

</project>