spec_fine_delay.xise 96.9 KB
Newer Older
1
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3 4 5 6 7 8 9 10 11

  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
12
    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
13 14
  </header>

15 16 17 18
  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>

  <files>
    <file xil_pn:name="../../platform/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
19 20
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
21
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_spartan6_icon.ngc" xil_pn:type="FILE_NGC">
22 23
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
24
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_spartan6_ila.ngc" xil_pn:type="FILE_NGC">
25 26
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
27
    <file xil_pn:name="../../platform/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
28 29
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
30
    <file xil_pn:name="../../ip_cores/spec/hdl/syn/common/spec_template_common.ucf" xil_pn:type="FILE_UCF">
31 32
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
33
    <file xil_pn:name="../../ip_cores/spec/hdl/syn/common/spec_template_spi.ucf" xil_pn:type="FILE_UCF">
34 35
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
36
    <file xil_pn:name="../../top/spec/spec_top.ucf" xil_pn:type="FILE_UCF">
37 38
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
39
    <file xil_pn:name="../../ip_cores/spec/hdl/syn/common/spec_template_onewire.ucf" xil_pn:type="FILE_UCF">
40 41
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
42
    <file xil_pn:name="../../ip_cores/spec/hdl/syn/common/spec_template_wr.ucf" xil_pn:type="FILE_UCF">
43 44
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
45 46 47
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
48
    </file>
49 50 51
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
52
    </file>
53 54 55
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
56
    </file>
57 58 59
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
60
    </file>
61 62 63
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
64
    </file>
65 66 67
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
68
    </file>
69 70 71
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
72
    </file>
73 74 75
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
76
    </file>
77 78 79
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
80
    </file>
81 82 83
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
84
    </file>
85 86 87
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
88
    </file>
89 90 91
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
92
    </file>
93 94 95
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
96
    </file>
97 98 99
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
100
    </file>
101 102 103
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
104
    </file>
105 106 107
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
108
    </file>
109 110 111
    <file xil_pn:name="../../rtl/fd_reset_generator.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="201"/>
112
    </file>
113 114 115
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
116
    </file>
117 118 119
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
120
    </file>
121 122 123
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
124
    </file>
125 126 127
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="222"/>
128
    </file>
129 130 131
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
132
    </file>
133 134
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
135 136
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    </file>
137 138 139
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
140
    </file>
141 142 143
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
144
    </file>
145 146 147
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
148
    </file>
149 150 151
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
152
    </file>
153 154 155
    <file xil_pn:name="../../platform/fd_ddr_pll.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
156
    </file>
157 158 159
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
160
    </file>
161 162 163
    <file xil_pn:name="../../rtl/fd_delay_line_arbiter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
164
    </file>
165 166 167
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
168
    </file>
169 170 171
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="190"/>
172
    </file>
173 174 175
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
176
    </file>
177 178 179
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
180
    </file>
181 182 183
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
184
    </file>
185 186 187
    <file xil_pn:name="../../rtl/fd_delay_channel_driver.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
188
    </file>
189 190 191
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
192
    </file>
193 194 195
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
196
    </file>
197 198 199
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
200
    </file>
201 202 203
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
204
    </file>
205 206 207
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
208
    </file>
209 210 211
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
212
    </file>
213 214 215
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
216
    </file>
217 218 219
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
220
    </file>
221 222 223
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
224
    </file>
225 226 227
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
228
    </file>
229 230 231
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
232
    </file>
233 234 235
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
236
    </file>
237 238 239
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
240
    </file>
241 242 243
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
244
    </file>
245 246 247
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
248
    </file>
249 250 251
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
252
    </file>
253 254 255
    <file xil_pn:name="../../rtl/fd_spi_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="182"/>
256
    </file>
257 258 259
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
260
    </file>
261 262 263
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
264
    </file>
265 266 267
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="176"/>
268
    </file>
269 270 271
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="179"/>
272
    </file>
273 274 275
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="173"/>
276
    </file>
277 278 279
    <file xil_pn:name="../../rtl/fd_channel_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="184"/>
280
    </file>
281 282 283
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
284
    </file>
285 286 287
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
288
    </file>
289 290
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
291 292
      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
    </file>
293 294 295
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
296
    </file>
297 298 299
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
300
    </file>
301 302 303
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
304
    </file>
305 306 307
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
308
    </file>
309 310 311
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
312
    </file>
313 314 315
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
316
    </file>
317 318 319
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="169"/>
320
    </file>
321 322 323
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
324
    </file>
325 326 327
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
328
    </file>
329 330 331
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
332
    </file>
333 334 335
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
336
    </file>
337 338 339
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
340
    </file>
341 342 343
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
344
    </file>
345 346 347
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
348
    </file>
349 350 351
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
352
    </file>
353 354 355
    <file xil_pn:name="../../rtl/fd_ts_adder.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="180"/>
356
    </file>
357 358 359
    <file xil_pn:name="../../rtl/fd_acam_timestamp_postprocessor.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="185"/>
360
    </file>
361 362 363
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
364
    </file>
365 366 367
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
368
    </file>
369 370 371
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
372
    </file>
373 374 375
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
376
    </file>
377 378 379
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
380
    </file>
381 382 383
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
384
    </file>
385 386 387
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
388
    </file>
389 390 391
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_split/xwb_split.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
392
    </file>
393 394 395
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="170"/>
396
    </file>
397 398 399
    <file xil_pn:name="../../rtl/fine_delay_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
400
    </file>
401 402 403
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
404
    </file>
405 406 407
    <file xil_pn:name="../../rtl/fd_spi_dac_arbiter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
408
    </file>
409 410
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
411 412
      <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
    </file>
413 414 415
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
416
    </file>
417 418 419
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
420
    </file>
421 422 423
    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
424
    </file>
425 426 427
    <file xil_pn:name="../../rtl/fd_timestamper_stat_unit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
428
    </file>
429 430 431
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
432
    </file>
433 434 435
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
436
    </file>
437 438 439
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
440
    </file>
441 442 443
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
444
    </file>
445 446 447
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
448
    </file>
449 450 451
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
452
    </file>
453 454 455
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
456
    </file>
457 458 459
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
460
    </file>
461 462 463
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
464
    </file>
465 466 467
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
468
    </file>
469 470 471
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
472
    </file>
473 474 475
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
476
    </file>
477 478 479
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
480
    </file>
481 482 483
    <file xil_pn:name="../../ip_cores/wr-cores/board/common/wr_board_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
484
    </file>
485 486 487
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
488
    </file>
489 490 491
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
492
    </file>
493 494 495
    <file xil_pn:name="../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="209"/>
496
    </file>
497 498 499
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
500
    </file>
501 502 503
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="127"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
504
    </file>
505 506 507
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
508
    </file>
509 510 511
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="129"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
512
    </file>
513 514 515
    <file xil_pn:name="../../rtl/fine_delay_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="130"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
516
    </file>
517 518 519
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="131"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
520
    </file>
521 522 523
    <file xil_pn:name="../../ip_cores/wr-cores/board/spec/wr_spec_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
524
    </file>
525 526 527
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="133"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
528
    </file>
529 530 531
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="134"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
532
    </file>
533 534 535
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="135"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
536
    </file>
537 538 539
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
540
    </file>
541 542 543
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="137"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
544
    </file>
545 546 547
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="138"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
548
    </file>
549 550 551
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="139"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
552
    </file>
553 554 555
    <file xil_pn:name="../../ip_cores/spec/hdl/rtl/spec_template_wr.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="140"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
556
    </file>
557 558 559
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="141"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
560
    </file>
561 562 563
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
564
    </file>
565 566 567
    <file xil_pn:name="../../rtl/fd_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="183"/>
568
    </file>
569 570 571
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
572
    </file>
573 574 575
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
576
    </file>
577 578 579
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
580
    </file>
581 582 583
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="147"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
584
    </file>
585 586 587
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="148"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
588
    </file>
589 590 591
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
592
    </file>
593 594 595
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="150"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
596
    </file>
597 598 599
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="151"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
600
    </file>
601 602 603
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
604
    </file>
605 606 607
    <file xil_pn:name="../../rtl/fd_main_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="153"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="202"/>
608
    </file>
609 610 611
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
612
    </file>
613 614 615
    <file xil_pn:name="../../rtl/fd_main_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="155"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
616
    </file>
617 618 619
    <file xil_pn:name="../../rtl/fd_dmtd_insertion_calibrator.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="203"/>
620
    </file>
621 622 623
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="172"/>
624
    </file>
625 626 627
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="158"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
628
    </file>
629 630 631
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="159"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
632
    </file>
633 634 635
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="160"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
636
    </file>
637 638 639
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="161"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
640
    </file>
641 642 643
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="162"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
644
    </file>
645 646 647
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/xwb_gn4124_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="163"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="211"/>
648
    </file>
649 650 651
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="164"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
652
    </file>
653 654 655
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="165"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
656
    </file>
657 658 659 660 661 662 663
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="166"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
    </file>
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="167"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
664
    </file>
665 666 667
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="168"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
668
    </file>
669 670 671
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="169"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
672
    </file>
673 674 675
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="170"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="175"/>
676
    </file>
677 678 679
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="171"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
680
    </file>
681 682 683
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/dma_controller_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="172"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
684
    </file>
685 686 687
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="173"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
688
    </file>
689 690 691
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="174"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
692
    </file>
693 694 695
    <file xil_pn:name="../../rtl/fd_csync_generator.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="175"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="206"/>
696
    </file>
697 698 699
    <file xil_pn:name="../../rtl/fd_acam_timestamper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="176"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
700
    </file>
701 702 703
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="177"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="196"/>
704
    </file>
705 706 707
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="178"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
708
    </file>
709 710 711
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="179"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
712
    </file>
713 714 715
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="180"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
716
    </file>
717 718 719
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="181"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="178"/>
720
    </file>
721 722 723
    <file xil_pn:name="../../platform/fd_ddr_driver.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="182"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="208"/>
724
    </file>
725 726 727
    <file xil_pn:name="../../rtl/fd_channel_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="183"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
728
    </file>
729 730 731
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="184"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
732
    </file>
733 734 735
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="185"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
736
    </file>
737 738 739
    <file xil_pn:name="../../rtl/fd_ring_buffer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="186"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
740
    </file>
741 742 743
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="187"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
744
    </file>
745 746 747
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="188"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
748
    </file>
749 750 751
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="189"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
752
    </file>
753 754 755
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="190"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
756
    </file>
757 758 759
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="191"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
760
    </file>
761 762
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="192"/>
763 764
      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
    </file>
765 766 767
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="193"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
768
    </file>
769 770 771
    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="194"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
772
    </file>
773 774 775
    <file xil_pn:name="buildinfo_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="195"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
776
    </file>
777 778 779
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="196"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
780
    </file>
781 782 783
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="197"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
784
    </file>
785 786 787
    <file xil_pn:name="../../top/spec/spec_top.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="198"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="223"/>
788
    </file>
789 790 791
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="199"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
792
    </file>
793 794 795
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="200"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
796
    </file>
797 798 799
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="201"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
800
    </file>
801 802 803
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="202"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
804
    </file>
805 806 807
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="203"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
808
    </file>
809 810 811
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="204"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
812
    </file>
813 814 815
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="205"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
816
    </file>
817 818
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="206"/>
819 820
      <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
    </file>
821 822 823
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="207"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
824
    </file>
825 826 827
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="208"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
828
    </file>
829 830 831
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="209"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
832
    </file>
833 834 835
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="210"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
836
    </file>
837 838 839
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="211"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
840
    </file>
841 842 843
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="212"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
844
    </file>
845 846 847
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="213"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
848
    </file>
849 850 851
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="214"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
852
    </file>
853 854 855
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="215"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
856
    </file>
857 858 859
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="216"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
860
    </file>
861 862 863
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="217"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
864
    </file>
865 866 867
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="218"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
868
    </file>
869 870 871
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="219"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
872
    </file>
873 874 875
    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="220"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
876
    </file>
877 878 879
    <file xil_pn:name="../../ip_cores/wr-cores/board/common/xwrc_board_common.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="221"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
880
    </file>
881 882 883
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="222"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
884
    </file>
885 886 887
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="223"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
888
    </file>
889 890 891
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="224"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
892
    </file>
893 894 895
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="225"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
896
    </file>
897 898 899
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="226"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
900
    </file>
901 902 903
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="227"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
904
    </file>
905 906 907
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="228"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
908
    </file>
909 910 911
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="229"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
912
    </file>
913 914 915
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="230"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
916
    </file>
917 918 919
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="231"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
920
    </file>
921 922
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="232"/>
923 924
      <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
    </file>
925 926 927
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="233"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
928
    </file>
929 930 931
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="234"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
932
    </file>
933 934 935
    <file xil_pn:name="../../ip_cores/spec/hdl/rtl/spec_template_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="235"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="210"/>
936 937 938
    </file>
  </files>

939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260
  <properties>
    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top|arch" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/spec_top.vhd" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Output File Name" xil_pn:value="spec_top" xil_pn:valueState="default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_map.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_timesim.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_synthesis.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_translate.v" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3"