# fd_main_wb_slave

### Fine Delay Main WB Slave

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Reset Register
3.2. ID Register
3.3. Global Control Register
3.4. Timing Control Register
3.5. Time Register - TAI seconds (MSB)
3.6. Time Register - TAI seconds (LSB)
3.7. Time Register - sub-second 125 MHz clock cycles
3.8. TDC Data Register
3.9. TDC control/status reg
3.10. Calibration register
3.11. Softpll Register
3.12. Softpll DAC Register
3.13. Acam to Delay line fractional part Scale Factor Register
3.14. Acam Timestamp Merging Control Register
3.15. Acam Start Offset Register
3.16. Raw Input Events Counter Register
3.17. Tagged Input Events Counter Register
3.18. Input Event Processing Delay Register
3.19. SPI Control Register
3.20. Reference Clock Rate Register
3.21. Timestamp Buffer Control Register
3.22. Timestamp Buffer Interrupt Register
3.23. Timestamp Buffer Readout Seconds Register (MSB)
3.24. Timestamp Buffer Readout Seconds Register (LSB)
3.25. Timestamp Buffer Readout Cycles Register
3.26. Timestamp Buffer Readout Fine / Channel / Seq ID Register
3.27. I2C bitbanged IO register
3.28. Interrupt disable register
3.29. Interrupt enable register
3.30. Interrupt mask register
3.31. Interrupt status register
5. Interrupts
5.1. TS Buffer not empty.
5.2. DMTD Softpll interrupt
5.3. Sync Status Changed

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Reset Register | fd_main_rstr | RSTR
0x1 | REG | ID Register | fd_main_idr | IDR
0x2 | REG | Global Control Register | fd_main_gcr | GCR
0x3 | REG | Timing Control Register | fd_main_tcr | TCR
0x4 | REG | Time Register - TAI seconds (MSB) | fd_main_tm_sech | TM_SECH
0x5 | REG | Time Register - TAI seconds (LSB) | fd_main_tm_secl | TM_SECL
0x6 | REG | Time Register - sub-second 125 MHz clock cycles | fd_main_tm_cycles | TM_CYCLES
0x7 | REG | TDC Data Register | fd_main_tdr | TDR
0x8 | REG | TDC control/status reg | fd_main_tdcsr | TDCSR
0x9 | REG | Calibration register | fd_main_calr | CALR
0xa | REG | Softpll Register | fd_main_spllr | SPLLR
0xb | REG | Softpll DAC Register | fd_main_sdacr | SDACR
0xc | REG | Acam to Delay line fractional part Scale Factor Register | fd_main_adsfr | ADSFR
0xd | REG | Acam Timestamp Merging Control Register | fd_main_atmcr | ATMCR
0xe | REG | Acam Start Offset Register | fd_main_asor | ASOR
0xf | REG | Raw Input Events Counter Register | fd_main_iecraw | IECRAW
0x10 | REG | Tagged Input Events Counter Register | fd_main_iectag | IECTAG
0x11 | REG | Input Event Processing Delay Register | fd_main_iepd | IEPD
0x12 | REG | SPI Control Register | fd_main_scr | SCR
0x13 | REG | Reference Clock Rate Register | fd_main_rcrr | RCRR
0x14 | REG | Timestamp Buffer Control Register | fd_main_tsbcr | TSBCR
0x15 | REG | Timestamp Buffer Interrupt Register | fd_main_tsbir | TSBIR
0x16 | REG | Timestamp Buffer Readout Seconds Register (MSB) | fd_main_tsbr_sech | TSBR_SECH
0x17 | REG | Timestamp Buffer Readout Seconds Register (LSB) | fd_main_tsbr_secl | TSBR_SECL
0x18 | REG | Timestamp Buffer Readout Cycles Register | fd_main_tsbr_cycles | TSBR_CYCLES
0x19 | REG | Timestamp Buffer Readout Fine / Channel / Seq ID Register | fd_main_tsbr_fid | TSBR_FID
0x1a | REG | I2C bitbanged IO register | fd_main_i2cr | I2CR
0x20 | REG | Interrupt disable register | fd_main_eic_idr | EIC_IDR
0x21 | REG | Interrupt enable register | fd_main_eic_ier | EIC_IER
0x22 | REG | Interrupt mask register | fd_main_eic_imr | EIC_IMR
0x23 | REG | Interrupt status register | fd_main_eic_isr | EIC_ISR

### 2. HDL symbol

→ | rst_n_i |  | Reset Register: |
→ | clk_sys_i |  | fd_main_rstr_rst_fmc_o | →
⇒ | wb_adr_i[5:0] |  | fd_main_rstr_rst_fmc_wr_o | →
⇒ | wb_dat_i[31:0] |  | fd_main_rstr_rst_core_o | →
⇐ | wb_dat_o[31:0] |  | fd_main_rstr_rst_core_wr_o | →
→ | wb_cyc_i |  | fd_main_rstr_lock_o[15:0] | ⇒
⇒ | wb_sel_i[3:0] |  | fd_main_rstr_lock_wr_o | →
→ | wb_stb_i |  |  |
→ | wb_we_i |  | ID Register: |
← | wb_ack_o |  |  |
← | wb_stall_o |  | Global Control Register: |
← | wb_int_o |  | fd_main_gcr_bypass_o | →
|  |  | fd_main_gcr_input_en_o | →
|  |  | fd_main_gcr_ddr_locked_i | ←
|  |  | Timing Control Register: |
|  |  | fd_main_tcr_dmtd_stat_i | ←
|  |  | tcr_rd_ack_o | →
|  |  | fd_main_tcr_wr_enable_o | →
|  |  | fd_main_tcr_wr_locked_i | ←
|  |  | fd_main_tcr_wr_present_i | ←
|  |  | fd_main_tcr_wr_ready_i | ←
|  |  | fd_main_tcr_wr_link_i | ←
|  |  | fd_main_tcr_cap_time_o | →
|  |  | fd_main_tcr_set_time_o | →
|  |  | Time Register - TAI seconds (MSB): |
|  |  | fd_main_tm_sech_o[7:0] | ⇒
|  |  | fd_main_tm_sech_i[7:0] | ⇐
|  |  | fd_main_tm_sech_load_o | →
|  |  | Time Register - TAI seconds (LSB): |
|  |  | fd_main_tm_secl_o[31:0] | ⇒
|  |  | fd_main_tm_secl_i[31:0] | ⇐
|  |  | fd_main_tm_secl_load_o | →
|  |  | Time Register - sub-second 125 MHz clock cycles : |
|  |  | fd_main_tm_cycles_o[27:0] | ⇒
|  |  | fd_main_tm_cycles_i[27:0] | ⇐
|  |  | fd_main_tm_cycles_load_o | →
|  |  | TDC Data Register: |
|  |  | fd_main_tdr_o[27:0] | ⇒
|  |  | fd_main_tdr_i[27:0] | ⇐
|  |  | fd_main_tdr_load_o | →
|  |  | TDC control/status reg: |
|  |  | fd_main_tdcsr_write_o | →
|  |  | fd_main_tdcsr_read_o | →
|  |  | fd_main_tdcsr_empty_i | ←
|  |  | fd_main_tdcsr_stop_en_o | →
|  |  | fd_main_tdcsr_start_dis_o | →
|  |  | fd_main_tdcsr_start_en_o | →
|  |  | fd_main_tdcsr_stop_dis_o | →
|  |  | fd_main_tdcsr_alutrig_o | →
|  |  | Calibration register: |
|  |  | fd_main_calr_cal_pulse_o | →
|  |  | fd_main_calr_cal_pps_o | →
|  |  | fd_main_calr_cal_dmtd_o | →
|  |  | fd_main_calr_psel_o[3:0] | ⇒
|  |  | fd_main_calr_dmtd_fbsel_o | →
|  |  | fd_main_calr_dmtd_tag_i[22:0] | ⇐
|  |  | calr_rd_ack_o | →
|  |  | fd_main_calr_dmtd_tag_rdy_i | ←
|  |  | Softpll Register: |
|  |  | fd_main_spllr_tag_i[19:0] | ⇐
|  |  | spllr_rd_ack_o | →
|  |  | fd_main_spllr_tag_rdy_i | ←
|  |  | fd_main_spllr_mode_o | →
|  |  | Softpll DAC Register: |
|  |  | fd_main_sdacr_dac_val_o[15:0] | ⇒
|  |  | fd_main_sdacr_dac_val_wr_o | →
|  |  | Acam to Delay line fractional part Scale Factor Register: |
|  |  | fd_main_adsfr_o[17:0] | ⇒
|  |  | Acam Timestamp Merging Control Register: |
|  |  | fd_main_atmcr_c_thr_o[3:0] | ⇒
|  |  | fd_main_atmcr_f_thr_o[22:0] | ⇒
|  |  | Acam Start Offset Register: |
|  |  | fd_main_asor_offset_o[22:0] | ⇒
|  |  | Raw Input Events Counter Register : |
|  |  | fd_main_iecraw_i[31:0] | ⇐
|  |  | Tagged Input Events Counter Register : |
|  |  | fd_main_iectag_i[31:0] | ⇐
|  |  | Input Event Processing Delay Register: |
|  |  | fd_main_iepd_rst_stat_o | →
|  |  | fd_main_iepd_pdelay_i[7:0] | ⇐
|  |  | SPI Control Register: |
|  |  | fd_main_scr_data_o[23:0] | ⇒
|  |  | fd_main_scr_data_i[23:0] | ⇐
|  |  | fd_main_scr_data_load_o | →
|  |  | fd_main_scr_sel_dac_o | →
|  |  | fd_main_scr_sel_pll_o | →
|  |  | fd_main_scr_sel_gpio_o | →
|  |  | fd_main_scr_ready_i | ←
|  |  | fd_main_scr_cpol_o | →
|  |  | fd_main_scr_start_o | →
|  |  | Reference Clock Rate Register: |
|  |  | fd_main_rcrr_i[31:0] | ⇐
|  |  | Timestamp Buffer Control Register: |
|  |  | fd_main_tsbcr_chan_mask_o[4:0] | ⇒
|  |  | fd_main_tsbcr_enable_o | →
|  |  | fd_main_tsbcr_purge_o | →
|  |  | fd_main_tsbcr_rst_seq_o | →
|  |  | fd_main_tsbcr_full_i | ←
|  |  | fd_main_tsbcr_empty_i | ←
|  |  | fd_main_tsbcr_count_i[11:0] | ⇐
|  |  | Timestamp Buffer Interrupt Register: |
|  |  | fd_main_tsbir_timeout_o[9:0] | ⇒
|  |  | fd_main_tsbir_threshold_o[11:0] | ⇒
|  |  | Timestamp Buffer Readout Seconds Register (MSB): |
|  |  | fd_main_tsbr_sech_i[7:0] | ⇐
|  |  | Timestamp Buffer Readout Seconds Register (LSB): |
|  |  | fd_main_tsbr_secl_i[31:0] | ⇐
|  |  | Timestamp Buffer Readout Cycles Register: |
|  |  | fd_main_tsbr_cycles_i[27:0] | ⇐
|  |  | Timestamp Buffer Readout Fine / Channel / Seq ID Register: |
|  |  | fd_main_tsbr_fid_channel_i[3:0] | ⇐
|  |  | fd_main_tsbr_fid_fine_i[11:0] | ⇐
|  |  | fd_main_tsbr_fid_seqid_i[15:0] | ⇐
|  |  | advance_rbuf_o | →
|  |  | I2C bitbanged IO register: |
|  |  | fd_main_i2cr_scl_out_o | →
|  |  | fd_main_i2cr_sda_out_o | →
|  |  | fd_main_i2cr_scl_in_i | ←
|  |  | fd_main_i2cr_sda_in_i | ←
|  |  | fd_main_i2cr_dbg_i[3:0] | ⇐
|  |  | TS Buffer not empty.: |
|  |  | irq_ts_buf_notempty_i | ←
|  |  | DMTD Softpll interrupt: |
|  |  | irq_dmtd_spll_i | ←
|  |  | Sync Status Changed: |
|  |  | irq_sync_status_i | ←

### 3. Register description

### 3.1. Reset Register

HW prefix: | fd_main_rstr
HW address: | 0x0
C prefix: | RSTR
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
LOCK[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
LOCK[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | RST_CORE | RST_FMC

- RST_FMC [write-only]: State of the reset Line of the FMC Card
  write 0: FMC is held in reset
  write 1: Normal FMC operation
- RST_CORE [write-only]: State of the reset of the Fine Delay HDL Core
  write 0: FD Core is held in reset
  write 1: Normal FD Core operation
- LOCK [write-only]: Reset magic value
  Protection field - the state of RST_FMC/RST_CORE lines will
  only be updated if LOCK is written with 0xdead

### 3.2. ID Register

HW prefix: | fd_main_idr
HW address: | 0x1
C prefix: | IDR
C offset: | 0x4

Magic identification value (for detecting FD cores by the driver)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
IDR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
IDR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
IDR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IDR[7:0] |  |  |  |  |  |  |

- IDR [read-only]: ID Magic Value
  Always 0xf19ede1a

### 3.3. Global Control Register

HW prefix: | fd_main_gcr
HW address: | 0x2
C prefix: | GCR
C offset: | 0x8

Common control bits used throughout the core.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | DDR_LOCKED | INPUT_EN | BYPASS

- BYPASS [read/write]: Bypass Hardware TDC/Delay Controller
  Descides who is in charge of the TDC and delay lines:
  write 0: TDC and delay lines are controlled by the HDL core (normal operation)
  write 1: TDC and delay lines controlled from the host (calibration)
- INPUT_EN [read/write]: Enable trigger input
  write 1: trigger input is enabled
  write 0: trigger input is disabled
- DDR_LOCKED [read-only]: PLL Locked
  read 1: AD9516 and internal DDR PLLs locked
  read 0: PLL(s) not locked

### 3.4. Timing Control Register

HW prefix: | fd_main_tcr
HW address: | 0x3
C prefix: | TCR
C offset: | 0xc

Controls timing stuff (and White Rabbit referencing)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SET_TIME | CAP_TIME | WR_LINK | WR_READY | WR_PRESENT | WR_LOCKED | WR_ENABLE | DMTD_STAT

- DMTD_STAT [read-only]: DMTD Clock Status
  Status of the DMTD (helper) clock, used for calibration purposes.
  read 0: DMTD clock is not available or has been lost since last read operation of WR_TCR register
  read 1: DMTD clock is OK and has been like this since the previous read of WR_TCR register
- WR_ENABLE [read/write]: WR Timing Enable
  Enables/disables WR synchronization.
  write 1: WR synchronization is enabled. Poll the WR_LOCKED bit to check if the WR Core is still locked.
  write 0: WR synchronization is disabled, the card is in free running mode.
- WR_LOCKED [read-only]: WR Timing Locked
  Status of WR synchronization.
  read 0: local oscillator/time base is not locked to WR (or has lost its lock since last read of WR_TCR register)
  read 1: local oscillator is syntonized to WR and local timebase is aligned with WR time.
- WR_PRESENT [read-only]: WR Core Present
  Indicates whether we have a WR Core associated with this Fine Delay Core. Reflects the state
  of 'g_with_wr_core' generic HDL parameter.
  read 0: No WR Core present.
  read 1: WR Core available.
- WR_READY [read-only]: WR Core Time Ready
  read 0: WR Core time syncing in progress (or no link).
  read 1: WR Core time ready.
- WR_LINK [read-only]: WR Core Link Up
  read 0: Link is down.
  read 1: Link is up.
- CAP_TIME [write-only]: Capture Current Time
  Controls the readout of TM_x registers.
  write 1: transfers the current value of UTC/Nsec counters to TM_x registers.
  write 0: no effect
- SET_TIME [write-only]: Set Current Time
  Controls the write of TM_x registers to the internal time counter.
  write 1: transfers the current value of TM_x to the timebase counters.
  write 0: no effect.
  WARNING Setting time also resynchronizes internal timebase counters, therefore
  time registers must be set after every reset/power cycle.

### 3.5. Time Register - TAI seconds (MSB)

HW prefix: | fd_main_tm_sech
HW address: | 0x4
C prefix: | TM_SECH
C offset: | 0x10

read: value of internal seconds counter taken during write to TCR.CAP_TIME bit.
write: new value of time (acked by writing TCR.SET_TIME bit)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TM_SECH[7:0] |  |  |  |  |  |  |

- TM_SECH [read/write]: TAI seconds (MSB)

### 3.6. Time Register - TAI seconds (LSB)

HW prefix: | fd_main_tm_secl
HW address: | 0x5
C prefix: | TM_SECL
C offset: | 0x14

read: value of internal seconds counter taken during write to TCR.CAP_TIME bit.
write: new value of time (acked by writing TCR.SET_TIME bit)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TM_SECL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TM_SECL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TM_SECL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TM_SECL[7:0] |  |  |  |  |  |  |

- TM_SECL [read/write]: TAI seconds (LSB)

### 3.7. Time Register - sub-second 125 MHz clock cycles

HW prefix: | fd_main_tm_cycles
HW address: | 0x6
C prefix: | TM_CYCLES
C offset: | 0x18

read: value of internal 125 MHz cycles counter taken during write to TCR.CAP_TIME bit.
write: new value of time (acked by writing TCR.SET_TIME bit)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | TM_CYCLES[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TM_CYCLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TM_CYCLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TM_CYCLES[7:0] |  |  |  |  |  |  |

- TM_CYCLES [read/write]: Reference clock cycles

### 3.8. TDC Data Register

HW prefix: | fd_main_tdr
HW address: | 0x7
C prefix: | TDR
C offset: | 0x1c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | TDR[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TDR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TDR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TDR[7:0] |  |  |  |  |  |  |

- TDR [read/write]: TDC Data

### 3.9. TDC control/status reg

HW prefix: | fd_main_tdcsr
HW address: | 0x8
C prefix: | TDCSR
C offset: | 0x20

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ALUTRIG | STOP_DIS | START_EN | START_DIS | STOP_EN | EMPTY | READ | WRITE

- WRITE [write-only]: Start TDC write
- READ [write-only]: Start TDC read
- EMPTY [read-only]: Empty flag
- STOP_EN [write-only]: Start enable
- START_DIS [write-only]: Start disable
- START_EN [write-only]: Stop enable
- STOP_DIS [write-only]: Stop disable
- ALUTRIG [write-only]: write 1: Pulse the Alutrigger line

### 3.10. Calibration register

HW prefix: | fd_main_calr
HW address: | 0x9
C prefix: | CALR
C offset: | 0x24

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DMTD_TAG_RDY | DMTD_TAG[22:16] |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DMTD_TAG[15:8] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DMTD_TAG[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DMTD_FBSEL | PSEL[3:0] | CAL_DMTD | CAL_PPS | CAL_PULSE |  |  |

- CAL_PULSE [write-only]: Triggers calibration pulses
  write 1: Generates synchronous calibration pulse on the channels selected in the PSEL field.
  write 0: no effect.
- CAL_PPS [read/write]: PPS Calibration output enable
  write 1: Feeds TDC input with internally generated PPS signal.
  write 0: PPS generation disabled.
- CAL_DMTD [read/write]: Triggers calibration pulses
  write 1: Enables DMTD test pattern generation on Delay chain input and output selected in PSEL.
  write 0: DMTD pattern generation disabled.
- PSEL [read/write]: Enable pulse generation
  1: enable generation of calibration pulses on the output corresponding to the written bit
  0: disable generation on the corresponding output
- DMTD_FBSEL [read/write]: DMTD Feedback Channel Select
  0: samples DDMTD pattern on the delay input
  1: samples DDMTD pattern on the delay output
- DMTD_TAG [read-only]: DMTD Tag
- DMTD_TAG_RDY [read-only]: DMTD Tag Ready

### 3.11. Softpll Register

HW prefix: | fd_main_spllr
HW address: | 0xa
C prefix: | SPLLR
C offset: | 0x28

Minimal SoftPLL register required to calibrate the card if it there's no WR core in the design

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | MODE | TAG_RDY | TAG[19:16] |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG[7:0] |  |  |  |  |  |  |

- TAG [read-only]: Frequency/Phase tag
- TAG_RDY [read-only]: Tag Ready
- MODE [read/write]: Freq/Phase mode select
  0: sample frequency (pre-locking)
  1: sample phase

### 3.12. Softpll DAC Register

HW prefix: | fd_main_sdacr
HW address: | 0xb
C prefix: | SDACR
C offset: | 0x2c

DMTD Dac Control register, used for calibration when there's no associated WR core

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DAC_VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DAC_VAL[7:0] |  |  |  |  |  |  |

- DAC_VAL [write-only]: DAC Value

### 3.13. Acam to Delay line fractional part Scale Factor Register

HW prefix: | fd_main_adsfr
HW address: | 0xc
C prefix: | ADSFR
C offset: | 0x30

Coefficient used to re-scale the fine part of the timestamp produced by Acam. Contains the number of Delay line bins per one Acam bin. Can be used to compensate the INL error and jitter of the delay lines induced by temperature changes. It's value can be calculated with the following formula: ADFSR = (2 ** 14) * Acam_bin [ps] / Delay_bin [ps]

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | ADSFR[17:16] |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
ADSFR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ADSFR[7:0] |  |  |  |  |  |  |

- ADSFR [read/write]: ADFSR Value

### 3.14. Acam Timestamp Merging Control Register

HW prefix: | fd_main_atmcr
HW address: | 0xd
C prefix: | ATMCR
C offset: | 0x34

Register controlling the merging of the fine timestamps prouced by Acam with the coarse timestamps gatheret by the FPGA. These values are hardware-specific. The register should be loaded with the paramete 'ATMCR' from the mezzanine's configuration EEPROM

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | F_THR[22:20] |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
F_THR[19:12] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
F_THR[11:4] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
F_THR[3:0] | C_THR[3:0] |  |  |  |  |  |

- C_THR [read/write]: Wraparound Coarse Threshold
- F_THR [read/write]: Wraparound Fine Threshold

### 3.15. Acam Start Offset Register

HW prefix: | fd_main_asor
HW address: | 0xe
C prefix: | ASOR
C offset: | 0x38

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | OFFSET[22:16] |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
OFFSET[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
OFFSET[7:0] |  |  |  |  |  |  |

- OFFSET [read/write]: Start Offset

### 3.16. Raw Input Events Counter Register

HW prefix: | fd_main_iecraw
HW address: | 0xf
C prefix: | IECRAW
C offset: | 0x3c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
IECRAW[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
IECRAW[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
IECRAW[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IECRAW[7:0] |  |  |  |  |  |  |

- IECRAW [read-only]: Number of raw events
  Number of all input pulses detected by the timestamper

### 3.17. Tagged Input Events Counter Register

HW prefix: | fd_main_iectag
HW address: | 0x10
C prefix: | IECTAG
C offset: | 0x40

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
IECTAG[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
IECTAG[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
IECTAG[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IECTAG[7:0] |  |  |  |  |  |  |

- IECTAG [read-only]: Number of tagged events
  Number of all input pulses which passed the width checks and have produced valid timestamps.

### 3.18. Input Event Processing Delay Register

HW prefix: | fd_main_iepd
HW address: | 0x11
C prefix: | IEPD
C offset: | 0x44

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | PDELAY[7:7]

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PDELAY[6:0] | RST_STAT |  |  |  |  |  |

- RST_STAT [write-only]: Reset stats
  Write 1: resets the delay/pulse count counters (IECRAW, IECTAG and IEPD_WDELAY)
  write 0: no effect
- PDELAY [read-only]: Processing delay
  Worst-case delay between the input event and the generation of its timestamp. Expressed as a number of 125 MHz clock cycles.

### 3.19. SPI Control Register

HW prefix: | fd_main_scr
HW address: | 0x12
C prefix: | SCR
C offset: | 0x48

Single control register for the SPI Controller, allowing for single-cycle (non-waiting) updates of the DAC, GPIO & PLL.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | START | CPOL | READY | SEL_GPIO | SEL_PLL | SEL_DAC

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DATA[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DATA[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA[7:0] |  |  |  |  |  |  |

- DATA [read/write]: Data
  Data to be read/written from/to the SPI bus
- SEL_DAC [read/write]: Select DAC
  write 1: selects the DAC as the target peripheral of the transfer
- SEL_PLL [read/write]: Select PLL
  write 1: selects the AD9516 PLL as the target peripheral of the transfer
- SEL_GPIO [read/write]: Select GPIO
  write 1: selects the MCP23S17 GPIO as the target peripheral of the transfer
- READY [read-only]: Ready flag
  read 0: SPI controller is busy performing a transfer
  read 1: SPI controller has finished its previous transfer. Read-back data is available in the DATA field
- CPOL [read/write]: Clock Polarity
  0: SPI clock is not inverted
  1: SPI clock is inverted
- START [write-only]: Transfer Start
  write 1: Starts transfer to the selected peripheral
  write 0: no effect

### 3.20. Reference Clock Rate Register

HW prefix: | fd_main_rcrr
HW address: | 0x13
C prefix: | RCRR
C offset: | 0x4c

Provides the momentary value of the internal clock rate counter. Can be used in conjunction with the DAC to roughly syntonize the card's reference clock with a clock coming from an external master installed in the same host (e.g. a CTRV/CTRP) in a software-only way.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RCRR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RCRR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCRR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RCRR[7:0] |  |  |  |  |  |  |

- RCRR [read-only]: Rate

### 3.21. Timestamp Buffer Control Register

HW prefix: | fd_main_tsbcr
HW address: | 0x14
C prefix: | TSBCR
C offset: | 0x50

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | COUNT[11:6] |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
COUNT[5:0] | EMPTY | FULL |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RST_SEQ | PURGE | ENABLE | CHAN_MASK[4:0] |  |  |  |

- CHAN_MASK [read/write]: Channel Mask
  Selects which channels' time tags shall be written to the buffer.
  bit 0 = TDC input, bits 1..4 = Delay outputs
- ENABLE [read/write]: Buffer enable
- PURGE [write-only]: Buffer purge
- RST_SEQ [write-only]: Reset TS Sequence Numbers
- FULL [read-only]: Buffer full
- EMPTY [read-only]: Buffer empty
- COUNT [read-only]: Buffer entries count

### 3.22. Timestamp Buffer Interrupt Register

HW prefix: | fd_main_tsbir
HW address: | 0x15
C prefix: | TSBIR
C offset: | 0x54

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | THRESHOLD[11:6] |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
THRESHOLD[5:0] | TIMEOUT[9:8] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TIMEOUT[7:0] |  |  |  |  |  |  |

- TIMEOUT [read/write]: IRQ timeout [milliseconds]
  The IRQ line will be asserted after TIMEOUT milliseconds even if the amount of data in the buffer is below the THRESHOLD.
- THRESHOLD [read/write]: Interrupt threshold
  Number of samples (timestamps) in the buffer, which will immediately trigger an interrupt.

### 3.23. Timestamp Buffer Readout Seconds Register (MSB)

HW prefix: | fd_main_tsbr_sech
HW address: | 0x16
C prefix: | TSBR_SECH
C offset: | 0x58

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TSBR_SECH[7:0] |  |  |  |  |  |  |

- TSBR_SECH [read-only]: Timestamps TAI Seconds (bits 39-32)

### 3.24. Timestamp Buffer Readout Seconds Register (LSB)

HW prefix: | fd_main_tsbr_secl
HW address: | 0x17
C prefix: | TSBR_SECL
C offset: | 0x5c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TSBR_SECL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TSBR_SECL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TSBR_SECL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TSBR_SECL[7:0] |  |  |  |  |  |  |

- TSBR_SECL [read-only]: Timestamps TAI Seconds (bits 31-0)

### 3.25. Timestamp Buffer Readout Cycles Register

HW prefix: | fd_main_tsbr_cycles
HW address: | 0x18
C prefix: | TSBR_CYCLES
C offset: | 0x60

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | TSBR_CYCLES[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TSBR_CYCLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TSBR_CYCLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TSBR_CYCLES[7:0] |  |  |  |  |  |  |

- TSBR_CYCLES [read-only]: Cycles Value [in 8 ns ticks]

### 3.26. Timestamp Buffer Readout Fine / Channel / Seq ID Register

HW prefix: | fd_main_tsbr_fid
HW address: | 0x19
C prefix: | TSBR_FID
C offset: | 0x64

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SEQID[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SEQID[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
FINE[11:4] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FINE[3:0] | CHANNEL[3:0] |  |  |  |  |  |

- CHANNEL [read-only]: Channel ID
  ID of the originating channel):
  0 = TDC input, 1..4 = delay outputs
- FINE [read-only]: Fine Value [in phase units]
- SEQID [read-only]: Timestamp Sequence ID

### 3.27. I2C bitbanged IO register

HW prefix: | fd_main_i2cr
HW address: | 0x1a
C prefix: | I2CR
C offset: | 0x68

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DBG[3:0] | SDA_IN | SCL_IN | SDA_OUT | SCL_OUT |  |  |

- SCL_OUT [read/write]: SCL Line out
- SDA_OUT [read/write]: SDA Line out
- SCL_IN [read-only]: SCL Line in
- SDA_IN [read-only]: SDA Line in
- DBG [read-only]: Debug in

### 3.28. Interrupt disable register

HW prefix: | fd_main_eic_idr
HW address: | 0x20
C prefix: | EIC_IDR
C offset: | 0x80

Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | SYNC_STATUS | DMTD_SPLL | TS_BUF_NOTEMPTY

- TS_BUF_NOTEMPTY [write-only]: TS Buffer not empty.
  write 1: disable interrupt 'TS Buffer not empty.'
  write 0: no effect
- DMTD_SPLL [write-only]: DMTD Softpll interrupt
  write 1: disable interrupt 'DMTD Softpll interrupt'
  write 0: no effect
- SYNC_STATUS [write-only]: Sync Status Changed
  write 1: disable interrupt 'Sync Status Changed'
  write 0: no effect

### 3.29. Interrupt enable register

HW prefix: | fd_main_eic_ier
HW address: | 0x21
C prefix: | EIC_IER
C offset: | 0x84

Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | SYNC_STATUS | DMTD_SPLL | TS_BUF_NOTEMPTY

- TS_BUF_NOTEMPTY [write-only]: TS Buffer not empty.
  write 1: enable interrupt 'TS Buffer not empty.'
  write 0: no effect
- DMTD_SPLL [write-only]: DMTD Softpll interrupt
  write 1: enable interrupt 'DMTD Softpll interrupt'
  write 0: no effect
- SYNC_STATUS [write-only]: Sync Status Changed
  write 1: enable interrupt 'Sync Status Changed'
  write 0: no effect

### 3.30. Interrupt mask register

HW prefix: | fd_main_eic_imr
HW address: | 0x22
C prefix: | EIC_IMR
C offset: | 0x88

Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | SYNC_STATUS | DMTD_SPLL | TS_BUF_NOTEMPTY

- TS_BUF_NOTEMPTY [read-only]: TS Buffer not empty.
  read 1: interrupt 'TS Buffer not empty.' is enabled
  read 0: interrupt 'TS Buffer not empty.' is disabled
- DMTD_SPLL [read-only]: DMTD Softpll interrupt
  read 1: interrupt 'DMTD Softpll interrupt' is enabled
  read 0: interrupt 'DMTD Softpll interrupt' is disabled
- SYNC_STATUS [read-only]: Sync Status Changed
  read 1: interrupt 'Sync Status Changed' is enabled
  read 0: interrupt 'Sync Status Changed' is disabled

### 3.31. Interrupt status register

HW prefix: | fd_main_eic_isr
HW address: | 0x23
C prefix: | EIC_ISR
C offset: | 0x8c

Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | SYNC_STATUS | DMTD_SPLL | TS_BUF_NOTEMPTY

- TS_BUF_NOTEMPTY [read/write]: TS Buffer not empty.
  read 1: interrupt 'TS Buffer not empty.' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'TS Buffer not empty.'
  write 0: no effect
- DMTD_SPLL [read/write]: DMTD Softpll interrupt
  read 1: interrupt 'DMTD Softpll interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'DMTD Softpll interrupt'
  write 0: no effect
- SYNC_STATUS [read/write]: Sync Status Changed
  read 1: interrupt 'Sync Status Changed' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'Sync Status Changed'
  write 0: no effect

### 5. Interrupts

### 5.1. TS Buffer not empty.

HW prefix: | fd_main_ts_buf_notempty
C prefix: | TS_BUF_NOTEMPTY
Trigger: | low level

### 5.2. DMTD Softpll interrupt

HW prefix: | fd_main_dmtd_spll
C prefix: | DMTD_SPLL
Trigger: | rising edge

### 5.3. Sync Status Changed

HW prefix: | fd_main_sync_status
C prefix: | SYNC_STATUS
Trigger: | rising edge