-- -*- Mode: LUA; tab-width: 2 -*-

-------------------------------------------------------------------------------
-- Title        : Fine Delay Core Wishbone register block (main registers)
-- Project      : Fine Delay FMC (FmcDel1ns4cha)
-------------------------------------------------------------------------------
-- File         : fd_main_wb_slave.wb
-- Author       : Tomasz Włostowski
-- Company      : CERN BE-CO-HT
-- Created      : 2011-01-30
-- Last update  : 2012-01-30
-- Standard     : Lua 5.1
-- Dependencies : wbgen2 ver 0.6+
-------------------------------------------------------------------------------
-- Description: Wishbone register block definition for the Fine Delay Core.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 - 2012 CERN
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author          Description
-- 2011-01-30  1.0      twlostow        Created
-------------------------------------------------------------------------------

peripheral {
   name = "Fine Delay Main WB Slave";
   hdl_entity = "fd_main_wb_slave";
   hdl_prefix = "fd_main";
   c_prefix = "fd";

   reg {
      name = "Reset Register";
      prefix = "RSTR";

      field {
         name = "State of the reset Line of the FMC Card";
         description = "write 0: FMC is held in reset\
                        write 1: Normal FMC operation";
         type = PASS_THROUGH;
         size = 1;
         prefix = "RST_FMC";	
      };

      field {
         name = "State of the reset of the Fine Delay HDL Core";
         description = "write 0: FD Core is held in reset\
                        write 1: Normal FD Core operation";
         type = PASS_THROUGH;
         size = 1;
         prefix = "RST_CORE";	
      };

      field {
         name = "Reset magic value";
         description = "Protection field - the state of RST_FMC/RST_CORE lines will\
                        only be updated if LOCK is written with 0xdead";
         type = PASS_THROUGH;
         prefix = "LOCK";
         align = 16;
         size = 16;
      };
   };

   reg {
      name = "ID Register";
      description = "Magic identification value (for detecting FD cores by the driver)";
      prefix = "IDR";

      field {
         name = "ID Magic Value";
         description = "Always 0xf19ede1a";
         size = 32;
         type = CONSTANT;
         value = 0xf19ede1a;
      };
   };

   reg {
      name = "Global Control Register";
      description = "Common control bits used throughout the core.";
      prefix = "GCR";
      
      field {
         clock = "clk_ref_i";

         name = "Bypass Hardware TDC/Delay Controller";
         prefix = "BYPASS";
         description = "Descides who is in charge of the TDC and delay lines:\
         write 0: TDC and delay lines are controlled by the HDL core (normal operation)\
         write 1: TDC and delay lines controlled from the host (calibration)";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         clock = "clk_ref_i";
         
         name = "Enable trigger input";
         description = "write 1: trigger input is enabled\
                        write 0: trigger input is disabled";
         prefix = "INPUT_EN";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };


      field {
         name = "PLL Locked";
         description = "read 1: AD9516 and internal DDR PLLs locked\
         read 0: PLL(s) not locked";
         prefix = "DDR_LOCKED";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

      field {
         name = "Mezzanice Present";
         description = "read 1: FMC card is present (PRSNT_L == 0)\
         read 0: no FMC card in the slot (PRSNT_L == 1)";
         prefix = "FMC_PRESENT";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
   };
   
   reg {
      name = "Timing Control Register";
      description = "Controls timing stuff (and White Rabbit referencing)";
      prefix = "TCR";
      
      
    

      field {
         ack_read = "tcr_rd_ack_o";

         name = "DMTD Clock Status";
         prefix = "DMTD_STAT";
         description = "Status of the DMTD (helper) clock, used for calibration purposes.\
         read 0: DMTD clock is not available or has been lost since last read operation of WR_TCR register\
         read 1: DMTD clock is OK and has been like this since the previous read of WR_TCR register";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

      field {
         name = "WR Timing Enable";
         prefix = "WR_ENABLE";
         description = "Enables/disables WR synchronization.\
         write 1: WR synchronization is enabled. Poll the WR_LOCKED bit to check if the WR Core is still locked.\
         write 0: WR synchronization is disabled, the card is in free running mode.";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };


      field {
         name = "WR Timing Locked";
         prefix = "WR_LOCKED";
         description = "Status of WR synchronization. \
         read 0: local oscillator/time base is not locked to WR (or has lost its lock since last read of WR_TCR register)\
         read 1: local oscillator is syntonized to WR and local timebase is aligned with WR time.";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

     field {
        name = "WR Core Present";
        prefix = "WR_PRESENT";
        description = "Indicates whether we have a WR Core associated with this Fine Delay Core. Reflects the state\
        of 'g_with_wr_core' generic HDL parameter. \
        read 0: No WR Core present.\
        read 1: WR Core available.";
        type = BIT;
        access_bus = READ_ONLY;
        access_dev = WRITE_ONLY;
     }; 

     field {
        name = "WR Core Time Ready";
        prefix = "WR_READY";
        description = "read 0: WR Core time syncing in progress (or no link).\
        read 1: WR Core time ready.";
        type = BIT;
        access_bus = READ_ONLY;
        access_dev = WRITE_ONLY;
     };

     field {
        name = "WR Core Link Up";
        prefix = "WR_LINK";
        description = "read 0: Link is down.\
        read 1: Link is up.";
        type = BIT;
        access_bus = READ_ONLY;
        access_dev = WRITE_ONLY;
     };

     field {
        name = "Capture Current Time";
        prefix = "CAP_TIME";
        description = "Controls the readout of TM_x registers.\
        write 1: transfers the current value of UTC/Nsec counters to TM_x registers.\
        write 0: no effect";
        type = MONOSTABLE;
        clock = "clk_ref_i";
     };

     field {
        name = "Set Current Time";
        prefix = "SET_TIME";
        description = "Controls the write of TM_x registers to the internal time counter.\
        write 1: transfers the current value of TM_x to the timebase counters.\
        write 0: no effect.\
        <b>WARNING</b> Setting time also resynchronizes internal timebase counters, therefore \
        time registers must be set after every reset/power cycle. ";
        type = MONOSTABLE;
        clock = "clk_ref_i";
     };

  };

   reg {
      name = "Time Register - TAI seconds (MSB)";
      prefix = "TM_SECH";
      description = "read: value of internal seconds counter taken during write to TCR.CAP_TIME bit.\
      write: new value of time (acked by writing TCR.SET_TIME bit)";
      field {
         name = "TAI seconds (MSB)";
         size = 8;
         type = SLV;
         access_bus = READ_WRITE;
         access_dev = READ_WRITE;
         load = LOAD_EXT;
         clock = "clk_ref_i";
      };
   };

   reg {
      name = "Time Register - TAI seconds (LSB)";
      prefix = "TM_SECL";
      description = "read: value of internal seconds counter taken during write to TCR.CAP_TIME bit.\
      write: new value of time (acked by writing TCR.SET_TIME bit)";
      field {
         name = "TAI seconds (LSB)";
         size = 32;
         type = SLV;
         access_bus = READ_WRITE;
         access_dev = READ_WRITE;
         load = LOAD_EXT;
         clock = "clk_ref_i";
      };
   };

   reg {
      name = "Time Register - sub-second 125 MHz clock cycles ";
      prefix = "TM_CYCLES";
      description = "read: value of internal 125 MHz cycles counter taken during write to TCR.CAP_TIME bit.\
      write: new value of time (acked by writing TCR.SET_TIME bit)";
      field {
         name = "Reference clock cycles";
         size = 28;
         type = SLV;
         access_bus = READ_WRITE;
         access_dev = READ_WRITE;
         load = LOAD_EXT;
         clock = "clk_ref_i";
      };
   };

   reg {
      name = "TDC Data Register";
      prefix = "TDR";
      
      field {
         clock = "clk_ref_i";
         name = "TDC Data";
         type = SLV;
         size = 28;
         access_bus = READ_WRITE;
         access_dev = READ_WRITE;
         load = LOAD_EXT;
      };
   };


   reg {
      name = "TDC control/status reg";
      prefix = "TDCSR";

      field {
         name = "Start TDC write";
         prefix = "WRITE";
         clock = "clk_ref_i";
         type = MONOSTABLE;
      };

      field {
         name = "Start TDC read";
         prefix = "READ";
         clock = "clk_ref_i";
         type = MONOSTABLE;
      };
      
      field {
         clock = "clk_ref_i";
         name = "Empty flag";
         prefix = "EMPTY";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
      
      field {
         clock = "clk_ref_i";
         name = "Start enable";
         prefix = "STOP_EN";
         type = MONOSTABLE;
      };

      field {
         clock = "clk_ref_i";
         name = "Start disable";
         prefix = "START_DIS";
         type = MONOSTABLE;
      };

      field {
         clock = "clk_ref_i";
         name = "Stop enable";
         prefix = "START_EN";
         type = MONOSTABLE;
      };

      field {
         clock = "clk_ref_i";
         name = "Stop disable";
         prefix = "STOP_DIS";
         type = MONOSTABLE;
      };

      field {
         clock = "clk_ref_i";
         name = "write 1: Pulse the Alutrigger line";
         prefix = "ALUTRIG";
         type = MONOSTABLE;
      };
   };

   reg {
      prefix = "CALR";
      name = "Calibration register";
      
      field {
         clock = "clk_ref_i";
         name = "Triggers calibration pulses";
         description = "write 1: Generates synchronous calibration pulse on the channels selected in the PSEL field.\
         write 0: no effect.";
         prefix = "CAL_PULSE";
         type = MONOSTABLE;
      };

      field {
         clock = "clk_ref_i";
         name = "PPS Calibration output enable";
         description = "write 1: Feeds TDC input with internally generated PPS signal.\
         write 0: PPS generation disabled.";
         prefix = "CAL_PPS";
         type = BIT;
         access_dev = READ_ONLY;
         access_bus = READ_WRITE;
      };

      field {
--         clock = "clk_ref_i";
         name = "Produce DDMTD calibration pattern";
         description = "write 1: Enables DMTD test pattern generation on Delay chain input and output selected in PSEL.\
write 0: DMTD pattern generation disabled.";
         prefix = "CAL_DMTD";
         type = BIT;
         access_dev = READ_ONLY;
         access_bus = READ_WRITE;
      };

      field {
         clock = "clk_ref_i";
         name = "Enable pulse generation";
         description = "1: enable generation of calibration pulses on the output corresponding to the written bit\
         0: disable generation on the corresponding output";
         prefix = "PSEL";
         type = SLV;
         size = 4;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };

   reg {
      prefix = "DMTR_IN";
      name = "DMTD Input Tag Register";
      
      field {
         ack_read = "dmtr_in_rd_ack_o";

         name = "DMTD Tag";
         prefix = "TAG";
         size = 31;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

      field {
         name = "DMTD Tag Ready";
         prefix = "RDY";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
   };

  reg {
      prefix = "DMTR_OUT";
      name = "DMTD Output Tag Register";
      
      field {
         ack_read = "dmtr_out_rd_ack_o";

         name = "DMTD Tag";
         prefix = "TAG";
         size = 31;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

      field {
         name = "DMTD Tag Ready";
         prefix = "RDY";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
   };

   reg {
      prefix = "ADSFR";
      name = "Acam to Delay line fractional part Scale Factor Register";
      description = "Coefficient used to re-scale the fine part of the timestamp produced by Acam. Contains the number of Delay line bins per one Acam bin. Can be used to compensate the INL error and jitter of the delay lines induced by temperature changes. It's value can be calculated with the following formula: <b>ADFSR = (2 ** 14) * Acam_bin [ps] / Delay_bin [ps]</b>";

      field {
         name = "ADFSR Value";
         size = 18;
         type = SLV;
         clock = "clk_ref_i";
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };

   reg {
      prefix = "ATMCR";
      name = "Acam Timestamp Merging Control Register";
      description = "Register controlling the merging of the fine timestamps prouced by Acam with the coarse timestamps gatheret by the FPGA. These values are hardware-specific. The register should be loaded with the paramete 'ATMCR' from the mezzanine's configuration EEPROM";

      field {
         name = "Wraparound Coarse Threshold";
         prefix = "C_THR";
         size = 4;
         type = SLV;
         clock = "clk_ref_i";
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      
      field {
         name = "Wraparound Fine Threshold";
         prefix = "F_THR";
         size = 23;
         type = SLV;
         clock = "clk_ref_i";
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };

   reg {
      prefix = "ASOR";
      name = "Acam Start Offset Register";
      description = "";

      field {
         name = "Start Offset";
         prefix = "OFFSET";
         size = 23;
         type = SLV;
         clock = "clk_ref_i";
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };

   reg {
      name = "Raw Input Events Counter Register ";
      prefix = "IECRAW";

      field {
         name = "Number of raw events";
         description = "Number of all input pulses detected by the timestamper";
         type = SLV;
         size = 32;
         clock = "clk_ref_i";
         access_bus = READ_ONLY;
         access_dev= WRITE_ONLY;
      };

   };

   reg {
      name = "Tagged Input Events Counter Register ";
      prefix = "IECTAG";

      field {
         name = "Number of tagged events";
         description = "Number of all input pulses which passed the width checks and have produced valid timestamps.";
         type = SLV;
         size = 32;
         clock = "clk_ref_i";
         access_bus = READ_ONLY;
         access_dev= WRITE_ONLY;
      };
   };

   reg {
      name = "Input Event Processing Delay Register";
      prefix = "IEPD";

      field {
         name = "Reset stats";
         prefix = "RST_STAT";
         description = "Write 1: resets the delay/pulse count counters (IECRAW, IECTAG and IEPD_WDELAY)\
         write 0: no effect";
         type = MONOSTABLE;
         clock = "clk_ref_i";
      };

      field {
         name = "Processing delay";
         description = "Worst-case delay between the input event and the generation of its timestamp. Expressed as a number of 125 MHz clock cycles.";
         prefix = "PDELAY";
         type = SLV;
         size = 8;
         clock = "clk_ref_i";
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
   };

    reg {
       name = "SPI Control Register";
       prefix = "SCR";
       description = "Single control register for the SPI Controller, allowing for single-cycle (non-waiting) updates of the DAC, GPIO & PLL.";
       field {
          name = "Data";
          prefix = "DATA";
          size = 24;
          description = "Data to be read/written from/to the SPI bus";
          type = SLV;
          load = LOAD_EXT;
          access_dev = READ_WRITE;
          access_bus = READ_WRITE;
       };
   
       field {
          name = "Select DAC";
          prefix = "SEL_DAC";
          type = BIT;
          description = "write 1: selects the DAC as the target peripheral of the transfer";
          access_bus = READ_WRITE;
          access_dev = READ_ONLY;
       };
       field {
          name = "Select PLL";
          prefix = "SEL_PLL";
          type = BIT;
          description = "write 1: selects the AD9516 PLL as the target peripheral of the transfer";
          access_bus = READ_WRITE;
          access_dev = READ_ONLY;
       };
       field {
          name = "Select GPIO";
          prefix = "SEL_GPIO";
          type = BIT;
          description = "write 1: selects the MCP23S17 GPIO as the target peripheral of the transfer";
          access_bus = READ_WRITE;
          access_dev = READ_ONLY;
       };

       field {
          name = "Ready flag";
          prefix = "READY";
          type = BIT;
          description = "read 0: SPI controller is busy performing a transfer\
          read 1: SPI controller has finished its previous transfer. Read-back data is available in the DATA field";
          access_bus = READ_ONLY;
          access_dev = WRITE_ONLY;
       };

       field {
          name = "Clock Polarity";
          description = "0: SPI clock is not inverted\
                         1: SPI clock is inverted";
          prefix = "CPOL";
          type = BIT;
          access_bus = READ_WRITE;
          access_dev = READ_ONLY;
       };

       field {
          name = "Transfer Start";
          prefix = "START";
          type = MONOSTABLE;
          description = "write 1: Starts transfer to the selected peripheral\
          write 0: no effect";
       };
    };


   reg {
      name = "Reference Clock Rate Register";
      prefix = "RCRR";
      description = "Provides the momentary value of the internal clock rate counter. Can be used in conjunction with the DAC to roughly syntonize the card's reference clock with a clock coming from an external master installed in the same host (e.g. a CTRV/CTRP) in a software-only way.";


      field {
         name = "Rate";
         type = SLV;
         size = 32;
         clock = "clk_ref_i";
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      }
   };


   reg {
      name = "Timestamp Buffer Control Register";
      prefix = "TSBCR";


      field {
         name = "Channel Mask";
         prefix = "CHAN_MASK";
         description = "Selects which channels' time tags shall be written to the buffer. \
                        bit 0 = TDC input, bits 1..4 = Delay outputs";

         type = SLV;
         size = 5;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
         clock = "clk_ref_i";
      };

      field {
         name = "Buffer enable";
         prefix = "ENABLE";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         name = "Buffer purge";
         prefix = "PURGE";
         type = MONOSTABLE;
      };

      field {
         name = "Reset TS Sequence Numbers";
         prefix = "RST_SEQ";
         clock = "clk_ref_i";
         type = MONOSTABLE;
      };
      
      field {
         name = "Buffer full";
         prefix = "FULL";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

      field {
         name = "Buffer empty";
         prefix = "EMPTY";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
         ack_read = "tsbcr_read_ack_o";
      };

      field {
         name = "Buffer entries count";
         prefix = "COUNT";
         type = SLV;
         size = 12;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

      field {
         name = "RAW readout mode enable";
         prefix = "RAW";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };

   reg {
      name = "Timestamp Buffer Interrupt Register";
      prefix = "TSBIR";

      field {
         name = "IRQ timeout [milliseconds]";
         description = "The IRQ line will be asserted after TIMEOUT milliseconds even if the amount of data in the buffer is below the THRESHOLD.";
         prefix = "TIMEOUT";
         type = SLV;
         size = 10;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         name = "Interrupt threshold";
         description = "Number of samples (timestamps) in the buffer, which will immediately trigger an interrupt.";
         prefix = "THRESHOLD";
         type = SLV;
         size = 12;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };


   reg {
      name = "Timestamp Buffer Readout Seconds Register (MSB)";
      prefix = "TSBR_SECH";

      field {
         name = "Timestamps TAI Seconds (bits 39-32)";
         size = 8;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY; 
      };
   };

   reg {
      name = "Timestamp Buffer Readout Seconds Register (LSB)";
      prefix = "TSBR_SECL";

      field {
         name = "Timestamps TAI Seconds (bits 31-0)";
         size = 32;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY; 
      };
   };

   reg {
      name = "Timestamp Buffer Readout Cycles Register";
      prefix = "TSBR_CYCLES";

      field {
         name = "Cycles Value [in 8 ns ticks]";
         size = 28;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY; 
      };
   };

   reg {
      name = "Timestamp Buffer Readout Fine / Channel / Seq ID Register";
      prefix = "TSBR_FID";

      field {
         name = "Channel ID";
         prefix = "CHANNEL";
         description = "ID of the originating channel):\
                        0 = TDC input, 1..4 = delay outputs";
         size = 4;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };

      field {
         name = "Fine Value [in phase units]";
         prefix = "FINE";
         size = 12;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY; 
      };

      field {
         name = "Timestamp Sequence ID";
         prefix = "SEQID";
         align = 16;
         size = 16;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY; 
         ack_read = "fid_read_ack_o";
      };
   };

   reg {
      name = "I2C bitbanged IO register";
      prefix = "I2CR";
      field {
         name = "SCL Line out";
         prefix = "SCL_OUT";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "SDA Line out";
         prefix = "SDA_OUT";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "SCL Line in";
         prefix = "SCL_IN";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
      field {
         name = "SDA Line in";
         prefix = "SDA_IN";
         type = BIT;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
   };


   reg {
      name = "Test/Debug register 1";
      prefix = "TDER1";
      
      field {
         name = "VCXO Frequency";
         prefix = "VCXO_FREQ";
         size = 32;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
   };

   reg {
      name = "Test/Debug register 1";
      prefix = "TDER2";
      
      field {
         name = "Peltier PWM drive";
         prefix = "PELT_DRIVE";
         size = 32;
         type = SLV;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };
  
  reg {
      name = "Timestamp Buffer Debug Values Register";
      prefix = "TSBR_DEBUG";

      field {
         name = "Debug value";
         size = 32;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY; 
      };
   };

  reg {
      name = "Timestamp Buffer Advance Register";
      prefix = "TSBR_ADVANCE";

      field {
         name = "Advance buffer readout";
         descriptor = "write 1: transfer the latest sample from the ring buffer to TSBR_SEC/CYCLES/FID registers,\
         write 0: no effect";
         type = MONOSTABLE;
         prefix = "ADV";
      };
   };


   irq {
      name = "TS Buffer not empty.";
      trigger = LEVEL_0;
      prefix = "ts_buf_notempty";
   };

   irq {
      name = "DMTD Softpll interrupt";
      trigger = EDGE_RISING;
      prefix = "dmtd_spll";
   };

   irq {
      name = "Sync Status Changed";
      trigger = EDGE_RISING;
      prefix = "sync_status";
   };
};

