fd_main_wb_slave

Fine Delay Main WB Slave

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Reset Register
3.2. ID Register
3.3. Global Control Register
3.4. Timing Control Register
3.5. Time Register - TAI seconds (MSB)
3.6. Time Register - TAI seconds (LSB)
3.7. Time Register - sub-second 125 MHz clock cycles
3.8. TDC Data Register
3.9. TDC control/status reg
3.10. Calibration register
3.11. DMTD Input Tag Register
3.12. DMTD Output Tag Register
3.13. Acam to Delay line fractional part Scale Factor Register
3.14. Acam Timestamp Merging Control Register
3.15. Acam Start Offset Register
3.16. Raw Input Events Counter Register
3.17. Tagged Input Events Counter Register
3.18. Input Event Processing Delay Register
3.19. SPI Control Register
3.20. Reference Clock Rate Register
3.21. Timestamp Buffer Control Register
3.22. Timestamp Buffer Interrupt Register
3.23. Timestamp Buffer Readout Seconds Register (MSB)
3.24. Timestamp Buffer Readout Seconds Register (LSB)
3.25. Timestamp Buffer Readout Cycles Register
3.26. Timestamp Buffer Readout Fine / Channel / Seq ID Register
3.27. I2C bitbanged IO register
3.28. Test/Debug register 1
3.29. Test/Debug register 1
3.30. Timestamp Buffer Debug Values Register
3.31. Timestamp Buffer Advance Register
3.32. Interrupt disable register
3.33. Interrupt enable register
3.34. Interrupt mask register
3.35. Interrupt status register
5. Interrupts
5.1. TS Buffer not empty.
5.2. DMTD Softpll interrupt
5.3. Sync Status Changed

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Reset Register fd_main_rstr RSTR
0x1 REG ID Register fd_main_idr IDR
0x2 REG Global Control Register fd_main_gcr GCR
0x3 REG Timing Control Register fd_main_tcr TCR
0x4 REG Time Register - TAI seconds (MSB) fd_main_tm_sech TM_SECH
0x5 REG Time Register - TAI seconds (LSB) fd_main_tm_secl TM_SECL
0x6 REG Time Register - sub-second 125 MHz clock cycles fd_main_tm_cycles TM_CYCLES
0x7 REG TDC Data Register fd_main_tdr TDR
0x8 REG TDC control/status reg fd_main_tdcsr TDCSR
0x9 REG Calibration register fd_main_calr CALR
0xa REG DMTD Input Tag Register fd_main_dmtr_in DMTR_IN
0xb REG DMTD Output Tag Register fd_main_dmtr_out DMTR_OUT
0xc REG Acam to Delay line fractional part Scale Factor Register fd_main_adsfr ADSFR
0xd REG Acam Timestamp Merging Control Register fd_main_atmcr ATMCR
0xe REG Acam Start Offset Register fd_main_asor ASOR
0xf REG Raw Input Events Counter Register fd_main_iecraw IECRAW
0x10 REG Tagged Input Events Counter Register fd_main_iectag IECTAG
0x11 REG Input Event Processing Delay Register fd_main_iepd IEPD
0x12 REG SPI Control Register fd_main_scr SCR
0x13 REG Reference Clock Rate Register fd_main_rcrr RCRR
0x14 REG Timestamp Buffer Control Register fd_main_tsbcr TSBCR
0x15 REG Timestamp Buffer Interrupt Register fd_main_tsbir TSBIR
0x16 REG Timestamp Buffer Readout Seconds Register (MSB) fd_main_tsbr_sech TSBR_SECH
0x17 REG Timestamp Buffer Readout Seconds Register (LSB) fd_main_tsbr_secl TSBR_SECL
0x18 REG Timestamp Buffer Readout Cycles Register fd_main_tsbr_cycles TSBR_CYCLES
0x19 REG Timestamp Buffer Readout Fine / Channel / Seq ID Register fd_main_tsbr_fid TSBR_FID
0x1a REG I2C bitbanged IO register fd_main_i2cr I2CR
0x1b REG Test/Debug register 1 fd_main_tder1 TDER1
0x1c REG Test/Debug register 1 fd_main_tder2 TDER2
0x1d REG Timestamp Buffer Debug Values Register fd_main_tsbr_debug TSBR_DEBUG
0x1e REG Timestamp Buffer Advance Register fd_main_tsbr_advance TSBR_ADVANCE
0x20 REG Interrupt disable register fd_main_eic_idr EIC_IDR
0x21 REG Interrupt enable register fd_main_eic_ier EIC_IER
0x22 REG Interrupt mask register fd_main_eic_imr EIC_IMR
0x23 REG Interrupt status register fd_main_eic_isr EIC_ISR

2. HDL symbol

rst_n_i Reset Register:
clk_sys_i fd_main_rstr_rst_fmc_o
wb_adr_i[5:0] fd_main_rstr_rst_fmc_wr_o
wb_dat_i[31:0] fd_main_rstr_rst_core_o
wb_dat_o[31:0] fd_main_rstr_rst_core_wr_o
wb_cyc_i fd_main_rstr_lock_o[15:0]
wb_sel_i[3:0] fd_main_rstr_lock_wr_o
wb_stb_i  
wb_we_i ID Register:
wb_ack_o  
wb_stall_o Global Control Register:
wb_int_o fd_main_gcr_bypass_o
fd_main_gcr_input_en_o
fd_main_gcr_ddr_locked_i
fd_main_gcr_fmc_present_i
 
Timing Control Register:
fd_main_tcr_dmtd_stat_i
tcr_rd_ack_o
fd_main_tcr_wr_enable_o
fd_main_tcr_wr_locked_i
fd_main_tcr_wr_present_i
fd_main_tcr_wr_ready_i
fd_main_tcr_wr_link_i
fd_main_tcr_cap_time_o
fd_main_tcr_set_time_o
 
Time Register - TAI seconds (MSB):
fd_main_tm_sech_o[7:0]
fd_main_tm_sech_i[7:0]
fd_main_tm_sech_load_o
 
Time Register - TAI seconds (LSB):
fd_main_tm_secl_o[31:0]
fd_main_tm_secl_i[31:0]
fd_main_tm_secl_load_o
 
Time Register - sub-second 125 MHz clock cycles :
fd_main_tm_cycles_o[27:0]
fd_main_tm_cycles_i[27:0]
fd_main_tm_cycles_load_o
 
TDC Data Register:
fd_main_tdr_o[27:0]
fd_main_tdr_i[27:0]
fd_main_tdr_load_o
 
TDC control/status reg:
fd_main_tdcsr_write_o
fd_main_tdcsr_read_o
fd_main_tdcsr_empty_i
fd_main_tdcsr_stop_en_o
fd_main_tdcsr_start_dis_o
fd_main_tdcsr_start_en_o
fd_main_tdcsr_stop_dis_o
fd_main_tdcsr_alutrig_o
 
Calibration register:
fd_main_calr_cal_pulse_o
fd_main_calr_cal_pps_o
fd_main_calr_cal_dmtd_o
fd_main_calr_psel_o[3:0]
 
DMTD Input Tag Register:
fd_main_dmtr_in_tag_i[30:0]
dmtr_in_rd_ack_o
fd_main_dmtr_in_rdy_i
 
DMTD Output Tag Register:
fd_main_dmtr_out_tag_i[30:0]
dmtr_out_rd_ack_o
fd_main_dmtr_out_rdy_i
 
Acam to Delay line fractional part Scale Factor Register:
fd_main_adsfr_o[17:0]
 
Acam Timestamp Merging Control Register:
fd_main_atmcr_c_thr_o[3:0]
fd_main_atmcr_f_thr_o[22:0]
 
Acam Start Offset Register:
fd_main_asor_offset_o[22:0]
 
Raw Input Events Counter Register :
fd_main_iecraw_i[31:0]
 
Tagged Input Events Counter Register :
fd_main_iectag_i[31:0]
 
Input Event Processing Delay Register:
fd_main_iepd_rst_stat_o
fd_main_iepd_pdelay_i[7:0]
 
SPI Control Register:
fd_main_scr_data_o[23:0]
fd_main_scr_data_i[23:0]
fd_main_scr_data_load_o
fd_main_scr_sel_dac_o
fd_main_scr_sel_pll_o
fd_main_scr_sel_gpio_o
fd_main_scr_ready_i
fd_main_scr_cpol_o
fd_main_scr_start_o
 
Reference Clock Rate Register:
fd_main_rcrr_i[31:0]
 
Timestamp Buffer Control Register:
fd_main_tsbcr_chan_mask_o[4:0]
fd_main_tsbcr_enable_o
fd_main_tsbcr_purge_o
fd_main_tsbcr_rst_seq_o
fd_main_tsbcr_full_i
fd_main_tsbcr_empty_i
tsbcr_read_ack_o
fd_main_tsbcr_count_i[11:0]
fd_main_tsbcr_raw_o
 
Timestamp Buffer Interrupt Register:
fd_main_tsbir_timeout_o[9:0]
fd_main_tsbir_threshold_o[11:0]
 
Timestamp Buffer Readout Seconds Register (MSB):
fd_main_tsbr_sech_i[7:0]
 
Timestamp Buffer Readout Seconds Register (LSB):
fd_main_tsbr_secl_i[31:0]
 
Timestamp Buffer Readout Cycles Register:
fd_main_tsbr_cycles_i[27:0]
 
Timestamp Buffer Readout Fine / Channel / Seq ID Register:
fd_main_tsbr_fid_channel_i[3:0]
fd_main_tsbr_fid_fine_i[11:0]
fd_main_tsbr_fid_seqid_i[15:0]
fid_read_ack_o
 
I2C bitbanged IO register:
fd_main_i2cr_scl_out_o
fd_main_i2cr_sda_out_o
fd_main_i2cr_scl_in_i
fd_main_i2cr_sda_in_i
 
Test/Debug register 1:
fd_main_tder1_vcxo_freq_i[31:0]
 
Test/Debug register 1:
fd_main_tder2_pelt_drive_o[31:0]
 
Timestamp Buffer Debug Values Register:
fd_main_tsbr_debug_i[31:0]
 
Timestamp Buffer Advance Register:
fd_main_tsbr_advance_adv_o
 
TS Buffer not empty.:
irq_ts_buf_notempty_i
 
DMTD Softpll interrupt:
irq_dmtd_spll_i
 
Sync Status Changed:
irq_sync_status_i

3. Register description

3.1. Reset Register

HW prefix: fd_main_rstr
HW address: 0x0
C prefix: RSTR
C offset: 0x0
31 30 29 28 27 26 25 24
LOCK[15:8]
23 22 21 20 19 18 17 16
LOCK[7:0]
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - RST_CORE RST_FMC

3.2. ID Register

HW prefix: fd_main_idr
HW address: 0x1
C prefix: IDR
C offset: 0x4

Magic identification value (for detecting FD cores by the driver)

31 30 29 28 27 26 25 24
IDR[31:24]
23 22 21 20 19 18 17 16
IDR[23:16]
15 14 13 12 11 10 9 8
IDR[15:8]
7 6 5 4 3 2 1 0
IDR[7:0]

3.3. Global Control Register

HW prefix: fd_main_gcr
HW address: 0x2
C prefix: GCR
C offset: 0x8

Common control bits used throughout the core.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - FMC_PRESENT DDR_LOCKED INPUT_EN BYPASS

3.4. Timing Control Register

HW prefix: fd_main_tcr
HW address: 0x3
C prefix: TCR
C offset: 0xc

Controls timing stuff (and White Rabbit referencing)

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
SET_TIME CAP_TIME WR_LINK WR_READY WR_PRESENT WR_LOCKED WR_ENABLE DMTD_STAT

3.5. Time Register - TAI seconds (MSB)

HW prefix: fd_main_tm_sech
HW address: 0x4
C prefix: TM_SECH
C offset: 0x10

read: value of internal seconds counter taken during write to TCR.CAP_TIME bit.
write: new value of time (acked by writing TCR.SET_TIME bit)

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
TM_SECH[7:0]

3.6. Time Register - TAI seconds (LSB)

HW prefix: fd_main_tm_secl
HW address: 0x5
C prefix: TM_SECL
C offset: 0x14

read: value of internal seconds counter taken during write to TCR.CAP_TIME bit.
write: new value of time (acked by writing TCR.SET_TIME bit)

31 30 29 28 27 26 25 24
TM_SECL[31:24]
23 22 21 20 19 18 17 16
TM_SECL[23:16]
15 14 13 12 11 10 9 8
TM_SECL[15:8]
7 6 5 4 3 2 1 0
TM_SECL[7:0]

3.7. Time Register - sub-second 125 MHz clock cycles

HW prefix: fd_main_tm_cycles
HW address: 0x6
C prefix: TM_CYCLES
C offset: 0x18

read: value of internal 125 MHz cycles counter taken during write to TCR.CAP_TIME bit.
write: new value of time (acked by writing TCR.SET_TIME bit)

31 30 29 28 27 26 25 24
- - - - TM_CYCLES[27:24]
23 22 21 20 19 18 17 16
TM_CYCLES[23:16]
15 14 13 12 11 10 9 8
TM_CYCLES[15:8]
7 6 5 4 3 2 1 0
TM_CYCLES[7:0]

3.8. TDC Data Register

HW prefix: fd_main_tdr
HW address: 0x7
C prefix: TDR
C offset: 0x1c
31 30 29 28 27 26 25 24
- - - - TDR[27:24]
23 22 21 20 19 18 17 16
TDR[23:16]
15 14 13 12 11 10 9 8
TDR[15:8]
7 6 5 4 3 2 1 0
TDR[7:0]

3.9. TDC control/status reg

HW prefix: fd_main_tdcsr
HW address: 0x8
C prefix: TDCSR
C offset: 0x20
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ALUTRIG STOP_DIS START_EN START_DIS STOP_EN EMPTY READ WRITE

3.10. Calibration register

HW prefix: fd_main_calr
HW address: 0x9
C prefix: CALR
C offset: 0x24
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- PSEL[3:0] CAL_DMTD CAL_PPS CAL_PULSE

3.11. DMTD Input Tag Register

HW prefix: fd_main_dmtr_in
HW address: 0xa
C prefix: DMTR_IN
C offset: 0x28
31 30 29 28 27 26 25 24
RDY TAG[30:24]
23 22 21 20 19 18 17 16
TAG[23:16]
15 14 13 12 11 10 9 8
TAG[15:8]
7 6 5 4 3 2 1 0
TAG[7:0]

3.12. DMTD Output Tag Register

HW prefix: fd_main_dmtr_out
HW address: 0xb
C prefix: DMTR_OUT
C offset: 0x2c
31 30 29 28 27 26 25 24
RDY TAG[30:24]
23 22 21 20 19 18 17 16
TAG[23:16]
15 14 13 12 11 10 9 8
TAG[15:8]
7 6 5 4 3 2 1 0
TAG[7:0]

3.13. Acam to Delay line fractional part Scale Factor Register

HW prefix: fd_main_adsfr
HW address: 0xc
C prefix: ADSFR
C offset: 0x30

Coefficient used to re-scale the fine part of the timestamp produced by Acam. Contains the number of Delay line bins per one Acam bin. Can be used to compensate the INL error and jitter of the delay lines induced by temperature changes. It's value can be calculated with the following formula: ADFSR = (2 ** 14) * Acam_bin [ps] / Delay_bin [ps]

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - ADSFR[17:16]
15 14 13 12 11 10 9 8
ADSFR[15:8]
7 6 5 4 3 2 1 0
ADSFR[7:0]

3.14. Acam Timestamp Merging Control Register

HW prefix: fd_main_atmcr
HW address: 0xd
C prefix: ATMCR
C offset: 0x34

Register controlling the merging of the fine timestamps prouced by Acam with the coarse timestamps gatheret by the FPGA. These values are hardware-specific. The register should be loaded with the paramete 'ATMCR' from the mezzanine's configuration EEPROM

31 30 29 28 27 26 25 24
- - - - - F_THR[22:20]
23 22 21 20 19 18 17 16
F_THR[19:12]
15 14 13 12 11 10 9 8
F_THR[11:4]
7 6 5 4 3 2 1 0
F_THR[3:0] C_THR[3:0]

3.15. Acam Start Offset Register

HW prefix: fd_main_asor
HW address: 0xe
C prefix: ASOR
C offset: 0x38

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- OFFSET[22:16]
15 14 13 12 11 10 9 8
OFFSET[15:8]
7 6 5 4 3 2 1 0
OFFSET[7:0]

3.16. Raw Input Events Counter Register

HW prefix: fd_main_iecraw
HW address: 0xf
C prefix: IECRAW
C offset: 0x3c
31 30 29 28 27 26 25 24
IECRAW[31:24]
23 22 21 20 19 18 17 16
IECRAW[23:16]
15 14 13 12 11 10 9 8
IECRAW[15:8]
7 6 5 4 3 2 1 0
IECRAW[7:0]

3.17. Tagged Input Events Counter Register

HW prefix: fd_main_iectag
HW address: 0x10
C prefix: IECTAG
C offset: 0x40
31 30 29 28 27 26 25 24
IECTAG[31:24]
23 22 21 20 19 18 17 16
IECTAG[23:16]
15 14 13 12 11 10 9 8
IECTAG[15:8]
7 6 5 4 3 2 1 0
IECTAG[7:0]

3.18. Input Event Processing Delay Register

HW prefix: fd_main_iepd
HW address: 0x11
C prefix: IEPD
C offset: 0x44
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - PDELAY[7:7]
7 6 5 4 3 2 1 0
PDELAY[6:0] RST_STAT

3.19. SPI Control Register

HW prefix: fd_main_scr
HW address: 0x12
C prefix: SCR
C offset: 0x48

Single control register for the SPI Controller, allowing for single-cycle (non-waiting) updates of the DAC, GPIO & PLL.

31 30 29 28 27 26 25 24
- - START CPOL READY SEL_GPIO SEL_PLL SEL_DAC
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
7 6 5 4 3 2 1 0
DATA[7:0]

3.20. Reference Clock Rate Register

HW prefix: fd_main_rcrr
HW address: 0x13
C prefix: RCRR
C offset: 0x4c

Provides the momentary value of the internal clock rate counter. Can be used in conjunction with the DAC to roughly syntonize the card's reference clock with a clock coming from an external master installed in the same host (e.g. a CTRV/CTRP) in a software-only way.

31 30 29 28 27 26 25 24
RCRR[31:24]
23 22 21 20 19 18 17 16
RCRR[23:16]
15 14 13 12 11 10 9 8
RCRR[15:8]
7 6 5 4 3 2 1 0
RCRR[7:0]

3.21. Timestamp Buffer Control Register

HW prefix: fd_main_tsbcr
HW address: 0x14
C prefix: TSBCR
C offset: 0x50
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- RAW COUNT[11:6]
15 14 13 12 11 10 9 8
COUNT[5:0] EMPTY FULL
7 6 5 4 3 2 1 0
RST_SEQ PURGE ENABLE CHAN_MASK[4:0]

3.22. Timestamp Buffer Interrupt Register

HW prefix: fd_main_tsbir
HW address: 0x15
C prefix: TSBIR
C offset: 0x54
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - THRESHOLD[11:6]
15 14 13 12 11 10 9 8
THRESHOLD[5:0] TIMEOUT[9:8]
7 6 5 4 3 2 1 0
TIMEOUT[7:0]

3.23. Timestamp Buffer Readout Seconds Register (MSB)

HW prefix: fd_main_tsbr_sech
HW address: 0x16
C prefix: TSBR_SECH
C offset: 0x58
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
TSBR_SECH[7:0]

3.24. Timestamp Buffer Readout Seconds Register (LSB)

HW prefix: fd_main_tsbr_secl
HW address: 0x17
C prefix: TSBR_SECL
C offset: 0x5c
31 30 29 28 27 26 25 24
TSBR_SECL[31:24]
23 22 21 20 19 18 17 16
TSBR_SECL[23:16]
15 14 13 12 11 10 9 8
TSBR_SECL[15:8]
7 6 5 4 3 2 1 0
TSBR_SECL[7:0]

3.25. Timestamp Buffer Readout Cycles Register

HW prefix: fd_main_tsbr_cycles
HW address: 0x18
C prefix: TSBR_CYCLES
C offset: 0x60
31 30 29 28 27 26 25 24
- - - - TSBR_CYCLES[27:24]
23 22 21 20 19 18 17 16
TSBR_CYCLES[23:16]
15 14 13 12 11 10 9 8
TSBR_CYCLES[15:8]
7 6 5 4 3 2 1 0
TSBR_CYCLES[7:0]

3.26. Timestamp Buffer Readout Fine / Channel / Seq ID Register

HW prefix: fd_main_tsbr_fid
HW address: 0x19
C prefix: TSBR_FID
C offset: 0x64
31 30 29 28 27 26 25 24
SEQID[15:8]
23 22 21 20 19 18 17 16
SEQID[7:0]
15 14 13 12 11 10 9 8
FINE[11:4]
7 6 5 4 3 2 1 0
FINE[3:0] CHANNEL[3:0]

3.27. I2C bitbanged IO register

HW prefix: fd_main_i2cr
HW address: 0x1a
C prefix: I2CR
C offset: 0x68
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - SDA_IN SCL_IN SDA_OUT SCL_OUT

3.28. Test/Debug register 1

HW prefix: fd_main_tder1
HW address: 0x1b
C prefix: TDER1
C offset: 0x6c
31 30 29 28 27 26 25 24
VCXO_FREQ[31:24]
23 22 21 20 19 18 17 16
VCXO_FREQ[23:16]
15 14 13 12 11 10 9 8
VCXO_FREQ[15:8]
7 6 5 4 3 2 1 0
VCXO_FREQ[7:0]

3.29. Test/Debug register 1

HW prefix: fd_main_tder2
HW address: 0x1c
C prefix: TDER2
C offset: 0x70
31 30 29 28 27 26 25 24
PELT_DRIVE[31:24]
23 22 21 20 19 18 17 16
PELT_DRIVE[23:16]
15 14 13 12 11 10 9 8
PELT_DRIVE[15:8]
7 6 5 4 3 2 1 0
PELT_DRIVE[7:0]

3.30. Timestamp Buffer Debug Values Register

HW prefix: fd_main_tsbr_debug
HW address: 0x1d
C prefix: TSBR_DEBUG
C offset: 0x74
31 30 29 28 27 26 25 24
TSBR_DEBUG[31:24]
23 22 21 20 19 18 17 16
TSBR_DEBUG[23:16]
15 14 13 12 11 10 9 8
TSBR_DEBUG[15:8]
7 6 5 4 3 2 1 0
TSBR_DEBUG[7:0]

3.31. Timestamp Buffer Advance Register

HW prefix: fd_main_tsbr_advance
HW address: 0x1e
C prefix: TSBR_ADVANCE
C offset: 0x78
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - ADV

3.32. Interrupt disable register

HW prefix: fd_main_eic_idr
HW address: 0x20
C prefix: EIC_IDR
C offset: 0x80

Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SYNC_STATUS DMTD_SPLL TS_BUF_NOTEMPTY

3.33. Interrupt enable register

HW prefix: fd_main_eic_ier
HW address: 0x21
C prefix: EIC_IER
C offset: 0x84

Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SYNC_STATUS DMTD_SPLL TS_BUF_NOTEMPTY

3.34. Interrupt mask register

HW prefix: fd_main_eic_imr
HW address: 0x22
C prefix: EIC_IMR
C offset: 0x88

Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SYNC_STATUS DMTD_SPLL TS_BUF_NOTEMPTY

3.35. Interrupt status register

HW prefix: fd_main_eic_isr
HW address: 0x23
C prefix: EIC_ISR
C offset: 0x8c

Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SYNC_STATUS DMTD_SPLL TS_BUF_NOTEMPTY

5. Interrupts

5.1. TS Buffer not empty.

HW prefix: fd_main_ts_buf_notempty
C prefix: TS_BUF_NOTEMPTY
Trigger: high level

5.2. DMTD Softpll interrupt

HW prefix: fd_main_dmtd_spll
C prefix: DMTD_SPLL
Trigger: rising edge

5.3. Sync Status Changed

HW prefix: fd_main_sync_status
C prefix: SYNC_STATUS
Trigger: rising edge