# fd_channel_wb_slave

### Fine Delay Channel WB Slave

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Delay Control Register
3.2. Fine Range Register
3.3. Pulse start time / offset (MSB TAI seconds)
3.4. Pulse start time / offset (LSB TAI seconds)
3.5. Pulse start time / offset (8 ns cycles)
3.6. Pulse start time / offset (sub-cycle fine part)
3.7. Pulse end time / offset (MSB TAI seconds)
3.8. Pulse end time / offset (LSB TAI seconds)
3.9. Pulse end time / offset (8 ns cycles)
3.10. Pulse end time / offset (sub-cycle fine part)
3.11. Pulse spacing (TAI seconds)
3.12. Pulse spacing (8 ns cycles)
3.13. Pulse spacing (sub-cycle fine part)
3.14. Repeat Count Register

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Delay Control Register | fd_channel_dcr | DCR
0x1 | REG | Fine Range Register | fd_channel_frr | FRR
0x2 | REG | Pulse start time / offset (MSB TAI seconds) | fd_channel_u_starth | U_STARTH
0x3 | REG | Pulse start time / offset (LSB TAI seconds) | fd_channel_u_startl | U_STARTL
0x4 | REG | Pulse start time / offset (8 ns cycles) | fd_channel_c_start | C_START
0x5 | REG | Pulse start time / offset (sub-cycle fine part) | fd_channel_f_start | F_START
0x6 | REG | Pulse end time / offset (MSB TAI seconds) | fd_channel_u_endh | U_ENDH
0x7 | REG | Pulse end time / offset (LSB TAI seconds) | fd_channel_u_endl | U_ENDL
0x8 | REG | Pulse end time / offset (8 ns cycles) | fd_channel_c_end | C_END
0x9 | REG | Pulse end time / offset (sub-cycle fine part) | fd_channel_f_end | F_END
0xa | REG | Pulse spacing (TAI seconds) | fd_channel_u_delta | U_DELTA
0xb | REG | Pulse spacing (8 ns cycles) | fd_channel_c_delta | C_DELTA
0xc | REG | Pulse spacing (sub-cycle fine part) | fd_channel_f_delta | F_DELTA
0xd | REG | Repeat Count Register | fd_channel_rcr | RCR

### 2. HDL symbol

→ | rst_n_i |  | Delay Control Register: |
→ | clk_sys_i |  | fd_channel_dcr_enable_o | →
⇒ | wb_adr_i[3:0] |  | fd_channel_dcr_mode_o | →
⇒ | wb_dat_i[31:0] |  | fd_channel_dcr_pg_arm_o | →
⇐ | wb_dat_o[31:0] |  | fd_channel_dcr_pg_trig_i | ←
→ | wb_cyc_i |  | fd_channel_dcr_update_o | →
⇒ | wb_sel_i[3:0] |  | fd_channel_dcr_upd_done_i | ←
→ | wb_stb_i |  | fd_channel_dcr_force_dly_o | →
→ | wb_we_i |  | fd_channel_dcr_no_fine_o | →
← | wb_ack_o |  | fd_channel_dcr_force_hi_o | →
← | wb_stall_o |  |  |
|  |  | Fine Range Register: |
|  |  | fd_channel_frr_o[9:0] | ⇒
|  |  | Pulse start time / offset (MSB TAI seconds): |
|  |  | fd_channel_u_starth_o[7:0] | ⇒
|  |  | Pulse start time / offset (LSB TAI seconds): |
|  |  | fd_channel_u_startl_o[31:0] | ⇒
|  |  | Pulse start time / offset (8 ns cycles): |
|  |  | fd_channel_c_start_o[27:0] | ⇒
|  |  | Pulse start time / offset (sub-cycle fine part): |
|  |  | fd_channel_f_start_o[11:0] | ⇒
|  |  | Pulse end time / offset (MSB TAI seconds): |
|  |  | fd_channel_u_endh_o[7:0] | ⇒
|  |  | Pulse end time / offset (LSB TAI seconds): |
|  |  | fd_channel_u_endl_o[31:0] | ⇒
|  |  | Pulse end time / offset (8 ns cycles): |
|  |  | fd_channel_c_end_o[27:0] | ⇒
|  |  | Pulse end time / offset (sub-cycle fine part): |
|  |  | fd_channel_f_end_o[11:0] | ⇒
|  |  | Pulse spacing (TAI seconds): |
|  |  | fd_channel_u_delta_o[3:0] | ⇒
|  |  | Pulse spacing (8 ns cycles): |
|  |  | fd_channel_c_delta_o[27:0] | ⇒
|  |  | Pulse spacing (sub-cycle fine part): |
|  |  | fd_channel_f_delta_o[11:0] | ⇒
|  |  | Repeat Count Register: |
|  |  | fd_channel_rcr_rep_cnt_o[15:0] | ⇒
|  |  | fd_channel_rcr_cont_o | →

### 3. Register description

### 3.1. Delay Control Register

HW prefix: | fd_channel_dcr
HW address: | 0x0
C prefix: | DCR
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | FORCE_HI

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NO_FINE | FORCE_DLY | UPD_DONE | UPDATE | PG_TRIG | PG_ARM | MODE | ENABLE

- ENABLE [read/write]: Enable channel
  0: channel is disabled
  1: channel is enabled
- MODE [read/write]: Delay mode select
  0: Channel will work as a delay generator, producing delayed copies of pulses comming to the trigger input
  1: Channel will work as a programmable pulse generator - producing a pulse which begins at UTC time [U_START, C_START, F_START] and ends at [U_END, C_END, F_END].
  Warning: MODE_DLY bit can be safely set only when the TDC and the delay logic are disabled (i.e. when GCR.BYPASS = 1)
- PG_ARM [write-only]: Pulse generator arm
  write 1: arms the pulse generator.
  write 0: no effect.
  Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system.
- PG_TRIG [read-only]: Pulse generator triggered
  read 1: pulse generator has been triggered and produced a pulse
  read 0: pulse generator is busy or hasn't triggered yet
- UPDATE [write-only]: Start Delay Update
  write 1: Starts delay update procedure. The start and end times from [U/C/F][START/END] will be transferred in an atomic way to the internal delay/pulse generator registers
  write 0: no effect.
- UPD_DONE [read-only]: Delay Update Done
  read 1: The delays from [U/C/F][START/END] have been loaded into internal registers
  read 0: update operation in progress
- FORCE_DLY [write-only]: Force Calibration Delay
  write 1: preloads the delay line with the contents of FRR register. Used for self-calibration purposes.
  write 0: no effect
- NO_FINE [read/write]: Disable Fine Part update
  write 1: disables updating of the fine part of the pulse delay to allow for producing faster signals (i.e. pulse width/spacing < 200 ns), at the cost of less accurate width/spacing control (multiple of 4 ms).
  write 0: normal operation. Pulse width/spacing must be at least 200 ns.
- FORCE_HI [read/write]: Force Output High
  write 1: Forces constant 1 on the output when the channel is disabled
  write 0: Forces constant 0 on the output when the channel is disabled
  Used for testing/calibration purposes.

### 3.2. Fine Range Register

HW prefix: | fd_channel_frr
HW address: | 0x1
C prefix: | FRR
C offset: | 0x4

Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | FRR[9:8] |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FRR[7:0] |  |  |  |  |  |  |

- FRR [read/write]: Fine Range

### 3.3. Pulse start time / offset (MSB TAI seconds)

HW prefix: | fd_channel_u_starth
HW address: | 0x2
C prefix: | U_STARTH
C offset: | 0x8

TAI seconds (8 upper bits) part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
U_STARTH[7:0] |  |  |  |  |  |  |

- U_STARTH [read/write]: TAI seconds (MSB)

### 3.4. Pulse start time / offset (LSB TAI seconds)

HW prefix: | fd_channel_u_startl
HW address: | 0x3
C prefix: | U_STARTL
C offset: | 0xc

TAI seconds (32 lower bits) part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
U_STARTL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
U_STARTL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
U_STARTL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
U_STARTL[7:0] |  |  |  |  |  |  |

- U_STARTL [read/write]: TAI seconds (LSB)

### 3.5. Pulse start time / offset (8 ns cycles)

HW prefix: | fd_channel_c_start
HW address: | 0x4
C prefix: | C_START
C offset: | 0x10

Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | C_START[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
C_START[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
C_START[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
C_START[7:0] |  |  |  |  |  |  |

- C_START [read/write]: Reference clock cycles

### 3.6. Pulse start time / offset (sub-cycle fine part)

HW prefix: | fd_channel_f_start
HW address: | 0x5
C prefix: | F_START
C offset: | 0x14

Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | F_START[11:8] |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
F_START[7:0] |  |  |  |  |  |  |

- F_START [read/write]: Fractional part

### 3.7. Pulse end time / offset (MSB TAI seconds)

HW prefix: | fd_channel_u_endh
HW address: | 0x6
C prefix: | U_ENDH
C offset: | 0x18

TAI seconds (8 upper bits) part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
U_ENDH[7:0] |  |  |  |  |  |  |

- U_ENDH [read/write]: TAI seconds (MSB)

### 3.8. Pulse end time / offset (LSB TAI seconds)

HW prefix: | fd_channel_u_endl
HW address: | 0x7
C prefix: | U_ENDL
C offset: | 0x1c

TAI seconds (32 lower bits) part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
U_ENDL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
U_ENDL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
U_ENDL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
U_ENDL[7:0] |  |  |  |  |  |  |

- U_ENDL [read/write]: TAI seconds (LSB)

### 3.9. Pulse end time / offset (8 ns cycles)

HW prefix: | fd_channel_c_end
HW address: | 0x8
C prefix: | C_END
C offset: | 0x20

Sub-second part of the pulse endabsolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | C_END[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
C_END[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
C_END[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
C_END[7:0] |  |  |  |  |  |  |

- C_END [read/write]: Reference clock cycles

### 3.10. Pulse end time / offset (sub-cycle fine part)

HW prefix: | fd_channel_f_end
HW address: | 0x9
C prefix: | F_END
C offset: | 0x24

Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | F_END[11:8] |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
F_END[7:0] |  |  |  |  |  |  |

- F_END [read/write]: Fractional part

### 3.11. Pulse spacing (TAI seconds)

HW prefix: | fd_channel_u_delta
HW address: | 0xa
C prefix: | U_DELTA
C offset: | 0x28

TAI seconds between rising edges of subsequent output pulses.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | U_DELTA[3:0] |  |  |

- U_DELTA [read/write]: TAI seconds

### 3.12. Pulse spacing (8 ns cycles)

HW prefix: | fd_channel_c_delta
HW address: | 0xb
C prefix: | C_DELTA
C offset: | 0x2c

Reference clock cycles between rising edges of subsequent output pulses.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | C_DELTA[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
C_DELTA[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
C_DELTA[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
C_DELTA[7:0] |  |  |  |  |  |  |

- C_DELTA [read/write]: Reference clock cycles

### 3.13. Pulse spacing (sub-cycle fine part)

HW prefix: | fd_channel_f_delta
HW address: | 0xc
C prefix: | F_DELTA
C offset: | 0x30

Sub-cycle part of spacing between rising edges of subsequent output pulses.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | F_DELTA[11:8] |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
F_DELTA[7:0] |  |  |  |  |  |  |

- F_DELTA [read/write]: Fractional part

### 3.14. Repeat Count Register

HW prefix: | fd_channel_rcr
HW address: | 0xd
C prefix: | RCR
C offset: | 0x34

Register controlling the number of output pulses to be generated upon reception of a trigger pulse.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | CONT

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
REP_CNT[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
REP_CNT[7:0] |  |  |  |  |  |  |

- REP_CNT [read/write]: Repeat Count
- CONT [read/write]: Continuous Waveform Mode
  write 1: output will produce a contiguous square wave upon receptio of trigger pulse. The generation can be aborted by disabling the channel (DCRx.ENABLE = 0)
  write 0: output will produce trains of REP_CNT+1 pulses.