debugger_gw/fmc-delay: HDL code for stand-alone opperation.

Signed-off-by: Jose Jimenez <ppjm@correo.ugr.es>

debugger_gw/fmc-delay: HDL code for stand-alone opperation.
Signed-off-by: Jose Jimenez <ppjm@correo.ugr.es>
cdb25a4b · Jose Jimenez · 55ed098b · cdb25a4b · cdb25a4b · cdb25a4b
Commit cdb25a4b authored Sep 29, 2014 by Jose Jimenez
11 changed files
--- a/.gitignore
+++ b/.gitignore
+/fmc-delay/fmc-delay-1ns-8cha
+*.ram
+*.bit
+*~
+*.*~
--- a/debugger_gw/fmc-delay/Makefile
+++ b/debugger_gw/fmc-delay/Makefile
+MAKE_DIR       = ./spec
+FMC_DEL_DIR    = ./fmc-delay-1ns-8cha
+GRAL_CORES_DIR = $(FMC_DEL_DIR)/hdl/ip_cores/general-cores
+WR_CORES_DIR   = $(FMC_DEL_DIR)/hdl/ip_cores/wr-cores
+GN_4124_DIR    = $(FMC_DEL_DIR)/hdl/ip_cores/gn4124-core
+
+
+all: git_submodules build_syn_makefile
+	$(MAKE) -C $(MAKE_DIR) -f Makefile
+
+git_submodules:
+	@cd $(FMC_DEL_DIR); \
+	@test -d $(GRAL_CORES_DIR)/syn || git submodule update --init ; \
+	@test -d $(WR_CORES_DIR)/syn   || git submodule update --init ; \
+	@test -d $(GN_4124_DIR)/syn    || git submodule update --init
+
+build_syn_makefile:
+	@cd $(MAKE_DIR); \
+	hdlmake --make-ise --ise-proj
+	
+clean:
+	$(MAKE) -C $(FMC_DEL_DIR)/spec -f Makefile $@
+
+mrproper:
+	$(MAKE) -C $(FMC_DEL_DIR)/spec -f Makefile $@
--- a/debugger_gw/fmc-delay/spec/Makefile
+++ b/debugger_gw/fmc-delay/spec/Makefile
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := spec_fine_delay.xise
+ISE_CRAP := *.b spec_top_std_summary.html *.tcl spec_top_std.bld spec_top_std.cmd_log *.drc spec_top_std.lso *.ncd spec_top_std.ngc spec_top_std.ngd spec_top_std.ngr spec_top_std.pad spec_top_std.par spec_top_std.pcf spec_top_std.prj spec_top_std.ptwx spec_top_std.stx spec_top_std.syr spec_top_std.twr spec_top_std.twx spec_top_std.gise spec_top_std.unroutes spec_top_std.ut spec_top_std.xpi spec_top_std.xst spec_top_std_bitgen.xwbt spec_top_std_envsettings.html spec_top_std_guide.ncd spec_top_std_map.map spec_top_std_map.mrp spec_top_std_map.ncd spec_top_std_map.ngm spec_top_std_map.xrpt spec_top_std_ngdbuild.xrpt spec_top_std_pad.csv spec_top_std_pad.txt spec_top_std_par.xrpt spec_top_std_summary.xml spec_top_std_usage.xml spec_top_std_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
+		xtclsh run.tcl
+
+
+#target for cleaing all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+    
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
--- a/debugger_gw/fmc-delay/spec/Manifest.py
+++ b/debugger_gw/fmc-delay/spec/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+fetchto = "../fmc-delay-1ns-8cha/hdl/ip_cores"
+
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_top = "spec_top_std"
+syn_project = "spec_fine_delay.xise"
+
+modules = { "local" : ["../top", "../fmc-delay-1ns-8cha/hdl/platform", "../../etherbone-core"] }
+
+files = "wrc-ethb.ram"
--- a/debugger_gw/fmc-delay/spec/spec_fine_delay.xise
+++ b/debugger_gw/fmc-delay/spec/spec_fine_delay.xise
--- a/debugger_gw/fmc-delay/spec/wrc-ethb.ram
+++ b/debugger_gw/fmc-delay/spec/wrc-ethb.ram
--- a/debugger_gw/fmc-delay/top/Manifest.py
+++ b/debugger_gw/fmc-delay/top/Manifest.py
+files = ["synthesis_descriptor.vhd", "spec_top_std.vhd", "spec_top.ucf", "spec_reset_gen.vhd"]
+
+fetchto = "../fmc-delay-1ns-8cha/hdl/ip_cores"
+
+modules = {
+    "local" : ["../fmc-delay-1ns-8cha/hdl/rtl", 
+	                      "../fmc-delay-1ns-8cha/hdl/platform",
+	                      "../.."],
+    "git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git",
+					    "git://ohwr.org/hdl-core-lib/gn4124-core.git" ]
+    }
--- a/debugger_gw/fmc-delay/top/spec_reset_gen.vhd
+++ b/debugger_gw/fmc-delay/top/spec_reset_gen.vhd
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.gencores_pkg.all;
+
+entity spec_reset_gen is
+  
+  port (
+    clk_sys_i : in std_logic;
+
+    rst_pcie_n_a_i   : in std_logic;
+    rst_button_n_a_i : in std_logic;
+
+    rst_n_o : out std_logic
+    );
+
+end spec_reset_gen;
+
+architecture behavioral of spec_reset_gen is
+
+  signal powerup_cnt     : unsigned(7 downto 0) := x"00";
+  signal button_synced_n : std_logic;
+  signal pcie_synced_n   : std_logic;
+  signal powerup_n       : std_logic            := '0';
+
+begin  -- behavioral
+
+  U_EdgeDet_PCIe : gc_sync_ffs port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => '1',
+    data_i   => rst_pcie_n_a_i,
+    ppulse_o => pcie_synced_n);
+
+  U_Sync_Button : gc_sync_ffs port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => '1',
+    data_i   => rst_button_n_a_i,
+    synced_o => button_synced_n);
+
+  p_powerup_reset : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(powerup_cnt /= x"ff") then
+        powerup_cnt <= powerup_cnt + 1;
+        powerup_n   <= '0';
+      else
+        powerup_n <= '1';
+      end if;
+    end if;
+  end process;
+
+  rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
+
+end behavioral;
--- a/debugger_gw/fmc-delay/top/spec_top.ucf
+++ b/debugger_gw/fmc-delay/top/spec_top.ucf
--- a/debugger_gw/fmc-delay/top/spec_top_std.vhd
+++ b/debugger_gw/fmc-delay/top/spec_top_std.vhd
--- a/debugger_gw/fmc-delay/top/synthesis_descriptor.vhd
+++ b/debugger_gw/fmc-delay/top/synthesis_descriptor.vhd
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Debugger SDB descriptor
+-- Project    : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
+-------------------------------------------------------------------------------
+-- File       : synthesis_descriptor.vhd
+-- Author     : Jose Jimenez <jjimenez.wr@gmail.com>
+-- Company    : University of Granada
+-- Created    : 2014-07-31
+-- Last update: 2014-07-36
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: SDB descriptor for the WB Debugger and top level of the FMC used
+--              on a SPEC carrier.
+-- Contains synthesis & source repository information.
+-- Warning: this file is modified whenever a synthesis is executed.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use work.wishbone_pkg.all;
+
+package synthesis_descriptor is
+  
+constant c_sdb_FMC_DEL_synthesis_info : t_sdb_synthesis :=
+  (
+    syn_module_name => "spec-fine-delay ",
+    syn_commit_id => "00000000000000000000000000000000",
+    syn_tool_name => "ISE     ",
+    syn_tool_version => x"00000147",
+    syn_date => x"20140731",
+    syn_username => "jjimenez       ");
+
+constant c_sdb_repo_url : t_sdb_repo_url :=
+  (
+    repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha-sa.git          " 
+  );
+
+constant c_sdb_synthesis_info : t_sdb_synthesis :=
+  (
+    syn_module_name => "wb-debugger     ",
+    syn_commit_id => "00000000000000000000000000000000",
+    syn_tool_name => "ISE     ",
+    syn_tool_version => x"00000147",
+    syn_date => x"20140731",
+    syn_username => "jjimenez       ");
+
+end package synthesis_descriptor;