Project description
The FMC DEL 1ns 2cha delay module will take in a TTL trigger signal and will send it out to two different outputs. Optimized for high frequency pulse repetition rates synchronized to an external clock.
TEMPLATE PLEASE UPDATE*
Top view of the FMC Delay card*
Bottom view
(prototype)
Specifications
- Full details in the Functional system specifications
Specification overview
Parameter | Value |
Channels | 1 trigger input, 4 outputs |
Signal connectors | LEMO 00 for all signals |
FMC connector | Low Pin Count (LPC) |
Signal level | TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate |
Operating modes |
Pulse delay: on trigger, generates a pulse or series of pulses of given width and repetition rate on chosen outputs after a certain time programmed by the user. Single channel TDC: time tags incoming trigger pulses available via a circular buffer. Pulse generator: produces a pulse or a series of pulses of arbitrary length and repetition rate starting at a given UTC/TAI time. |
Minimum input pulse width | 100 ns. Pulses below 24 ns are ignored. |
Maximum input pulse rate | 1 MHz (minimum pulse spacing: 1 us) |
Output pulse width | 250 ns - 1 s (10 ps resolution), 50ns - 1 s (pulse generation mode only, 4 ns resolution) |
Output pulse spacing | 250 ns - 1 s (10 ps resolution), 50ns - 1 s (pulse generation mode only, 4 ns resolution) |
Trigger to output delay | 600 ns (min) to 120 seconds (max). Independent setting for each channel. |
Output pulse repeat count (train generation) | 1 - 65536 pulses or infinity (continuous mode) |
Timebase accuracy | ± 2.5 ppm The timebase from a local TCXO on FMC card needs calibration. The 2.5 ppm accuracy is the one of the on-board TCXO. Cesium-quality accuracy will be reached when used on a White Rabbit enabled FMC carrier. |
TDC Resolution | 28 ps |
TDC Precision (std. dev) | 55 ps |
Delay accuracy | Baseline: < 300 ps average, < 1 ns peak-to-peak (minimum delay setting of 600 ns). Accuracy is as good as the time base, e.g. for a delay of 1 s using internal time base, the worst case error will be (2.5 ppm x 1 s) = 2.5 us. The accuracy can be greatly improved by locking the card to GPS/Cesium clock source through White Rabbit. |
Time tag buffer | 1024-entries circular buffer with time tags for input/output pulses. Buffer interrupt (with timeout/threshold coalescing) |
Power consumption | 7 Watt (200 mA from 12V, 1.5 A from 3V3) |
Detailed project information
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-03339
- Users
- Software
- CERN specific information
- Driver developers information
- Notes on hardware/VHDL design
- User's manual
- Long term test report
- Temperature issues and solutions
- Frequently Asked Questions
Contacts
Commercial producers
- The card is not yet commercially produced.
General question about project
- Michael Betz - CERN
Project Status
Date | Event |
04-01-2016 | Work on schematics started. |
27-01-2016 | First version of schematics ready for review. |
05-02-2016 | Layout started by CERN design office. |
08-02-2016 | Inclusion of project on OHWR. |
Michael Betz, Tom Levens - 08 February 2016