Project description
The FMC DEL 1ns 2cha delay module provides two TTL pulse-outputs with
independently adjustable delay and pulse width. Pulses are triggered by
a common TTL input with adjustable threshold.
The timing is synchronized either to an external reference clock or an
internal 125 MHz VCXO (white rabbit compatible). Delay and pulse width
can be fine-adjusted with a resolution of 10 ps.
Signal paths have been optimized for low jitter and high frequency pulse
repetition
rates.
Specifications
| Parameter | Value |
| Channels | Two independently programmable output channels sharing a clock and trigger input. |
| Signal connectors | SMA for all signals |
| FMC connector | Low Pin Count (LPC) |
| Input signal level |
Clock: 150mVpp to 2Vpp. Trigger: 5V maximum, adjustable input threshold. |
| Output signal level |
Clock: 800mVpp square wave. Output: TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate |
| Operating modes | TBC |
| Minimum input pulse width | Depends on input clock frequency |
| Maximum input pulse rate | Depends on input clock frequency |
| Output pulse width | 2ns (min) |
| Output pulse spacing | Depends on input clock frequency |
| Trigger to output delay | TBC |
| Timebase accuracy | TBC |
| Delay accuracy | TBC |
| Power consumption |
P3V3: 1.5 A P12V: 50 mA |
Detailed project information
- Schematic: EDA-03339-V1-0_sch.pdf
- Production documentation (EDMS): EDA-03339
Contacts
Commercial producers
- The card is not yet commercially produced.
General question about project
- Michael Betz - CERN
- Tom Levens - CERN
Project Status
| Date | Event |
| 04-01-2016 | Work on schematics started. |
| 27-01-2016 | First version of schematics ready for review. |
| 05-02-2016 | Layout started by CERN design office. |
| 08-02-2016 | Inclusion of project on OHWR. |
| 15-03-2016 | Layout completed. |
| 27-05-2016 | First two prototype boards received. |
| 10-08-2016 | First prototype boards under test. |
Michael Betz, Tom Levens - 09 February 2016