Project description
The FMC DEL 1ns 2cha delay module will take in a TTL trigger signal and will send it out to two different outputs. Optimized for high frequency pulse repetition rates synchronized to an external clock.
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Specifications
Parameter | Value |
Channels | Two independently programmable output channels sharing a clock and trigger input. |
Signal connectors | SMA for all signals |
FMC connector | Low Pin Count (LPC) |
Input signal level |
Clock: 150mVpp to 2Vpp. Trigger: 5V maximum, adjustable input threshold. |
Output signal level |
Clock: 800mVpp square wave. Output: TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate |
Operating modes | TBC |
Minimum input pulse width | Depends on input clock frequency |
Maximum input pulse rate | Depends on input clock frequency |
Output pulse width | <1ns (min) |
Output pulse spacing | Depends on input clock frequency |
Trigger to output delay | TBC |
Timebase accuracy | TBC |
Delay accuracy | TBC |
Power consumption | TBC |
Detailed project information
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-03339
Contacts
Commercial producers
- The card is not yet commercially produced.
General question about project
- Michael Betz - CERN
- Tom Levens - CERN
Project Status
Date | Event |
04-01-2016 | Work on schematics started. |
27-01-2016 | First version of schematics ready for review. |
05-02-2016 | Layout started by CERN design office. |
08-02-2016 | Inclusion of project on OHWR. |
Michael Betz, Tom Levens - 09 February 2016