- 05 Sep, 2016 4 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
added reset of MC100EP140 bad state; better configuration; better debugging; comments; attempt for better trigger latency calibration (not working yet) Signed-off-by:
Michael Betz <Michael.Betz@cern.ch>
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- 01 Sep, 2016 3 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 25 Aug, 2016 1 commit
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Jan Pospisil authored
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- 24 Aug, 2016 2 commits
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Jan Pospisil authored
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Jan Pospisil authored
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- 23 Aug, 2016 7 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
fixed sensitivity list; fixed ratio initial value to reflect Wishbone slave default values (always zeros)
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- 22 Aug, 2016 4 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
added automatic start-up AD9512 configuration; implemented full clock selection feature; added clock division ratio selection; removed AD9512 SPI slave; fixed FFPG simulation scripts
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Jan Pospisil authored
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- 18 Aug, 2016 9 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
removed one clock domain in top-level, now everything runs on 62.5 MHz; added few default values for simulation
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Jan Pospisil authored
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Jan Pospisil authored
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- 17 Aug, 2016 5 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 16 Aug, 2016 5 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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