FMC DEL 1ns 2cha:master commitshttps://ohwr.org/project/fmc-del-1ns-2cha/commits/master2023-02-28T09:41:41Zhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/46befee2b128328d82bef455cfc67b325d450ad4Split PCI/VME drivers2023-02-28T09:41:41ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/01d4ddcf69ec014dec7191ded5fb02271f0c1762Add constraints for SPEC LEDs2023-02-28T09:36:38ZTom Levenstom.levens@cern.ch
- Front-panel "link" and "act" LEDs are not included in the base design
constraints unless WR is enabled.
- Constraints for the "aux" LEDs are missing, see:
<a href="https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/spec/-/issues/15" rel="nofollow noreferrer noopener" target="_blank">https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/spec/-/issues/15</a>
Also switch to the "link" (green) LED for bus activity.https://ohwr.org/project/fmc-del-1ns-2cha/commit/bcde5365ee12e7abc20c0450af7dcd0d096f36e9Build for SVEC150T2023-02-27T12:10:29ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/b97eee850ca35407fe999179ea5f99c878fd5f77Remove unused ports in instantiation of base2023-02-27T06:47:51ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/995c4865839ae8f01bb7fcde6a0188f7e0f9ea7aAdd SPEC top level and synthesis2023-02-26T08:46:17ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/fc03fc634f7b05a4a25b5023257baac87e864cc8Avoid gc_sync_register ISE error2023-02-26T08:08:12ZTom Levenstom.levens@cern.ch
The SVEC base design has constraints for gc_sync_register but this is
never instantiated in this design. Therefore ISE gives an error during
synthesis.
To avoid this error I have added an extra "dummy" gc_sync_register for
synchronising the FP GPIO inputs. This can be removed once this issue
is resolved:
<a href="https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec/-/issues/25" rel="nofollow noreferrer noopener" target="_blank">https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec/-/issues/25</a>https://ohwr.org/project/fmc-del-1ns-2cha/commit/4e5cb99a86e166b97818d13a17f20d6fa084faf3Add BLT/MBLT modes to driver2023-02-24T12:42:25ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/383952d8c0ce2647008fadf213ba35d26b180023Update HISTORY.txt2023-02-24T12:13:41ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/78b5bf5dd6790a9ee1c56b99100e31a464f03523Add EDGE driver description2023-02-24T11:11:23ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/d9a08ee8e484995c976f4a78900ab869403de983Move python scripts to subdirectory2023-02-24T10:07:20ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/9464d0e8a3273d9e9649584505a815690754520aTake version from sourceid2023-02-24T09:36:10ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/a3dc2ea892b52434fe40f7218c423186497cb1b9Port to latest SVEC reference design2023-02-24T09:22:44ZTom Levenstom.levens@cern.ch
References:
<a href="https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec" rel="nofollow noreferrer noopener" target="_blank">https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec</a>
<a href="https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/wrtd-reference-designs" rel="nofollow noreferrer noopener" target="_blank">https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/wrtd-reference-designs</a>https://ohwr.org/project/fmc-del-1ns-2cha/commit/0ca74d2962abe1ece5a50b411bb5dc8d339d5573V1.4.22023-02-23T13:43:06ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/f33b2d1c46ea180724a0a0ba44cd4c2ad4d8985aRename Fsm.vhd -> DelayedPulseGeneratorFsm.vhd2023-02-23T13:42:40ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/f7b7c9a0c278cf204819be3318b41235df1f1477Update FSM2023-02-23T13:37:14ZTom Levenstom.levens@cern.ch
Ensure transition to stop state only happens at end of sequence and that
start only happens when stopped.https://ohwr.org/project/fmc-del-1ns-2cha/commit/e502f50406ed9af1551b56eb44a35a23a3dd3702V1.4.1 to test build chain2023-02-20T16:39:51ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/2d7c18d917122b6cd488eb3494d8b8aa34efb106Rename readme.txt to README.txt2023-02-19T11:19:02ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/c06f91c89ab7e8a9c92eaaa8cf260c906454bfe1Normalise formatting2023-02-19T09:33:00ZTom Levenstom.levens@cern.ch
- Convert tabs to spaces
- Convert DOS line endings to Unix
- Clean whitespace at end of lineshttps://ohwr.org/project/fmc-del-1ns-2cha/commit/852214cf01696970b374d2f1bb18a8b10df820e3Update submodule paths2023-02-19T08:42:20ZTom Levenstom.levens@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/857483c0281167e71ce2567b1fba6cde0831a47dadded test script; reformatted Ffpg class (added comments)2017-09-14T13:40:55ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/6e97c2da651bd712816324a4f670617817878ad8added new CLI command for driver initialization - has to be called once at th...2017-05-02T13:39:08ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/da4ee7c9601f995e3fd1676ce67db08c99ef7ca9added non-zero word highlight in memory printing function hexDump2017-05-02T13:38:14ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/058fb484a0e5e1235c2a137e3731fad4e4ae3537new version 1.42017-04-10T14:51:31ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/a474761b36cf2630b56e71d07b2f3d9ef809c3e7reverted test stuff2017-04-10T13:40:15ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/8781787ee4c589165e3c3ddbfaec6b1001905577added option for better UVM debug2017-04-10T13:38:25ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/1ca03bbf26c898ba3d35343232ea8eee138eb7b1added AD9512 synchronization pulse to the simulation2017-04-10T13:37:51ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/28f3b2fe9b39354ece8ddbe61a0ed20e3ee8a931fixed X values at the beginning of the simulation2017-04-10T13:37:23ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/62381b860010e489ae1f9f350b4d80bca4477870comments, typos2017-04-10T13:37:01ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/a814058b0193e8f64a1389973c9a12c8974b5e6ctypo2017-04-06T14:19:25ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/df896ba948547db42bec88d7e934908227bedd56fixed DelayController logic and port naming (LEN port for delay chips)2017-04-06T13:39:58ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/6f3130c2d9704ec0fbe9d87ca5586ec55f2e9109fixed naming style; better test synchronization to the clock2017-04-06T13:38:43ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/835859a945dfa66cff4e36c9d162624829a3340efixed rounding problem2017-04-06T13:38:08ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/decd2b2204296dcf05858a24a07d1333399e4dbdadded few words about how to test the board2017-04-04T15:59:11ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/c2bf9a5fa6e002a8527b17a029e470afc97ddcf0clean-up after tests2017-04-04T14:53:44ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/fbb43e6974fcc1eb1c7c6cff22a47adb2edb0558swapped LEMO output to fit FMC position (top row of LEMOs correspond to top F...2017-04-04T14:53:18ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/52f577fb7f65478028db52ea51875633b93bdf70added AD9512 SPI mux (between automatic configuration and WB access)2017-04-04T14:34:20ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/42357774fac6ece7a7b6fb4f2cbc543db1dc6ce6moved AD9512 Config/Check methods to proper class2017-04-04T14:14:28ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/5a5ceb58d6cd113441c34146724a5d2f0f761e29typo2017-04-04T14:13:07ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/0e45f7f22b320d3a3b16f30f8edfbbd6d499c14freformatted for better folding support2017-04-04T13:55:48ZJan Pospisilj.pospisil@cern.chhttps://ohwr.org/project/fmc-del-1ns-2cha/commit/3db419eb25fd1f1943768deb4fce5033b9edb6b5fixed pulseGenerator for cases when g_PulseMinWidth==12017-04-04T12:47:40ZJan Pospisilj.pospisil@cern.ch