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FMC DEL 1ns 2cha
Commit f1b0308f authored by Jan Pospisil's avatar Jan Pospisil
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added AD9512 synchronization feature (instead of AD9512 reset)

parent 548e07d3
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Showing with 51 additions and 17 deletions
hdl/ffpg/rtl/FfpgCore.vhd
View file @ f1b0308f
-- TODO:
-- ! clock dividers synchronization
-- - automatic clock infrastructure configuration
-- ? clock selection
-- ? clock divider
......@@ -27,7 +26,7 @@ entity FfpgCore is
Wb_o: out t_wishbone_slave_out;
--- FMC interface
-- clock
ClkIn0_ik: in std_logic;
ClkIn0_ik: in std_logic; -- 1 MHz <= f_ClkIn0_ik <= 204 MHz
-- DACs
TriggerDac_o: out t_Ad5600Interface;
VcxoDac_o: out t_Ad5600Interface;
......
hdl/ffpg/rtl/FfpgSlave.vhd
View file @ f1b0308f
......@@ -69,6 +69,8 @@ architecture syn of FfpgSlave is
signal LedSignal_b: std_logic_vector(4 downto 1);
signal Ad9512SyncePulse: std_logic;
begin
ClkRf_k <= ClkIn0_ik;
......@@ -234,7 +236,7 @@ begin
)
port map (
Clk_ik => Clk_ik,
Reset_ir => '0',
Reset_ir => Reset_ir,
Test_i => WbRegsOutput.control_led_test_o,
Signal_ib => LedSignal_b,
Signal_ob => Led_ob
......@@ -243,7 +245,23 @@ begin
----------------------------------
-- Pulse generator board clocks
----------------------------------
Ad9512Func_o <= not WbRegsOutput.control_ad9512_reset_o;
-- Ad9512Func_o is set as SYNCB - need negative pulse > 1.5*T_rfClk
-- (f_rfClk >= 1 MHz) => (1.5*T_rfClk <= 1.5 us)
cAd9512SyncPulseGenerator: entity work.PulseGeneratorTime(syn)
generic map (
g_ClkFrequency => g_ClkFrequency,
g_PulseMinWidthInTime => 2 us
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Signal_i => WbRegsOutput.control_ad9512_sync_o,
Pulse_o => Ad9512SyncePulse
);
Ad9512Func_o <= not Ad9512SyncePulse;
ClkOut_ok <= Clk_ik;
----------------------------------
......
hdl/ffpg/rtl/pulseGeneratorTime.vhd
View file @ f1b0308f
......@@ -5,7 +5,7 @@ use ieee.numeric_std.all;
entity PulseGeneratorTime is
generic (
g_ClkFrequency: positive; -- input clock frequency in Hz
g_PulseMinWidthInTime: time -- minimal pulse width in [s]
g_PulseMinWidthInTime: time -- minimal pulse width
);
port (
Clk_ik: in std_logic;
......
hdl/ffpg/wb_gen/ffpg_csr.wb
View file @ f1b0308f
......@@ -154,11 +154,10 @@ peripheral {
};
field {
name = "AD9512 Reset";
prefix = "ad9512_reset";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
name = "AD9512 Synchronization";
description = "When written with 1 AD9512 dividers synchronization is performed. It automatically clear to 0.";
prefix = "ad9512_sync";
type = MONOSTABLE;
};
};
......
hdl/svec/sim/testbench/Testbench.sv
View file @ f1b0308f
......@@ -210,6 +210,7 @@ module Testbench;
endtask
initial begin
uint32_t data;
acc = new(VME);
#10us; // for PLL lock and reset settle
......@@ -219,7 +220,11 @@ module Testbench;
// TestSdb;
// TestFfpgCsr;
// TestSpi;
TestReal;
// TestReal;
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 'h200);
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
#2us
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
// uint64_t blt_addr[];
......
hdl/svec/syn/SvecFfpg.ucf
View file @ f1b0308f
......@@ -662,7 +662,7 @@ TIMESPEC TS_clk_20m_vcxo_i = PERIOD "Clk20_ik" 50 ns HIGH 50%;
# RF clock
NET "Fmc0ClkIn0P_ik" TNM_NET = Fmc0ClkIn0P_ik;
TIMESPEC TS_Fmc0ClkIn0P_ik = PERIOD "Fmc0ClkIn0P_ik" 5 ns HIGH 50%;
TIMESPEC TS_Fmc0ClkIn0P_ik = PERIOD "Fmc0ClkIn0P_ik" 4.97 ns HIGH 50%;
#===============================================================================
# False Path
......
hdl/svec/syn/SvecFfpg.xise
View file @ f1b0308f
......@@ -100,7 +100,7 @@
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
......@@ -131,7 +131,7 @@
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
......
readme.txt
View file @ f1b0308f
Requirements
============
1 MHz <= f_ClkIn0_ik <= 204 MHz
Implementation
==============
1) Git - make sure submodules are updated
2) make Wishbone slaves:
......
sw/FFPG_driver.py
View file @ f1b0308f
......@@ -59,7 +59,9 @@ def WbWrite(register, data):
WB_DEBUG_2_SV_FP.write('WbWrite('+str(address)+', '+str(data)+', "WB_WRITE: '+register+':");\n')
m.write(register, (data,))
def WbSetBits(register, mask, bits):
def WbSetBits(register, mask, bits = -1):
if bits == -1:
bits = mask
value = WbRead(register)
value &= (~mask)
value |= (bits & mask)
......@@ -173,6 +175,9 @@ def Ad9512Init():
SpiWrite(0x58, 0x20)
# confirm write
SpiWrite(0x5a, 1)
# synchronize dividers
WbSetBits('control', 0x200)
# 0 - front panel clock
# 1 - FPGA loop clock
......@@ -334,7 +339,7 @@ def Control():
PrintBits(control, 4, 5, 'Channel 1 mode', ('stopped', 'continuous', 'one-shot'))
PrintBits(control, 6, 7, 'Channel 2 mode', ('stopped', 'continuous', 'one-shot'))
PrintBit(control, 8, 'LEDs', 'blinking', 'normal operation')
PrintBit(control, 9, 'AD9512', 'in reset', 'running')
PrintBit(control, 9, 'AD9512 Synchronization', 'in progress', 'done')
def Enable(channel):
channel -= 1
......@@ -371,7 +376,7 @@ def Debug():
PrintBits(debug, 3, 5, "CH2 FSM state", ("Stop", "WaitForTrigger", "Generating", "Outputting"))
###################################################################
## OneWire stuff
## OneWire stuff - not working yet
###################################################################
OW_CMD_ROM_SEARCH = 0xF0
......
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