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F
FMC DEL 1ns 2cha
Commit b21ab4a0 authored by Jan Pospisil's avatar Jan Pospisil
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added wbgen2 generated files

parent 521618bf
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.gitignore
View file @ b21ab4a0
/doc/manual/ffpg_csr.tex
/doc/manual/svec/carrier_csr.tex
/hdl/*/wb_gen/*.h
/hdl/*/sim/testbench/work/*
/hdl/*/sim/testbench/tr_db.log
/hdl/*/sim/testbench/transcript
......@@ -8,10 +5,4 @@
/hdl/*/sim/testbench/vsim.wlf
/hdl/*/sim/testbench/wlf*
/hdl/*/sim/testbench/*.vstf
/hdl/ffpg/rtl/ffpg_csr.vhd
/hdl/ffpg/rtl/ffpg_csr_pkg.vhd
/hdl/ffpg/sim/testbench/ffpg_csr.svh
/hdl/svec/syn
/hdl/svec/rtl/carrier_csr.vhd
/hdl/svec/sim/testbench/carrier_csr.svh
doc/manual/ffpg_csr.htm
View file @ b21ab4a0
......@@ -3,27 +3,26 @@
<TITLE>ffpg_csr</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
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.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
.td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
<!--
BODY { background: white; color: black; font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
.td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
.td_code { font-family:Courier New,Courier; padding: 3px; }
.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
.td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
......@@ -2579,38 +2578,47 @@ CLOCK_INFRASTRUCTURE_BUSY
</table>
<ul>
<li><b>
[0]
CLOCK_INFRASTRUCTURE_BUSY
</b>[<i>read-only</i>]: Clock infrastructure configuration in progress
<br>Status of the clock infrastructure configuration<br>0: configuration done<br>1: configuration in progress
<li><b>
[1]
DAC_VCXO_BUSY
</b>[<i>read-only</i>]: VCXO DAC busy
<br>Status of the VCXO DAC communication<br>0: DAC idle, value already set<br>1: DAC busy, communication in progress
<li><b>
[2]
DAC_TRIGGER_BUSY
</b>[<i>read-only</i>]: Trigger DAC busy
<br>Status of the trigger DAC communication<br>0: DAC idle, value already set<br>1: DAC busy, communication in progress
<li><b>
[3]
DELAY_CONFIGURATION_BUSY
</b>[<i>read-only</i>]: Delay configuration in progress
<br>Status of the delay configuration<br>0: configuration done<br>1: configuration in progress
<li><b>
[4]
CHANNEL_1_OE
</b>[<i>read-only</i>]: Channel 1 output enabled
<br>Channel 1 output enabled<br>0: output disabled<br>1: output enabled
<li><b>
[5]
CHANNEL_2_OE
</b>[<i>read-only</i>]: Channel 2 output enabled
<br>Channel 2 output enabled<br>0: output disabled<br>1: output enabled
<li><b>
[6]
CHANNEL_1_RUNNING
</b>[<i>read-only</i>]: Pulse generator channel 1 running
<br>Pulse generator channel 1 running<br>0: channel 1 is not running<br>1: channel 1 is running, pulses are generated
<li><b>
[7]
CHANNEL_2_RUNNING
</b>[<i>read-only</i>]: Pulse generator channel 2 running
<br>Pulse generator channel 2 running<br>0: channel 2 is not running<br>1: channel 2 is running, pulses are generated
<li><b>
[8]
INPUT_CLOCK_STABLE
</b>[<i>read-only</i>]: Input clock stable
<br>Indicates the stability of the input clock.<br>0: input clock not present or not stable<br>1: input clock present and stable
......@@ -2869,32 +2877,40 @@ CLOCK_SELECTION[1:0]
</table>
<ul>
<li><b>
[2:0]
CLOCK_SELECTION
</b>[<i>read/write</i>]: Clock source selection
<br>0 (default): external clock used (connector on the front panel)<br>1: FPGA loop clock used<br>2: on-board VCXO clock used
<li><b>
[2]
CH1_OE
</b>[<i>read/write</i>]: CH1 output enable
<li><b>
[3]
CH2_OE
</b>[<i>read/write</i>]: CH2 output enable
<li><b>
[6:4]
CH1_MODE
</b>[<i>read/write</i>]: CH1 mode selection
<br>0 (default): stopped (no output generated)<br>1: continuous (non-stop memory looping)<br>2: one-shot (loop memory just once)
<li><b>
[8:6]
CH2_MODE
</b>[<i>read/write</i>]: CH2 mode selection
<br>0 (default): stopped (no output generated)<br>1: continuous (non-stop memory looping)<br>2: one-shot (loop memory just once)
<li><b>
[8]
LED_TEST
</b>[<i>read/write</i>]: LED test
<br>If set to 1, all LEDs on the FFPG front panel will be blinking.
<li><b>
[9]
AD9512_SYNC
</b>[<i>write-only</i>]: AD9512 Synchronization
<br>When written with 1 AD9512 dividers synchronization is performed. It automatically clear to 0.
<li><b>
[10]
FINE_DELAY_ENABLE
</b>[<i>read/write</i>]: AD9512 OUT4 fine delay enable
<br>If set to 1, fine delay on OUT4 output of AD9512 is enabled. Fine delay itself can be set in a separate register.
......@@ -3156,6 +3172,7 @@ VCXO_VOLTAGE[7:0]
</table>
<ul>
<li><b>
[16:0]
VCXO_VOLTAGE
</b>[<i>read/write</i>]: VCXO voltage register value
</ul>
......@@ -3416,6 +3433,7 @@ CLOCK_RATIO_M1[4:0]
</table>
<ul>
<li><b>
[5:0]
CLOCK_RATIO_M1
</b>[<i>read/write</i>]: Clock ratio-1
</ul>
......@@ -3676,6 +3694,7 @@ CH1_DELAY_SET[7:0]
</table>
<ul>
<li><b>
[10:0]
CH1_DELAY_SET
</b>[<i>read/write</i>]: CH1 SET delay
</ul>
......@@ -3936,6 +3955,7 @@ CH1_DELAY_RESET[7:0]
</table>
<ul>
<li><b>
[10:0]
CH1_DELAY_RESET
</b>[<i>read/write</i>]: CH1 RES delay
</ul>
......@@ -4196,6 +4216,7 @@ CH2_DELAY_SET[7:0]
</table>
<ul>
<li><b>
[10:0]
CH2_DELAY_SET
</b>[<i>read/write</i>]: CH2 SET delay
</ul>
......@@ -4456,6 +4477,7 @@ CH2_DELAY_RESET[7:0]
</table>
<ul>
<li><b>
[10:0]
CH2_DELAY_RESET
</b>[<i>read/write</i>]: CH2 RES delay
</ul>
......@@ -4716,6 +4738,7 @@ TRIGGER_THRESHOLD[7:0]
</table>
<ul>
<li><b>
[16:0]
TRIGGER_THRESHOLD
</b>[<i>read/write</i>]: Trigger threshold voltage register value
</ul>
......@@ -4976,6 +4999,7 @@ OVERFLOW[7:0]
</table>
<ul>
<li><b>
[16:0]
OVERFLOW
</b>[<i>read/write</i>]: Overflow value
</ul>
......@@ -5236,6 +5260,7 @@ CH1_TRIGGER_LATENCY[7:0]
</table>
<ul>
<li><b>
[16:0]
CH1_TRIGGER_LATENCY
</b>[<i>read/write</i>]: Trigger latency value
</ul>
......@@ -5496,6 +5521,7 @@ FREQUENCY[7:0]
</table>
<ul>
<li><b>
[32:0]
FREQUENCY
</b>[<i>read-only</i>]: Clock frequency value
</ul>
......@@ -5756,6 +5782,7 @@ DEBUG[7:0]
</table>
<ul>
<li><b>
[32:0]
DEBUG
</b>[<i>read-only</i>]: Debug field
</ul>
......@@ -6016,12 +6043,15 @@ REVISION[7:0]
</table>
<ul>
<li><b>
[12:0]
REVISION
</b>[<i>read-only</i>]: Revision
<li><b>
[22:12]
MINOR
</b>[<i>read-only</i>]: Minor version
<li><b>
[32:22]
MAJOR
</b>[<i>read-only</i>]: Major version
</ul>
......@@ -6282,6 +6312,7 @@ CH2_TRIGGER_LATENCY[7:0]
</table>
<ul>
<li><b>
[16:0]
CH2_TRIGGER_LATENCY
</b>[<i>read/write</i>]: Trigger latency value
</ul>
......@@ -6542,12 +6573,15 @@ VALUE[4:0]
</table>
<ul>
<li><b>
[5:0]
VALUE
</b>[<i>read/write</i>]: AD9512 OUT4 fine delay value
<li><b>
[8:5]
CURRENT
</b>[<i>read/write</i>]: Ramp current
<li><b>
[11:8]
CAPACITORS
</b>[<i>read/write</i>]: Ramp capacitors
</ul>
......
doc/manual/svec/carrier_csr.htm
View file @ b21ab4a0
......@@ -3,27 +3,26 @@
<TITLE>carrier_csr</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
.td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
.td_code { font-family:Courier New,Courier; padding: 3px; }
.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
.td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
<!--
BODY { background: white; color: black; font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
.td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
.td_code { font-family:Courier New,Courier; padding: 3px; }
.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
.td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
......@@ -760,14 +759,17 @@ PCB_REV[4:0]
</table>
<ul>
<li><b>
[5:0]
PCB_REV
</b>[<i>read-only</i>]: PCB revision
<br>Binary coded PCB layout revision.
<li><b>
[16:5]
RESERVED
</b>[<i>read-only</i>]: Reserved register
<br>Ignore on read, write with 0's.
<li><b>
[32:16]
TYPE
</b>[<i>read-only</i>]: Carrier type
<br>Carrier type identifier<br>1 = SPEC<br>2 = SVEC<br>3 = VFC<br>4 = SPEXI
......@@ -1026,22 +1028,27 @@ FMC0_PRES
</table>
<ul>
<li><b>
[0]
FMC0_PRES
</b>[<i>read-only</i>]: FMC 1 presence
<br>0: FMC slot 1 is populated<br>1: FMC slot 1 is not populated.
<li><b>
[1]
FMC1_PRES
</b>[<i>read-only</i>]: FMC 2 presence
<br>0: FMC slot 2 is populated<br>1: FMC slot 2 is not populated.
<li><b>
[2]
SYS_PLL_LCK
</b>[<i>read-only</i>]: System clock PLL status
<br>0: not locked<br>1: locked.
<li><b>
[3]
DDR0_CAL_DONE
</b>[<i>read-only</i>]: NOT_IMPLEMENTED: DDR3 bank 4 calibration status
<br>0: not done<br>1: done.
<li><b>
[4]
DDR1_CAL_DONE
</b>[<i>read-only</i>]: NOT_IMPLEMENTED: DDR3 bank 5 calibration status
<br>0: not done<br>1: done.
......@@ -1300,6 +1307,7 @@ FP_LEDS_MAN[7:0]
</table>
<ul>
<li><b>
[16:0]
FP_LEDS_MAN
</b>[<i>read/write</i>]: NOT_IMPLEMENTED: Front panel LED manual control
<br>NOT_IMPLEMENTED: Height front panel LED, two bits per LED.<br>00 = OFF<br>01 = Green<br>10 = Red<br>11 = Orange
......@@ -1561,10 +1569,12 @@ FMC0_N
</table>
<ul>
<li><b>
[0]
FMC0_N
</b>[<i>read/write</i>]: State of the FMC 1 reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
<li><b>
[1]
FMC1_N
</b>[<i>read/write</i>]: State of the FMC 2 reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
......
hdl/ffpg/rtl/ffpg_csr.vhd 0 → 100644
View file @ b21ab4a0
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC DEL 1ns 2cha core registers
---------------------------------------------------------------------------------------
-- File : ../rtl/ffpg_csr.vhd
-- Author : auto-generated by wbgen2 from ffpg_csr.wb
-- Created : 12/19/16 17:04:33
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ffpg_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.ffpg_wbgen2_pkg.all;
entity ffpg_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(13 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_rf_ik : in std_logic;
-- Ports for RAM: CH1 SET serial stream
ffpg_ch1_set_mem_addr_i : in std_logic_vector(10 downto 0);
-- Read data output
ffpg_ch1_set_mem_data_o : out std_logic_vector(31 downto 0);
-- Read strobe input (active high)
ffpg_ch1_set_mem_rd_i : in std_logic;
-- Ports for RAM: CH1 RES serial stream
ffpg_ch1_res_mem_addr_i : in std_logic_vector(10 downto 0);
-- Read data output
ffpg_ch1_res_mem_data_o : out std_logic_vector(31 downto 0);
-- Read strobe input (active high)
ffpg_ch1_res_mem_rd_i : in std_logic;
-- Ports for RAM: CH2 SET serial stream
ffpg_ch2_set_mem_addr_i : in std_logic_vector(10 downto 0);
-- Read data output
ffpg_ch2_set_mem_data_o : out std_logic_vector(31 downto 0);
-- Read strobe input (active high)
ffpg_ch2_set_mem_rd_i : in std_logic;
-- Ports for RAM: CH2 RES serial stream
ffpg_ch2_res_mem_addr_i : in std_logic_vector(10 downto 0);
-- Read data output
ffpg_ch2_res_mem_data_o : out std_logic_vector(31 downto 0);
-- Read strobe input (active high)
ffpg_ch2_res_mem_rd_i : in std_logic;
regs_i : in t_ffpg_in_registers;
regs_o : out t_ffpg_out_registers
);
end ffpg_csr;
architecture syn of ffpg_csr is
signal ffpg_control_clock_selection_int : std_logic_vector(1 downto 0);
signal ffpg_control_ch1_oe_int : std_logic;
signal ffpg_control_ch2_oe_int : std_logic;
signal ffpg_control_ch1_mode_int : std_logic_vector(1 downto 0);
signal ffpg_control_ch2_mode_int : std_logic_vector(1 downto 0);
signal ffpg_control_led_test_int : std_logic;
signal ffpg_control_ad9512_sync_dly0 : std_logic;
signal ffpg_control_ad9512_sync_int : std_logic;
signal ffpg_control_fine_delay_enable_int : std_logic;
signal ffpg_ch1_set_mem_rddata_int : std_logic_vector(31 downto 0);
signal ffpg_ch1_set_mem_rd_int : std_logic;
signal ffpg_ch1_set_mem_wr_int : std_logic;
signal ffpg_ch1_res_mem_rddata_int : std_logic_vector(31 downto 0);
signal ffpg_ch1_res_mem_rd_int : std_logic;
signal ffpg_ch1_res_mem_wr_int : std_logic;
signal ffpg_ch2_set_mem_rddata_int : std_logic_vector(31 downto 0);
signal ffpg_ch2_set_mem_rd_int : std_logic;
signal ffpg_ch2_set_mem_wr_int : std_logic;
signal ffpg_ch2_res_mem_rddata_int : std_logic_vector(31 downto 0);
signal ffpg_ch2_res_mem_rd_int : std_logic;
signal ffpg_ch2_res_mem_wr_int : std_logic;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(13 downto 0);
signal ack_in_progress : std_logic;
signal wr_int : std_logic;
signal rd_int : std_logic;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
ffpg_control_clock_selection_int <= "00";
ffpg_control_ch1_oe_int <= '0';
ffpg_control_ch2_oe_int <= '0';
ffpg_control_ch1_mode_int <= "00";
ffpg_control_ch2_mode_int <= "00";
ffpg_control_led_test_int <= '0';
ffpg_control_ad9512_sync_int <= '0';
ffpg_control_fine_delay_enable_int <= '0';
regs_o.vcxo_voltage_load_o <= '0';
regs_o.clock_ratio_m1_load_o <= '0';
regs_o.ch1_delay_set_load_o <= '0';
regs_o.ch1_delay_reset_load_o <= '0';
regs_o.ch2_delay_set_load_o <= '0';
regs_o.ch2_delay_reset_load_o <= '0';
regs_o.trigger_threshold_load_o <= '0';
regs_o.overflow_load_o <= '0';
regs_o.ch1_trigger_latency_load_o <= '0';
regs_o.ch2_trigger_latency_load_o <= '0';
regs_o.fine_delay_value_load_o <= '0';
regs_o.fine_delay_current_load_o <= '0';
regs_o.fine_delay_capacitors_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ffpg_control_ad9512_sync_int <= '0';
regs_o.vcxo_voltage_load_o <= '0';
regs_o.clock_ratio_m1_load_o <= '0';
regs_o.ch1_delay_set_load_o <= '0';
regs_o.ch1_delay_reset_load_o <= '0';
regs_o.ch2_delay_set_load_o <= '0';
regs_o.ch2_delay_reset_load_o <= '0';
regs_o.trigger_threshold_load_o <= '0';
regs_o.overflow_load_o <= '0';
regs_o.ch1_trigger_latency_load_o <= '0';
regs_o.ch2_trigger_latency_load_o <= '0';
regs_o.fine_delay_value_load_o <= '0';
regs_o.fine_delay_current_load_o <= '0';
regs_o.fine_delay_capacitors_load_o <= '0';
ack_in_progress <= '0';
else
regs_o.vcxo_voltage_load_o <= '0';
regs_o.clock_ratio_m1_load_o <= '0';
regs_o.ch1_delay_set_load_o <= '0';
regs_o.ch1_delay_reset_load_o <= '0';
regs_o.ch2_delay_set_load_o <= '0';
regs_o.ch2_delay_reset_load_o <= '0';
regs_o.trigger_threshold_load_o <= '0';
regs_o.overflow_load_o <= '0';
regs_o.ch1_trigger_latency_load_o <= '0';
regs_o.ch2_trigger_latency_load_o <= '0';
regs_o.fine_delay_value_load_o <= '0';
regs_o.fine_delay_current_load_o <= '0';
regs_o.fine_delay_capacitors_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(13 downto 11) is
when "000" =>
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.status_clock_infrastructure_busy_i;
rddata_reg(1) <= regs_i.status_dac_vcxo_busy_i;
rddata_reg(2) <= regs_i.status_dac_trigger_busy_i;
rddata_reg(3) <= regs_i.status_delay_configuration_busy_i;
rddata_reg(4) <= regs_i.status_channel_1_oe_i;
rddata_reg(5) <= regs_i.status_channel_2_oe_i;
rddata_reg(6) <= regs_i.status_channel_1_running_i;
rddata_reg(7) <= regs_i.status_channel_2_running_i;
rddata_reg(8) <= regs_i.status_input_clock_stable_i;
rddata_reg(31 downto 9) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
ffpg_control_clock_selection_int <= wrdata_reg(1 downto 0);
ffpg_control_ch1_oe_int <= wrdata_reg(2);
ffpg_control_ch2_oe_int <= wrdata_reg(3);
ffpg_control_ch1_mode_int <= wrdata_reg(5 downto 4);
ffpg_control_ch2_mode_int <= wrdata_reg(7 downto 6);
ffpg_control_led_test_int <= wrdata_reg(8);
ffpg_control_ad9512_sync_int <= wrdata_reg(9);
ffpg_control_fine_delay_enable_int <= wrdata_reg(10);
end if;
rddata_reg(1 downto 0) <= ffpg_control_clock_selection_int;
rddata_reg(2) <= ffpg_control_ch1_oe_int;
rddata_reg(3) <= ffpg_control_ch2_oe_int;
rddata_reg(5 downto 4) <= ffpg_control_ch1_mode_int;
rddata_reg(7 downto 6) <= ffpg_control_ch2_mode_int;
rddata_reg(8) <= ffpg_control_led_test_int;
rddata_reg(9) <= '0';
rddata_reg(10) <= ffpg_control_fine_delay_enable_int;
rddata_reg(31 downto 11) <= (others => 'X');
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
regs_o.vcxo_voltage_load_o <= '1';
end if;
rddata_reg(15 downto 0) <= std_logic_vector(regs_i.vcxo_voltage_i);
rddata_reg(31 downto 16) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
regs_o.clock_ratio_m1_load_o <= '1';
end if;
rddata_reg(4 downto 0) <= std_logic_vector(regs_i.clock_ratio_m1_i);
rddata_reg(31 downto 5) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
regs_o.ch1_delay_set_load_o <= '1';
end if;
rddata_reg(9 downto 0) <= std_logic_vector(regs_i.ch1_delay_set_i);
rddata_reg(31 downto 10) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
regs_o.ch1_delay_reset_load_o <= '1';
end if;
rddata_reg(9 downto 0) <= std_logic_vector(regs_i.ch1_delay_reset_i);
rddata_reg(31 downto 10) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
regs_o.ch2_delay_set_load_o <= '1';
end if;
rddata_reg(9 downto 0) <= std_logic_vector(regs_i.ch2_delay_set_i);
rddata_reg(31 downto 10) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
regs_o.ch2_delay_reset_load_o <= '1';
end if;
rddata_reg(9 downto 0) <= std_logic_vector(regs_i.ch2_delay_reset_i);
rddata_reg(31 downto 10) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
regs_o.trigger_threshold_load_o <= '1';
end if;
rddata_reg(15 downto 0) <= std_logic_vector(regs_i.trigger_threshold_i);
rddata_reg(31 downto 16) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
regs_o.overflow_load_o <= '1';
end if;
rddata_reg(15 downto 0) <= std_logic_vector(regs_i.overflow_i);
rddata_reg(31 downto 16) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
regs_o.ch1_trigger_latency_load_o <= '1';
end if;
rddata_reg(15 downto 0) <= std_logic_vector(regs_i.ch1_trigger_latency_i);
rddata_reg(31 downto 16) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= std_logic_vector(regs_i.frequency_i);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= std_logic_vector(regs_i.debug_i);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(11 downto 0) <= std_logic_vector(regs_i.version_revision_i);
rddata_reg(21 downto 12) <= std_logic_vector(regs_i.version_minor_i);
rddata_reg(31 downto 22) <= std_logic_vector(regs_i.version_major_i);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1110" =>
if (wb_we_i = '1') then
regs_o.ch2_trigger_latency_load_o <= '1';
end if;
rddata_reg(15 downto 0) <= std_logic_vector(regs_i.ch2_trigger_latency_i);
rddata_reg(31 downto 16) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1111" =>
if (wb_we_i = '1') then
regs_o.fine_delay_value_load_o <= '1';
regs_o.fine_delay_current_load_o <= '1';
regs_o.fine_delay_capacitors_load_o <= '1';
end if;
rddata_reg(4 downto 0) <= std_logic_vector(regs_i.fine_delay_value_i);
rddata_reg(7 downto 5) <= std_logic_vector(regs_i.fine_delay_current_i);
rddata_reg(10 downto 8) <= std_logic_vector(regs_i.fine_delay_capacitors_i);
rddata_reg(31 downto 11) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
when "001" =>
if (rd_int = '1') then
ack_sreg(0) <= '1';
else
ack_sreg(0) <= '1';
end if;
ack_in_progress <= '1';
when "010" =>
if (rd_int = '1') then
ack_sreg(0) <= '1';
else
ack_sreg(0) <= '1';
end if;
ack_in_progress <= '1';
when "011" =>
if (rd_int = '1') then
ack_sreg(0) <= '1';
else
ack_sreg(0) <= '1';
end if;
ack_in_progress <= '1';
when "100" =>
if (rd_int = '1') then
ack_sreg(0) <= '1';
else
ack_sreg(0) <= '1';
end if;
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Data output multiplexer process
process (rddata_reg, rwaddr_reg, ffpg_ch1_set_mem_rddata_int, ffpg_ch1_res_mem_rddata_int, ffpg_ch2_set_mem_rddata_int, ffpg_ch2_res_mem_rddata_int, wb_adr_i )
begin
case rwaddr_reg(13 downto 11) is
when "001" =>
wb_dat_o(31 downto 0) <= ffpg_ch1_set_mem_rddata_int;
when "010" =>
wb_dat_o(31 downto 0) <= ffpg_ch1_res_mem_rddata_int;
when "011" =>
wb_dat_o(31 downto 0) <= ffpg_ch2_set_mem_rddata_int;
when "100" =>
wb_dat_o(31 downto 0) <= ffpg_ch2_res_mem_rddata_int;
when others =>
wb_dat_o <= rddata_reg;
end case;
end process;
-- Read & write lines decoder for RAMs
process (wb_adr_i, rd_int, wr_int )
begin
if (wb_adr_i(13 downto 11) = "001") then
ffpg_ch1_set_mem_rd_int <= rd_int;
ffpg_ch1_set_mem_wr_int <= wr_int;
else
ffpg_ch1_set_mem_wr_int <= '0';
ffpg_ch1_set_mem_rd_int <= '0';
end if;
if (wb_adr_i(13 downto 11) = "010") then
ffpg_ch1_res_mem_rd_int <= rd_int;
ffpg_ch1_res_mem_wr_int <= wr_int;
else
ffpg_ch1_res_mem_wr_int <= '0';
ffpg_ch1_res_mem_rd_int <= '0';
end if;
if (wb_adr_i(13 downto 11) = "011") then
ffpg_ch2_set_mem_rd_int <= rd_int;
ffpg_ch2_set_mem_wr_int <= wr_int;
else
ffpg_ch2_set_mem_wr_int <= '0';
ffpg_ch2_set_mem_rd_int <= '0';
end if;
if (wb_adr_i(13 downto 11) = "100") then
ffpg_ch2_res_mem_rd_int <= rd_int;
ffpg_ch2_res_mem_wr_int <= wr_int;
else
ffpg_ch2_res_mem_wr_int <= '0';
ffpg_ch2_res_mem_rd_int <= '0';
end if;
end process;
-- Clock source selection
regs_o.control_clock_selection_o <= ffpg_control_clock_selection_int;
-- CH1 output enable
regs_o.control_ch1_oe_o <= ffpg_control_ch1_oe_int;
-- CH2 output enable
regs_o.control_ch2_oe_o <= ffpg_control_ch2_oe_int;
-- CH1 mode selection
regs_o.control_ch1_mode_o <= ffpg_control_ch1_mode_int;
-- CH2 mode selection
regs_o.control_ch2_mode_o <= ffpg_control_ch2_mode_int;
-- LED test
regs_o.control_led_test_o <= ffpg_control_led_test_int;
-- AD9512 Synchronization
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ffpg_control_ad9512_sync_dly0 <= '0';
regs_o.control_ad9512_sync_o <= '0';
elsif rising_edge(clk_sys_i) then
ffpg_control_ad9512_sync_dly0 <= ffpg_control_ad9512_sync_int;
regs_o.control_ad9512_sync_o <= ffpg_control_ad9512_sync_int and (not ffpg_control_ad9512_sync_dly0);
end if;
end process;
-- AD9512 OUT4 fine delay enable
regs_o.control_fine_delay_enable_o <= ffpg_control_fine_delay_enable_int;
-- VCXO voltage register value
regs_o.vcxo_voltage_o <= unsigned(wrdata_reg(15 downto 0));
-- Clock ratio-1
regs_o.clock_ratio_m1_o <= unsigned(wrdata_reg(4 downto 0));
-- CH1 SET delay
regs_o.ch1_delay_set_o <= unsigned(wrdata_reg(9 downto 0));
-- CH1 RES delay
regs_o.ch1_delay_reset_o <= unsigned(wrdata_reg(9 downto 0));
-- CH2 SET delay
regs_o.ch2_delay_set_o <= unsigned(wrdata_reg(9 downto 0));
-- CH2 RES delay
regs_o.ch2_delay_reset_o <= unsigned(wrdata_reg(9 downto 0));
-- Trigger threshold voltage register value
regs_o.trigger_threshold_o <= unsigned(wrdata_reg(15 downto 0));
-- Overflow value
regs_o.overflow_o <= unsigned(wrdata_reg(15 downto 0));
-- Trigger latency value
regs_o.ch1_trigger_latency_o <= unsigned(wrdata_reg(15 downto 0));
-- Trigger latency value
regs_o.ch2_trigger_latency_o <= unsigned(wrdata_reg(15 downto 0));
-- AD9512 OUT4 fine delay value
regs_o.fine_delay_value_o <= unsigned(wrdata_reg(4 downto 0));
-- Ramp current
regs_o.fine_delay_current_o <= unsigned(wrdata_reg(7 downto 5));
-- Ramp capacitors
regs_o.fine_delay_capacitors_o <= unsigned(wrdata_reg(10 downto 8));
-- extra code for reg/fifo/mem: CH1 SET serial stream
-- RAM block instantiation for memory: CH1 SET serial stream
ffpg_ch1_set_mem_raminst : wbgen2_dpssram
generic map (
g_data_width => 32,
g_size => 2048,
g_addr_width => 11,
g_dual_clock => true,
g_use_bwsel => false
)
port map (
clk_a_i => clk_sys_i,
clk_b_i => clk_rf_ik,
addr_b_i => ffpg_ch1_set_mem_addr_i,
addr_a_i => rwaddr_reg(10 downto 0),
data_b_o => ffpg_ch1_set_mem_data_o,
rd_b_i => ffpg_ch1_set_mem_rd_i,
bwsel_b_i => allones(3 downto 0),
data_b_i => allzeros(31 downto 0),
wr_b_i => allzeros(0),
data_a_o => ffpg_ch1_set_mem_rddata_int(31 downto 0),
rd_a_i => ffpg_ch1_set_mem_rd_int,
data_a_i => wrdata_reg(31 downto 0),
wr_a_i => ffpg_ch1_set_mem_wr_int,
bwsel_a_i => allones(3 downto 0)
);
-- extra code for reg/fifo/mem: CH1 RES serial stream
-- RAM block instantiation for memory: CH1 RES serial stream
ffpg_ch1_res_mem_raminst : wbgen2_dpssram
generic map (
g_data_width => 32,
g_size => 2048,
g_addr_width => 11,
g_dual_clock => true,
g_use_bwsel => false
)
port map (
clk_a_i => clk_sys_i,
clk_b_i => clk_rf_ik,
addr_b_i => ffpg_ch1_res_mem_addr_i,
addr_a_i => rwaddr_reg(10 downto 0),
data_b_o => ffpg_ch1_res_mem_data_o,
rd_b_i => ffpg_ch1_res_mem_rd_i,
bwsel_b_i => allones(3 downto 0),
data_b_i => allzeros(31 downto 0),
wr_b_i => allzeros(0),
data_a_o => ffpg_ch1_res_mem_rddata_int(31 downto 0),
rd_a_i => ffpg_ch1_res_mem_rd_int,
data_a_i => wrdata_reg(31 downto 0),
wr_a_i => ffpg_ch1_res_mem_wr_int,
bwsel_a_i => allones(3 downto 0)
);
-- extra code for reg/fifo/mem: CH2 SET serial stream
-- RAM block instantiation for memory: CH2 SET serial stream
ffpg_ch2_set_mem_raminst : wbgen2_dpssram
generic map (
g_data_width => 32,
g_size => 2048,
g_addr_width => 11,
g_dual_clock => true,
g_use_bwsel => false
)
port map (
clk_a_i => clk_sys_i,
clk_b_i => clk_rf_ik,
addr_b_i => ffpg_ch2_set_mem_addr_i,
addr_a_i => rwaddr_reg(10 downto 0),
data_b_o => ffpg_ch2_set_mem_data_o,
rd_b_i => ffpg_ch2_set_mem_rd_i,
bwsel_b_i => allones(3 downto 0),
data_b_i => allzeros(31 downto 0),
wr_b_i => allzeros(0),
data_a_o => ffpg_ch2_set_mem_rddata_int(31 downto 0),
rd_a_i => ffpg_ch2_set_mem_rd_int,
data_a_i => wrdata_reg(31 downto 0),
wr_a_i => ffpg_ch2_set_mem_wr_int,
bwsel_a_i => allones(3 downto 0)
);
-- extra code for reg/fifo/mem: CH2 RES serial stream
-- RAM block instantiation for memory: CH2 RES serial stream
ffpg_ch2_res_mem_raminst : wbgen2_dpssram
generic map (
g_data_width => 32,
g_size => 2048,
g_addr_width => 11,
g_dual_clock => true,
g_use_bwsel => false
)
port map (
clk_a_i => clk_sys_i,
clk_b_i => clk_rf_ik,
addr_b_i => ffpg_ch2_res_mem_addr_i,
addr_a_i => rwaddr_reg(10 downto 0),
data_b_o => ffpg_ch2_res_mem_data_o,
rd_b_i => ffpg_ch2_res_mem_rd_i,
bwsel_b_i => allones(3 downto 0),
data_b_i => allzeros(31 downto 0),
wr_b_i => allzeros(0),
data_a_o => ffpg_ch2_res_mem_rddata_int(31 downto 0),
rd_a_i => ffpg_ch2_res_mem_rd_int,
data_a_i => wrdata_reg(31 downto 0),
wr_a_i => ffpg_ch2_res_mem_wr_int,
bwsel_a_i => allones(3 downto 0)
);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (ack_in_progress or (wb_stb_i and wb_cyc_i));
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/ffpg/rtl/ffpg_csr_pkg.vhd 0 → 100644
View file @ b21ab4a0
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC DEL 1ns 2cha core registers
---------------------------------------------------------------------------------------
-- File : ../rtl/ffpg_csr_pkg.vhd
-- Author : auto-generated by wbgen2 from ffpg_csr.wb
-- Created : 12/19/16 17:04:33
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ffpg_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package ffpg_wbgen2_pkg is
-- Constants
constant c_ffpg_address_width: natural := 14;
-- Input registers (user design -> WB slave)
type t_ffpg_in_registers is record
status_clock_infrastructure_busy_i : std_logic;
status_dac_vcxo_busy_i : std_logic;
status_dac_trigger_busy_i : std_logic;
status_delay_configuration_busy_i : std_logic;
status_channel_1_oe_i : std_logic;
status_channel_2_oe_i : std_logic;
status_channel_1_running_i : std_logic;
status_channel_2_running_i : std_logic;
status_input_clock_stable_i : std_logic;
vcxo_voltage_i : unsigned(15 downto 0);
clock_ratio_m1_i : unsigned(4 downto 0);
ch1_delay_set_i : unsigned(9 downto 0);
ch1_delay_reset_i : unsigned(9 downto 0);
ch2_delay_set_i : unsigned(9 downto 0);
ch2_delay_reset_i : unsigned(9 downto 0);
trigger_threshold_i : unsigned(15 downto 0);
overflow_i : unsigned(15 downto 0);
ch1_trigger_latency_i : unsigned(15 downto 0);
frequency_i : unsigned(31 downto 0);
debug_i : unsigned(31 downto 0);
version_revision_i : unsigned(11 downto 0);
version_minor_i : unsigned(9 downto 0);
version_major_i : unsigned(9 downto 0);
ch2_trigger_latency_i : unsigned(15 downto 0);
fine_delay_value_i : unsigned(4 downto 0);
fine_delay_current_i : unsigned(2 downto 0);
fine_delay_capacitors_i : unsigned(2 downto 0);
end record;
constant c_ffpg_in_registers_init_value: t_ffpg_in_registers := (
status_clock_infrastructure_busy_i => '0',
status_dac_vcxo_busy_i => '0',
status_dac_trigger_busy_i => '0',
status_delay_configuration_busy_i => '0',
status_channel_1_oe_i => '0',
status_channel_2_oe_i => '0',
status_channel_1_running_i => '0',
status_channel_2_running_i => '0',
status_input_clock_stable_i => '0',
vcxo_voltage_i => (others => '0'),
clock_ratio_m1_i => (others => '0'),
ch1_delay_set_i => (others => '0'),
ch1_delay_reset_i => (others => '0'),
ch2_delay_set_i => (others => '0'),
ch2_delay_reset_i => (others => '0'),
trigger_threshold_i => (others => '0'),
overflow_i => (others => '0'),
ch1_trigger_latency_i => (others => '0'),
frequency_i => (others => '0'),
debug_i => (others => '0'),
version_revision_i => (others => '0'),
version_minor_i => (others => '0'),
version_major_i => (others => '0'),
ch2_trigger_latency_i => (others => '0'),
fine_delay_value_i => (others => '0'),
fine_delay_current_i => (others => '0'),
fine_delay_capacitors_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_ffpg_out_registers is record
control_clock_selection_o : std_logic_vector(1 downto 0);
control_ch1_oe_o : std_logic;
control_ch2_oe_o : std_logic;
control_ch1_mode_o : std_logic_vector(1 downto 0);
control_ch2_mode_o : std_logic_vector(1 downto 0);
control_led_test_o : std_logic;
control_ad9512_sync_o : std_logic;
control_fine_delay_enable_o : std_logic;
vcxo_voltage_o : unsigned(15 downto 0);
vcxo_voltage_load_o : std_logic;
clock_ratio_m1_o : unsigned(4 downto 0);
clock_ratio_m1_load_o : std_logic;
ch1_delay_set_o : unsigned(9 downto 0);
ch1_delay_set_load_o : std_logic;
ch1_delay_reset_o : unsigned(9 downto 0);
ch1_delay_reset_load_o : std_logic;
ch2_delay_set_o : unsigned(9 downto 0);
ch2_delay_set_load_o : std_logic;
ch2_delay_reset_o : unsigned(9 downto 0);
ch2_delay_reset_load_o : std_logic;
trigger_threshold_o : unsigned(15 downto 0);
trigger_threshold_load_o : std_logic;
overflow_o : unsigned(15 downto 0);
overflow_load_o : std_logic;
ch1_trigger_latency_o : unsigned(15 downto 0);
ch1_trigger_latency_load_o : std_logic;
ch2_trigger_latency_o : unsigned(15 downto 0);
ch2_trigger_latency_load_o : std_logic;
fine_delay_value_o : unsigned(4 downto 0);
fine_delay_value_load_o : std_logic;
fine_delay_current_o : unsigned(2 downto 0);
fine_delay_current_load_o : std_logic;
fine_delay_capacitors_o : unsigned(2 downto 0);
fine_delay_capacitors_load_o : std_logic;
end record;
constant c_ffpg_out_registers_init_value: t_ffpg_out_registers := (
control_clock_selection_o => (others => '0'),
control_ch1_oe_o => '0',
control_ch2_oe_o => '0',
control_ch1_mode_o => (others => '0'),
control_ch2_mode_o => (others => '0'),
control_led_test_o => '0',
control_ad9512_sync_o => '0',
control_fine_delay_enable_o => '0',
vcxo_voltage_o => (others => '0'),
vcxo_voltage_load_o => '0',
clock_ratio_m1_o => (others => '0'),
clock_ratio_m1_load_o => '0',
ch1_delay_set_o => (others => '0'),
ch1_delay_set_load_o => '0',
ch1_delay_reset_o => (others => '0'),
ch1_delay_reset_load_o => '0',
ch2_delay_set_o => (others => '0'),
ch2_delay_set_load_o => '0',
ch2_delay_reset_o => (others => '0'),
ch2_delay_reset_load_o => '0',
trigger_threshold_o => (others => '0'),
trigger_threshold_load_o => '0',
overflow_o => (others => '0'),
overflow_load_o => '0',
ch1_trigger_latency_o => (others => '0'),
ch1_trigger_latency_load_o => '0',
ch2_trigger_latency_o => (others => '0'),
ch2_trigger_latency_load_o => '0',
fine_delay_value_o => (others => '0'),
fine_delay_value_load_o => '0',
fine_delay_current_o => (others => '0'),
fine_delay_current_load_o => '0',
fine_delay_capacitors_o => (others => '0'),
fine_delay_capacitors_load_o => '0'
);
-- functions
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
function f_x_to_zero (x:signed) return signed;
function f_x_to_zero (x:unsigned) return unsigned;
function "or" (left, right: t_ffpg_in_registers) return t_ffpg_in_registers;
end package;
package body ffpg_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function f_x_to_zero (x:signed) return signed is
begin
return signed(f_x_to_zero(std_logic_vector(x)));
end function;
function f_x_to_zero (x:unsigned) return unsigned is
begin
return unsigned(f_x_to_zero(std_logic_vector(x)));
end function;
function "or" (left, right: t_ffpg_in_registers) return t_ffpg_in_registers is
variable tmp: t_ffpg_in_registers;
begin
tmp.status_clock_infrastructure_busy_i := f_x_to_zero(left.status_clock_infrastructure_busy_i) or f_x_to_zero(right.status_clock_infrastructure_busy_i);
tmp.status_dac_vcxo_busy_i := f_x_to_zero(left.status_dac_vcxo_busy_i) or f_x_to_zero(right.status_dac_vcxo_busy_i);
tmp.status_dac_trigger_busy_i := f_x_to_zero(left.status_dac_trigger_busy_i) or f_x_to_zero(right.status_dac_trigger_busy_i);
tmp.status_delay_configuration_busy_i := f_x_to_zero(left.status_delay_configuration_busy_i) or f_x_to_zero(right.status_delay_configuration_busy_i);
tmp.status_channel_1_oe_i := f_x_to_zero(left.status_channel_1_oe_i) or f_x_to_zero(right.status_channel_1_oe_i);
tmp.status_channel_2_oe_i := f_x_to_zero(left.status_channel_2_oe_i) or f_x_to_zero(right.status_channel_2_oe_i);
tmp.status_channel_1_running_i := f_x_to_zero(left.status_channel_1_running_i) or f_x_to_zero(right.status_channel_1_running_i);
tmp.status_channel_2_running_i := f_x_to_zero(left.status_channel_2_running_i) or f_x_to_zero(right.status_channel_2_running_i);
tmp.status_input_clock_stable_i := f_x_to_zero(left.status_input_clock_stable_i) or f_x_to_zero(right.status_input_clock_stable_i);
tmp.vcxo_voltage_i := f_x_to_zero(left.vcxo_voltage_i) or f_x_to_zero(right.vcxo_voltage_i);
tmp.clock_ratio_m1_i := f_x_to_zero(left.clock_ratio_m1_i) or f_x_to_zero(right.clock_ratio_m1_i);
tmp.ch1_delay_set_i := f_x_to_zero(left.ch1_delay_set_i) or f_x_to_zero(right.ch1_delay_set_i);
tmp.ch1_delay_reset_i := f_x_to_zero(left.ch1_delay_reset_i) or f_x_to_zero(right.ch1_delay_reset_i);
tmp.ch2_delay_set_i := f_x_to_zero(left.ch2_delay_set_i) or f_x_to_zero(right.ch2_delay_set_i);
tmp.ch2_delay_reset_i := f_x_to_zero(left.ch2_delay_reset_i) or f_x_to_zero(right.ch2_delay_reset_i);
tmp.trigger_threshold_i := f_x_to_zero(left.trigger_threshold_i) or f_x_to_zero(right.trigger_threshold_i);
tmp.overflow_i := f_x_to_zero(left.overflow_i) or f_x_to_zero(right.overflow_i);
tmp.ch1_trigger_latency_i := f_x_to_zero(left.ch1_trigger_latency_i) or f_x_to_zero(right.ch1_trigger_latency_i);
tmp.frequency_i := f_x_to_zero(left.frequency_i) or f_x_to_zero(right.frequency_i);
tmp.debug_i := f_x_to_zero(left.debug_i) or f_x_to_zero(right.debug_i);
tmp.version_revision_i := f_x_to_zero(left.version_revision_i) or f_x_to_zero(right.version_revision_i);
tmp.version_minor_i := f_x_to_zero(left.version_minor_i) or f_x_to_zero(right.version_minor_i);
tmp.version_major_i := f_x_to_zero(left.version_major_i) or f_x_to_zero(right.version_major_i);
tmp.ch2_trigger_latency_i := f_x_to_zero(left.ch2_trigger_latency_i) or f_x_to_zero(right.ch2_trigger_latency_i);
tmp.fine_delay_value_i := f_x_to_zero(left.fine_delay_value_i) or f_x_to_zero(right.fine_delay_value_i);
tmp.fine_delay_current_i := f_x_to_zero(left.fine_delay_current_i) or f_x_to_zero(right.fine_delay_current_i);
tmp.fine_delay_capacitors_i := f_x_to_zero(left.fine_delay_capacitors_i) or f_x_to_zero(right.fine_delay_capacitors_i);
return tmp;
end function;
end package body;
hdl/ffpg/sim/testbench/ffpg_csr.svh 0 → 100644
View file @ b21ab4a0
`define ADDR_FFPG_STATUS 16'h0
`define FFPG_STATUS_CLOCK_INFRASTRUCTURE_BUSY_OFFSET 0
`define FFPG_STATUS_CLOCK_INFRASTRUCTURE_BUSY 32'h00000001
`define FFPG_STATUS_DAC_VCXO_BUSY_OFFSET 1
`define FFPG_STATUS_DAC_VCXO_BUSY 32'h00000002
`define FFPG_STATUS_DAC_TRIGGER_BUSY_OFFSET 2
`define FFPG_STATUS_DAC_TRIGGER_BUSY 32'h00000004
`define FFPG_STATUS_DELAY_CONFIGURATION_BUSY_OFFSET 3
`define FFPG_STATUS_DELAY_CONFIGURATION_BUSY 32'h00000008
`define FFPG_STATUS_CHANNEL_1_OE_OFFSET 4
`define FFPG_STATUS_CHANNEL_1_OE 32'h00000010
`define FFPG_STATUS_CHANNEL_2_OE_OFFSET 5
`define FFPG_STATUS_CHANNEL_2_OE 32'h00000020
`define FFPG_STATUS_CHANNEL_1_RUNNING_OFFSET 6
`define FFPG_STATUS_CHANNEL_1_RUNNING 32'h00000040
`define FFPG_STATUS_CHANNEL_2_RUNNING_OFFSET 7
`define FFPG_STATUS_CHANNEL_2_RUNNING 32'h00000080
`define FFPG_STATUS_INPUT_CLOCK_STABLE_OFFSET 8
`define FFPG_STATUS_INPUT_CLOCK_STABLE 32'h00000100
`define ADDR_FFPG_CONTROL 16'h4
`define FFPG_CONTROL_CLOCK_SELECTION_OFFSET 0
`define FFPG_CONTROL_CLOCK_SELECTION 32'h00000003
`define FFPG_CONTROL_CH1_OE_OFFSET 2
`define FFPG_CONTROL_CH1_OE 32'h00000004
`define FFPG_CONTROL_CH2_OE_OFFSET 3
`define FFPG_CONTROL_CH2_OE 32'h00000008
`define FFPG_CONTROL_CH1_MODE_OFFSET 4
`define FFPG_CONTROL_CH1_MODE 32'h00000030
`define FFPG_CONTROL_CH2_MODE_OFFSET 6
`define FFPG_CONTROL_CH2_MODE 32'h000000c0
`define FFPG_CONTROL_LED_TEST_OFFSET 8
`define FFPG_CONTROL_LED_TEST 32'h00000100
`define FFPG_CONTROL_AD9512_SYNC_OFFSET 9
`define FFPG_CONTROL_AD9512_SYNC 32'h00000200
`define FFPG_CONTROL_FINE_DELAY_ENABLE_OFFSET 10
`define FFPG_CONTROL_FINE_DELAY_ENABLE 32'h00000400
`define ADDR_FFPG_VCXO_VOLTAGE 16'h8
`define ADDR_FFPG_CLOCK_RATIO_M1 16'hc
`define ADDR_FFPG_CH1_DELAY_SET 16'h10
`define ADDR_FFPG_CH1_DELAY_RESET 16'h14
`define ADDR_FFPG_CH2_DELAY_SET 16'h18
`define ADDR_FFPG_CH2_DELAY_RESET 16'h1c
`define ADDR_FFPG_TRIGGER_THRESHOLD 16'h20
`define ADDR_FFPG_OVERFLOW 16'h24
`define ADDR_FFPG_CH1_TRIGGER_LATENCY 16'h28
`define ADDR_FFPG_FREQUENCY 16'h2c
`define ADDR_FFPG_DEBUG 16'h30
`define ADDR_FFPG_VERSION 16'h34
`define FFPG_VERSION_REVISION_OFFSET 0
`define FFPG_VERSION_REVISION 32'h00000fff
`define FFPG_VERSION_MINOR_OFFSET 12
`define FFPG_VERSION_MINOR 32'h003ff000
`define FFPG_VERSION_MAJOR_OFFSET 22
`define FFPG_VERSION_MAJOR 32'hffc00000
`define ADDR_FFPG_CH2_TRIGGER_LATENCY 16'h38
`define ADDR_FFPG_FINE_DELAY 16'h3c
`define FFPG_FINE_DELAY_VALUE_OFFSET 0
`define FFPG_FINE_DELAY_VALUE 32'h0000001f
`define FFPG_FINE_DELAY_CURRENT_OFFSET 5
`define FFPG_FINE_DELAY_CURRENT 32'h000000e0
`define FFPG_FINE_DELAY_CAPACITORS_OFFSET 8
`define FFPG_FINE_DELAY_CAPACITORS 32'h00000700
`define BASE_FFPG_CH1_SET_MEM 16'h2000
`define SIZE_FFPG_CH1_SET_MEM 32'h800
`define BASE_FFPG_CH1_RES_MEM 16'h4000
`define SIZE_FFPG_CH1_RES_MEM 32'h800
`define BASE_FFPG_CH2_SET_MEM 16'h6000
`define SIZE_FFPG_CH2_SET_MEM 32'h800
`define BASE_FFPG_CH2_RES_MEM 16'h8000
`define SIZE_FFPG_CH2_RES_MEM 32'h800
hdl/ffpg/wb_gen/Makefile
View file @ b21ab4a0
......@@ -5,4 +5,3 @@ SIM=../sim/testbench/
%:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_pkg.vhd -f html -D $(DOC)$@.htm -C $@.h -K $(SIM)$@.svh $@.wb
$(WBGEN2) -f texinfo -D $(DOC)$@.tex $@.wb
\ No newline at end of file
hdl/ffpg/wb_gen/ffpg_csr.h 0 → 100644
View file @ b21ab4a0
/*
Register definitions for slave core: FMC DEL 1ns 2cha core registers
* File : ffpg_csr.h
* Author : auto-generated by wbgen2 from ffpg_csr.wb
* Created : 12/19/16 17:04:33
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ffpg_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_FFPG_CSR_WB
#define __WBGEN2_REGDEFS_FFPG_CSR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1ULL<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status register */
/* definitions for field: Clock infrastructure configuration in progress in reg: Status register */
#define FFPG_STATUS_CLOCK_INFRASTRUCTURE_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: VCXO DAC busy in reg: Status register */
#define FFPG_STATUS_DAC_VCXO_BUSY WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Trigger DAC busy in reg: Status register */
#define FFPG_STATUS_DAC_TRIGGER_BUSY WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Delay configuration in progress in reg: Status register */
#define FFPG_STATUS_DELAY_CONFIGURATION_BUSY WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Channel 1 output enabled in reg: Status register */
#define FFPG_STATUS_CHANNEL_1_OE WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel 2 output enabled in reg: Status register */
#define FFPG_STATUS_CHANNEL_2_OE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Pulse generator channel 1 running in reg: Status register */
#define FFPG_STATUS_CHANNEL_1_RUNNING WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Pulse generator channel 2 running in reg: Status register */
#define FFPG_STATUS_CHANNEL_2_RUNNING WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Input clock stable in reg: Status register */
#define FFPG_STATUS_INPUT_CLOCK_STABLE WBGEN2_GEN_MASK(8, 1)
/* definitions for register: Control register */
/* definitions for field: Clock source selection in reg: Control register */
#define FFPG_CONTROL_CLOCK_SELECTION_MASK WBGEN2_GEN_MASK(0, 2)
#define FFPG_CONTROL_CLOCK_SELECTION_SHIFT 0
#define FFPG_CONTROL_CLOCK_SELECTION_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FFPG_CONTROL_CLOCK_SELECTION_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: CH1 output enable in reg: Control register */
#define FFPG_CONTROL_CH1_OE WBGEN2_GEN_MASK(2, 1)
/* definitions for field: CH2 output enable in reg: Control register */
#define FFPG_CONTROL_CH2_OE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: CH1 mode selection in reg: Control register */
#define FFPG_CONTROL_CH1_MODE_MASK WBGEN2_GEN_MASK(4, 2)
#define FFPG_CONTROL_CH1_MODE_SHIFT 4
#define FFPG_CONTROL_CH1_MODE_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define FFPG_CONTROL_CH1_MODE_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: CH2 mode selection in reg: Control register */
#define FFPG_CONTROL_CH2_MODE_MASK WBGEN2_GEN_MASK(6, 2)
#define FFPG_CONTROL_CH2_MODE_SHIFT 6
#define FFPG_CONTROL_CH2_MODE_W(value) WBGEN2_GEN_WRITE(value, 6, 2)
#define FFPG_CONTROL_CH2_MODE_R(reg) WBGEN2_GEN_READ(reg, 6, 2)
/* definitions for field: LED test in reg: Control register */
#define FFPG_CONTROL_LED_TEST WBGEN2_GEN_MASK(8, 1)
/* definitions for field: AD9512 Synchronization in reg: Control register */
#define FFPG_CONTROL_AD9512_SYNC WBGEN2_GEN_MASK(9, 1)
/* definitions for field: AD9512 OUT4 fine delay enable in reg: Control register */
#define FFPG_CONTROL_FINE_DELAY_ENABLE WBGEN2_GEN_MASK(10, 1)
/* definitions for register: VCXO voltage register */
/* definitions for register: Clock ratio-1 register */
/* definitions for register: SET delay configuration (channel 1) */
/* definitions for register: RES delay configuration (channel 1) */
/* definitions for register: SET delay configuration (channel 2) */
/* definitions for register: RES delay configuration (channel 2) */
/* definitions for register: Trigger threshold voltage register */
/* definitions for register: Overflow */
/* definitions for register: Trigger latency (channel 1) */
/* definitions for register: Clock frequency */
/* definitions for register: Debug register */
/* definitions for register: Gateware version */
/* definitions for field: Revision in reg: Gateware version */
#define FFPG_VERSION_REVISION_MASK WBGEN2_GEN_MASK(0, 12)
#define FFPG_VERSION_REVISION_SHIFT 0
#define FFPG_VERSION_REVISION_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define FFPG_VERSION_REVISION_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Minor version in reg: Gateware version */
#define FFPG_VERSION_MINOR_MASK WBGEN2_GEN_MASK(12, 10)
#define FFPG_VERSION_MINOR_SHIFT 12
#define FFPG_VERSION_MINOR_W(value) WBGEN2_GEN_WRITE(value, 12, 10)
#define FFPG_VERSION_MINOR_R(reg) WBGEN2_GEN_READ(reg, 12, 10)
/* definitions for field: Major version in reg: Gateware version */
#define FFPG_VERSION_MAJOR_MASK WBGEN2_GEN_MASK(22, 10)
#define FFPG_VERSION_MAJOR_SHIFT 22
#define FFPG_VERSION_MAJOR_W(value) WBGEN2_GEN_WRITE(value, 22, 10)
#define FFPG_VERSION_MAJOR_R(reg) WBGEN2_GEN_READ(reg, 22, 10)
/* definitions for register: Trigger latency (channel 2) */
/* definitions for register: AD9512 OUT4 fine delay */
/* definitions for field: AD9512 OUT4 fine delay value in reg: AD9512 OUT4 fine delay */
#define FFPG_FINE_DELAY_VALUE_MASK WBGEN2_GEN_MASK(0, 5)
#define FFPG_FINE_DELAY_VALUE_SHIFT 0
#define FFPG_FINE_DELAY_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define FFPG_FINE_DELAY_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Ramp current in reg: AD9512 OUT4 fine delay */
#define FFPG_FINE_DELAY_CURRENT_MASK WBGEN2_GEN_MASK(5, 3)
#define FFPG_FINE_DELAY_CURRENT_SHIFT 5
#define FFPG_FINE_DELAY_CURRENT_W(value) WBGEN2_GEN_WRITE(value, 5, 3)
#define FFPG_FINE_DELAY_CURRENT_R(reg) WBGEN2_GEN_READ(reg, 5, 3)
/* definitions for field: Ramp capacitors in reg: AD9512 OUT4 fine delay */
#define FFPG_FINE_DELAY_CAPACITORS_MASK WBGEN2_GEN_MASK(8, 3)
#define FFPG_FINE_DELAY_CAPACITORS_SHIFT 8
#define FFPG_FINE_DELAY_CAPACITORS_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define FFPG_FINE_DELAY_CAPACITORS_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for RAM: CH1 SET serial stream */
#define FFPG_CH1_SET_MEM_BASE 0x00002000 /* base address */
#define FFPG_CH1_SET_MEM_BYTES 0x00002000 /* size in bytes */
#define FFPG_CH1_SET_MEM_WORDS 0x00000800 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: CH1 RES serial stream */
#define FFPG_CH1_RES_MEM_BASE 0x00004000 /* base address */
#define FFPG_CH1_RES_MEM_BYTES 0x00002000 /* size in bytes */
#define FFPG_CH1_RES_MEM_WORDS 0x00000800 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: CH2 SET serial stream */
#define FFPG_CH2_SET_MEM_BASE 0x00006000 /* base address */
#define FFPG_CH2_SET_MEM_BYTES 0x00002000 /* size in bytes */
#define FFPG_CH2_SET_MEM_WORDS 0x00000800 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: CH2 RES serial stream */
#define FFPG_CH2_RES_MEM_BASE 0x00008000 /* base address */
#define FFPG_CH2_RES_MEM_BYTES 0x00002000 /* size in bytes */
#define FFPG_CH2_RES_MEM_WORDS 0x00000800 /* size in 32-bit words, 32-bit aligned */
PACKED struct FFPG_WB {
/* [0x0]: REG Status register */
uint32_t STATUS;
/* [0x4]: REG Control register */
uint32_t CONTROL;
/* [0x8]: REG VCXO voltage register */
uint32_t VCXO_VOLTAGE;
/* [0xc]: REG Clock ratio-1 register */
uint32_t CLOCK_RATIO_M1;
/* [0x10]: REG SET delay configuration (channel 1) */
uint32_t CH1_DELAY_SET;
/* [0x14]: REG RES delay configuration (channel 1) */
uint32_t CH1_DELAY_RESET;
/* [0x18]: REG SET delay configuration (channel 2) */
uint32_t CH2_DELAY_SET;
/* [0x1c]: REG RES delay configuration (channel 2) */
uint32_t CH2_DELAY_RESET;
/* [0x20]: REG Trigger threshold voltage register */
uint32_t TRIGGER_THRESHOLD;
/* [0x24]: REG Overflow */
uint32_t OVERFLOW;
/* [0x28]: REG Trigger latency (channel 1) */
uint32_t CH1_TRIGGER_LATENCY;
/* [0x2c]: REG Clock frequency */
uint32_t FREQUENCY;
/* [0x30]: REG Debug register */
uint32_t DEBUG;
/* [0x34]: REG Gateware version */
uint32_t VERSION;
/* [0x38]: REG Trigger latency (channel 2) */
uint32_t CH2_TRIGGER_LATENCY;
/* [0x3c]: REG AD9512 OUT4 fine delay */
uint32_t FINE_DELAY;
/* padding to: 2048 words */
uint32_t __padding_0[2032];
/* [0x2000 - 0x3fff]: RAM CH1 SET serial stream, 2048 32-bit words, 32-bit aligned, word-addressable */
uint32_t CH1_SET_MEM [2048];
/* padding to: 4096 words */
uint32_t __padding_1[2048];
/* [0x4000 - 0x5fff]: RAM CH1 RES serial stream, 2048 32-bit words, 32-bit aligned, word-addressable */
uint32_t CH1_RES_MEM [2048];
/* padding to: 6144 words */
uint32_t __padding_2[2048];
/* [0x6000 - 0x7fff]: RAM CH2 SET serial stream, 2048 32-bit words, 32-bit aligned, word-addressable */
uint32_t CH2_SET_MEM [2048];
/* padding to: 8192 words */
uint32_t __padding_3[2048];
/* [0x8000 - 0x9fff]: RAM CH2 RES serial stream, 2048 32-bit words, 32-bit aligned, word-addressable */
uint32_t CH2_RES_MEM [2048];
};
#define FFPG_PERIPH_PREFIX "ffpg"
#define FFPG_PERIPH_NAME "FMC DEL 1ns 2cha core registers"
#define FFPG_PERIPH_DESC WBGEN2_DESC("Wishbone slave for FMC DEL 1ns 2cha core")
#endif
hdl/svec/rtl/carrier_csr.vhd 0 → 100644
View file @ b21ab4a0
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for SVEC carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : 12/19/16 17:04:37
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_reserved_i : in std_logic_vector(10 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC 1 presence' in reg: 'Status'
carrier_csr_stat_fmc0_pres_i : in std_logic;
-- Port for BIT field: 'FMC 2 presence' in reg: 'Status'
carrier_csr_stat_fmc1_pres_i : in std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
carrier_csr_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'NOT_IMPLEMENTED: DDR3 bank 4 calibration status' in reg: 'Status'
carrier_csr_stat_ddr0_cal_done_i : in std_logic;
-- Port for BIT field: 'NOT_IMPLEMENTED: DDR3 bank 5 calibration status' in reg: 'Status'
carrier_csr_stat_ddr1_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'NOT_IMPLEMENTED: Front panel LED manual control' in reg: 'Control'
carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0);
-- Ports for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
-- Ports for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc1_n_o : out std_logic;
carrier_csr_rst_fmc1_n_i : in std_logic;
carrier_csr_rst_fmc1_n_load_o : out std_logic
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic;
signal wr_int : std_logic;
signal rd_int : std_logic;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 5) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= carrier_csr_stat_fmc0_pres_i;
rddata_reg(1) <= carrier_csr_stat_fmc1_pres_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr0_cal_done_i;
rddata_reg(4) <= carrier_csr_stat_ddr1_cal_done_i;
rddata_reg(31 downto 5) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int;
rddata_reg(31 downto 16) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_fmc1_n_load_o <= '1';
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(1) <= carrier_csr_rst_fmc1_n_i;
rddata_reg(31 downto 2) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- NOT_IMPLEMENTED: Front panel LED manual control
carrier_csr_ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
-- State of the FMC 1 reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
-- State of the FMC 2 reset line
carrier_csr_rst_fmc1_n_o <= wrdata_reg(1);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (ack_in_progress or (wb_stb_i and wb_cyc_i));
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/svec/sim/testbench/carrier_csr.svh 0 → 100644
View file @ b21ab4a0
`define ADDR_CARRIER_CSR_CARRIER 4'h0
`define CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
`define CARRIER_CSR_CARRIER_PCB_REV 32'h0000001f
`define CARRIER_CSR_CARRIER_RESERVED_OFFSET 5
`define CARRIER_CSR_CARRIER_RESERVED 32'h0000ffe0
`define CARRIER_CSR_CARRIER_TYPE_OFFSET 16
`define CARRIER_CSR_CARRIER_TYPE 32'hffff0000
`define ADDR_CARRIER_CSR_STAT 4'h4
`define CARRIER_CSR_STAT_FMC0_PRES_OFFSET 0
`define CARRIER_CSR_STAT_FMC0_PRES 32'h00000001
`define CARRIER_CSR_STAT_FMC1_PRES_OFFSET 1
`define CARRIER_CSR_STAT_FMC1_PRES 32'h00000002
`define CARRIER_CSR_STAT_SYS_PLL_LCK_OFFSET 2
`define CARRIER_CSR_STAT_SYS_PLL_LCK 32'h00000004
`define CARRIER_CSR_STAT_DDR0_CAL_DONE_OFFSET 3
`define CARRIER_CSR_STAT_DDR0_CAL_DONE 32'h00000008
`define CARRIER_CSR_STAT_DDR1_CAL_DONE_OFFSET 4
`define CARRIER_CSR_STAT_DDR1_CAL_DONE 32'h00000010
`define ADDR_CARRIER_CSR_CTRL 4'h8
`define CARRIER_CSR_CTRL_FP_LEDS_MAN_OFFSET 0
`define CARRIER_CSR_CTRL_FP_LEDS_MAN 32'h0000ffff
`define ADDR_CARRIER_CSR_RST 4'hc
`define CARRIER_CSR_RST_FMC0_N_OFFSET 0
`define CARRIER_CSR_RST_FMC0_N 32'h00000001
`define CARRIER_CSR_RST_FMC1_N_OFFSET 1
`define CARRIER_CSR_RST_FMC1_N 32'h00000002
hdl/svec/wb_gen/Makefile
View file @ b21ab4a0
......@@ -5,4 +5,3 @@ SIM=../sim/testbench/
%:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $(DOC)$@.htm -C $@.h -K $(SIM)$@.svh $@.wb
$(WBGEN2) -f texinfo -D $(DOC)$@.tex $@.wb
hdl/svec/wb_gen/carrier_csr.h 0 → 100644
View file @ b21ab4a0
/*
Register definitions for slave core: SVEC carrier control and status registers
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : 12/19/16 17:04:37
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_CARRIER_CSR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1ULL<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Carrier type and PCB version */
/* definitions for field: PCB revision in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_PCB_REV_MASK WBGEN2_GEN_MASK(0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define CARRIER_CSR_CARRIER_PCB_REV_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reserved register in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_RESERVED_MASK WBGEN2_GEN_MASK(5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_SHIFT 5
#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 11)
/* definitions for field: Carrier type in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_TYPE_MASK WBGEN2_GEN_MASK(16, 16)
#define CARRIER_CSR_CARRIER_TYPE_SHIFT 16
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Status */
/* definitions for field: FMC 1 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC0_PRES WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC 2 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC1_PRES WBGEN2_GEN_MASK(1, 1)
/* definitions for field: System clock PLL status in reg: Status */
#define CARRIER_CSR_STAT_SYS_PLL_LCK WBGEN2_GEN_MASK(2, 1)
/* definitions for field: NOT_IMPLEMENTED: DDR3 bank 4 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR0_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: NOT_IMPLEMENTED: DDR3 bank 5 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR1_CAL_DONE WBGEN2_GEN_MASK(4, 1)
/* definitions for register: Control */
/* definitions for field: NOT_IMPLEMENTED: Front panel LED manual control in reg: Control */
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_MASK WBGEN2_GEN_MASK(0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_SHIFT 0
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1)
/* definitions for field: State of the FMC 2 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC1_N WBGEN2_GEN_MASK(1, 1)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
/* [0x4]: REG Status */
uint32_t STAT;
/* [0x8]: REG Control */
uint32_t CTRL;
/* [0xc]: REG Reset Register */
uint32_t RST;
};
#define CARRIER_CSR_PERIPH_PREFIX "carrier_csr"
#define CARRIER_CSR_PERIPH_NAME "SVEC carrier control and status registers"
#define CARRIER_CSR_PERIPH_DESC WBGEN2_DESC("Wishbone slave for control and status registers related to the SVEC FMC carrier")
#endif
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