Commit 88165e5d authored by Jan Pospisil's avatar Jan Pospisil

added license, headers, comments

parent 4706f608
This diff is collapsed.
------------------------------------------------------------------------
-- Title : AD9512 Control
-- Project : http://www.ohwr.org/projects/fmc-del-1ns-2cha/
------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : AD9512 clock divider automatic control
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : Ad9512Control.vhd
-- Author : T. Levens, J. Pospisil
-- Company : CERN BE-BI-QP
-- Author(s) : Tom Levens <tom.levens@cern.ch>
-- Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2015-08-17
-- Last update: 2016-08-18
-- Platform : FPGA-generic
-- Standard : VHDL
------------------------------------------------------------------------
-- Description:
--
-- AD9512 control using OpenCores SPI master.
--
-- Based on https://gitlab.cern.ch/bi/mim/blob/master/hdl/rtl/PllControl.v
------------------------------------------------------------------------
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: AD9512 clock divider automatic control using OpenCores SPI
-- master. Based on:
-- https://gitlab.cern.ch/bi/mim/blob/master/hdl/rtl/PllControl.v
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-06-21 0.1 Tom Levens
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......
-------------------------------------------------------------------------------
-- Title : Testbench for Ad9512Control.vhd
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : Ad9512Control_tb.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-08-18
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : AD9512 clock divider synchronizer
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : Ad9512Syncer.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-08-17
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: On request, generates AD9512 synchronization pulse based on
-- Trigger_i.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......
-------------------------------------------------------------------------------
-- Title : AD5600 DACs controller
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : DacsController.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-01
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Encapsulation for gc_serial_dac.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : MC100EP195 delay controller
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : DelayController.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-01
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Sets delay for individual MC100EP195 chips with shared D bus.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : Delayed Pulse Generator core
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : DelayedPulseGenerator.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-05
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Main functionality of the pulse generation - read the memory
-- and outputs pulses, synchronized by Trigger_i.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : Clock domain crossing for Delayed Pulse Generator core
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : DelayedPulseGeneratorsCdc.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-08-15
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Clock domain crossing between system (VME) clock and ClkRf_ik
-- RF clock.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : FSM for Delayed Pulse Generator core
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : Fsm.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-05
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This FSM controls pulse "generation" (waiting for Trigger_i, no
-- output) and "outputting" of the pulses according to Mode_i.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : FFPG core
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : FfpgCore.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-06-28
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Core entity of the FFPG functionality ~ one FMC mezzanine.
-- Contains FFPG WB slave and OneWire WB slave for on-board
-- temperature sensor read-out.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : FFPG package
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : FfpgPkg.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-01
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Contains mainly AD5600 interface and Mode declarations.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : FFPG Wishbone slave
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : FfpgSlave.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-25
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Encapsulates AD5600 DACs controller, MC100EP195 delay
-- controller, two Delayed Pulse Generator cores, clock
-- infrastructure (AD9512 and various clock inputs) configuration,
-- RF clock sense (frequency and stability) and informative LEDs
-- output.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : Clock frequency sense
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : FrequencySense.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-08-23
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Calculate input clock frequency and determines its stability.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : Testbench for FrequencySense.vhd
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : FrequencySense_tb.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-08-23
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
--
-- ShiftEnable_i register
-- Shift register
-- Jan Pospisil
-- 2010; KP, FEL, CVUT
-- 2016; BE-BI-QP, CERN
......
-------------------------------------------------------------------------------
-- Title : Wrapper for Wbgen2 generated Wishbone slave
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : WbSlaveWrapper.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-01
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Encapsulates functionality, which is not available in actual
-- version of Wbgen2.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : Wrapper of FfpgCore for SystemVerilog testbench
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : FfpgCoreWrapper.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-06-30
-- Last update: 2016-08-24
-- Standard : VHDL2008
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
/**
* UVM verification package for FMC DEL 1ns 2cha (FFPG)
* http://www.ohwr.org/projects/fmc-del-1ns-2cha/
* 2016_07_06, Jan Pospisil, j.pospisil@cern.ch
*/
//-----------------------------------------------------------------------------
// Title : UVM verification package for FMC DEL 1ns 2cha (FFPG)
// Project : FMC DEL 1ns 2cha (FFPG)
// URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
//-----------------------------------------------------------------------------
// File : FfpgFmcPackage.sv
// Author(s) : Jan Pospisil <j.pospisil@cern.ch>
// Company : CERN (BE-BI-QP)
// Created : 2016-07-06
// Last update: 2016-08-24
// Standard : SystemVerilog, UVM
//-----------------------------------------------------------------------------
// Description:
//-----------------------------------------------------------------------------
// Copyright (c) 2016 CERN (BE-BI-QP)
//-----------------------------------------------------------------------------
// GNU LESSER GENERAL PUBLIC LICENSE
//-----------------------------------------------------------------------------
// This source file is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by the
// Free Software Foundation; either version 2.1 of the License, or (at your
// option) any later version. This source is distributed in the hope that it
// will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU Lesser General Public License for more details. You should have
// received a copy of the GNU Lesser General Public License along with this
// source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author
// 2016-08-24 1.0 Jan Pospisil
//-----------------------------------------------------------------------------
`include "timescale.svh"
`include "uvm_macros.svh"
......
//-----------------------------------------------------------------------------
// Title : UVM testbench for FFPG core
// Project : FMC DEL 1ns 2cha (FFPG)
// URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
//-----------------------------------------------------------------------------
// File : Testbench.sv
// Author(s) : Jan Pospisil <j.pospisil@cern.ch>
// Company : CERN (BE-BI-QP)
// Created : 2016-06-30
// Last update: 2016-08-24
// Standard : SystemVerilog, UVM
//-----------------------------------------------------------------------------
// Description:
//-----------------------------------------------------------------------------
// Copyright (c) 2016 CERN (BE-BI-QP)
//-----------------------------------------------------------------------------
// GNU LESSER GENERAL PUBLIC LICENSE
//-----------------------------------------------------------------------------
// This source file is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by the
// Free Software Foundation; either version 2.1 of the License, or (at your
// option) any later version. This source is distributed in the hope that it
// will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU Lesser General Public License for more details. You should have
// received a copy of the GNU Lesser General Public License along with this
// source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author
// 2016-08-24 1.0 Jan Pospisil
//-----------------------------------------------------------------------------
`include "timescale.svh"
`include "Config.svh"
......
//-----------------------------------------------------------------------------
// Title : UVM verification package for FFPG core testbench
// Project : FMC DEL 1ns 2cha (FFPG)
// URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
//-----------------------------------------------------------------------------
// File : TestbenchPackage.sv
// Author(s) : Jan Pospisil <j.pospisil@cern.ch>
// Company : CERN (BE-BI-QP)
// Created : 2016-06-30
// Last update: 2016-08-24
// Standard : SystemVerilog, UVM
//-----------------------------------------------------------------------------
// Description:
//-----------------------------------------------------------------------------
// Copyright (c) 2016 CERN (BE-BI-QP)
//-----------------------------------------------------------------------------
// GNU LESSER GENERAL PUBLIC LICENSE
//-----------------------------------------------------------------------------
// This source file is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by the
// Free Software Foundation; either version 2.1 of the License, or (at your
// option) any later version. This source is distributed in the hope that it
// will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU Lesser General Public License for more details. You should have
// received a copy of the GNU Lesser General Public License along with this
// source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author
// 2016-08-24 1.0 Jan Pospisil
//-----------------------------------------------------------------------------
`include "timescale.svh"
`include "Config.svh"
......
-------------------------------------------------------------------------------
-- Title : Heart beat generator
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : HeartBeat.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-28
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Generates "glowing" signal, intended for LED signalization.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : Testbench for HeartBeat.vhd
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : HeartBeat_tb.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-28
-- Last update: 2016-08-24
-- Standard : VHDL2008
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : Top-level entity for implementation on SVEC carrier card
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : SvecTopFfpg.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-26
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Contains code for two FMC mezzanines, communication via VME bus
-- and other board specific code.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-------------------------------------------------------------------------------
-- Title : Wrapper of SvecTopFfpg for SystemVerilog testbench
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : SvecTopFfpgWrapper.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-08-03
-- Last update: 2016-08-24
-- Standard : VHDL2008
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
//-----------------------------------------------------------------------------
// Title : Testbench for implementation on SVEC carrier card
// Project : FMC DEL 1ns 2cha (FFPG)
// URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
//-----------------------------------------------------------------------------
// File : Testbench.sv
// Author(s) : Jan Pospisil <j.pospisil@cern.ch>
// Company : CERN (BE-BI-QP)
// Created : 2016-08-03
// Last update: 2016-08-24
// Standard : SystemVerilog
//-----------------------------------------------------------------------------
// Description:
//-----------------------------------------------------------------------------
// Copyright (c) 2016 CERN (BE-BI-QP)
//-----------------------------------------------------------------------------
// GNU LESSER GENERAL PUBLIC LICENSE
//-----------------------------------------------------------------------------
// This source file is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by the
// Free Software Foundation; either version 2.1 of the License, or (at your
// option) any later version. This source is distributed in the hope that it
// will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU Lesser General Public License for more details. You should have
// received a copy of the GNU Lesser General Public License along with this
// source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author
// 2016-08-24 1.0 Jan Pospisil
//-----------------------------------------------------------------------------
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "fmc.svh"
......
// http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/repository/revisions/master/changes/hdl/svec/sim/vme64x_bfm/components/sn74vmeh22501.v
`timescale 1ns/1ns
module sn74vmeh22501 (
......
// http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/repository/revisions/master/changes/hdl/svec/sim/vme64x_bfm/svec_vme_buffers.svh
// modified by Jan Pospisil, j.pospisil@cern.ch, 2016, CERN BE-BI-QP
`include "components/sn74vmeh22501.v"
`include "vme64x_bfm.svh"
......
// http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/repository/revisions/master/changes/hdl/svec/sim/vme64x_bfm/vme64x_bfm.svh
// modified by Jan Pospisil, j.pospisil@cern.ch, 2016, CERN BE-BI-QP
`ifndef __VME64X_BFM_SVH
`define __VME64X_BFM_SVH 1
......
#!/usr/bin/env python
# TODO: propper BUSY bits checking
##-----------------------------------------------------------------------------
## Title : Driver example
## Project : FMC DEL 1ns 2cha (FFPG)
## URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
##-----------------------------------------------------------------------------
## File : FFPG_driver.py
## Author(s) : Jan Pospisil <j.pospisil@cern.ch>
## Company : CERN (BE-BI-QP)
## Created : 2016-08-09
## Last update: 2016-08-24
## Standard : Python
##-----------------------------------------------------------------------------
## Description: Example functions how to operate the FFPG gateware via its
## Wishbone interface.
##-----------------------------------------------------------------------------
## Copyright (c) 2016 CERN (BE-BI-QP)
##-----------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
##-----------------------------------------------------------------------------
## This source file is free software; you can redistribute it and/or modify it
## under the terms of the GNU Lesser General Public License as published by the
## Free Software Foundation; either version 2.1 of the License, or (at your
## option) any later version. This source is distributed in the hope that it
## will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
## of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details. You should have
## received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-----------------------------------------------------------------------------
## Revisions :
## Date Version Author
## 2016-08-24 1.0 Jan Pospisil
##-----------------------------------------------------------------------------
# TODO: proper BUSY bits checking
import sys
import time
......
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