FFPG_driver.py 5.57 KB
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#!/usr/bin/env python
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# coding: utf8
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##-----------------------------------------------------------------------------
## Title      : Driver example
## Project    : FMC DEL 1ns 2cha (FFPG)
## URL        : http://www.ohwr.org/projects/fmc-del-1ns-2cha
##-----------------------------------------------------------------------------
## File       : FFPG_driver.py
## Author(s)  : Jan Pospisil <j.pospisil@cern.ch>
## Company    : CERN (BE-BI-QP)
## Created    : 2016-08-09
## Last update: 2016-08-24
## Standard   : Python
##-----------------------------------------------------------------------------
## Description: Example functions how to operate the FFPG gateware via its
##              Wishbone interface.
##-----------------------------------------------------------------------------
## Copyright (c) 2016 CERN (BE-BI-QP)
##-----------------------------------------------------------------------------
## GNU LESSER GENERAL PUBLIC LICENSE
##-----------------------------------------------------------------------------
## This source file is free software; you can redistribute it and/or modify it
## under the terms of the GNU Lesser General Public License as published by the
## Free Software Foundation; either version 2.1 of the License, or (at your
## option) any later version. This source is distributed in the hope that it
## will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
## of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
## See the GNU Lesser General Public License for more details. You should have
## received a copy of the GNU Lesser General Public License along with this
## source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##-----------------------------------------------------------------------------
## Revisions  :
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## Date        Version  Author        Comment
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## 2016-08-24  1.0      Jan Pospisil
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## 2016-09-01  1.1      Jan Pospisil  added version numbers (major.minor.rev)
##                                    added clock_stable status bit
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##                                    added option for negative pulses
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## 2016-09-02  1.2      Michael Betz  added reset of MC100EP140 bad state;
##                                    better configuration; better debugging;
##                                    comments; attempt for better trigger
##                                    latency calibration (not working yet)
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## 2016-09-05  1.3      Jan Pospisil  Independent Trigger Latency for the two
##                                    channels (issue 1389)
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##                                    added version check
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## 2016-09-06  1.4      Jan Pospisil  fixed OneWire code
##                                    convert to OOP
##                                    divided into more files
##                                    simplified interface
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## 2016-09-21  1.5      Jan Pospisil  added calibration example code
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##----------------------------------------------------------------------------- 

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import time
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from Ffpg import *

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# triggerPhase = 53.76 # same for both channels in the test setup
calibrationData = [ # -1 = uncalibrated
    # channel 1, channel 2
    [51.29, 51.03],     # FMC slot 0
    [51.29, 51.11]      # FMC slot 1
]

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fmcSlot = 1 # 0 | 1
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channel = 1 # 1 | 2
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ad9512Config = (
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    (0x34, 0x01),
    (0x35, 0x00),
    (0x36, 0x00),
    (0x3f, 0x03),
    (0x45, 0x05),
    (0x4a, 0x00),
    (0x4c, 0x00),
    (0x4e, 0x00),
    (0x50, 0x00),
    (0x52, 0x00),
    (0x4b, 0x00),
    (0x4d, 0x00),
    (0x4f, 0x00),
    (0x51, 0x00),
    (0x53, 0x00),
    (0x58, 0x20)
)

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def Init(pg):
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    global calibrationData
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    pg.Reset()
    pg.SelectClock("external", 400.789)
    pg.SetRatio(2)
    pg.SetOverflow(17820)
    pg.Ad9512Sync()
    pg.SetTriggerThreshold(0.5)
    pg.SetVcxoFrequency(-0.2105) # 125.0000 MHz
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    # calibration
    fmcSlot = pg.GetFmcSlot()
    for channel in [1,2]:
        triggerPhase = calibrationData[fmcSlot][channel-1]
        print("Calibrating channel "+str(channel)+" on FMC slot "+str(fmcSlot)+" to "+str(triggerPhase)+" ns")
        if triggerPhase > -1:
            pg.SetTriggerPhase(channel, triggerPhase)
        else:
            print("   (Skipping this calibration, no calibration data (-1) provided.)")
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def TestSinglePulse(pg, channel):
    pg.ResetBadState(channel)
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    pg.CreateSinglePulse(channel, start = 0, width = 10, polarity = 1)
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    pg.EnableChannel(channel)
    pg.StartChannel(channel)

def TestBunchPulses(pg, channel):
    pg.ResetBadState(channel)
    pg.CreateBunchPulses(channel, pulseDelay = 10, pulseWidth = 10, bunches = (0,1,10,15), polarity = 1)
    pg.EnableChannel(channel)
    pg.StartChannel(channel)

def StopAndDisable(pg, channel):
    pg.StopChannel(channel)
    pg.DisableChannel(channel)

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def PrintFrequency(pg):
    frequency = pg.GetFrequency()
    if frequency is not None:
        print("RF clock frequency: "+str(frequency/1.0e6) + " MHz")
    else:
        print("RF clock frequency: (unstable)")

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# create FFPG driver for FMC slot
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pg = Ffpg(fmcSlot)
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# activate low-level debug output
# pg.wb.SetDebug(True)
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# activate SystemVerilog trace debug
# pg.wb.SetDebugSv("wb_trace.svh")
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# initialize the driver
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Init(pg)
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# create single pulse
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TestSinglePulse(pg, channel)
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# create bunched pulses
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# TestBunchPulses(pg, channel)
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# stop and disable channel
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# StopAndDisable(pg, channel)
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# print some info
pg.PrintVersion()
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# print("Actual temperature: "+str(pg.temp.ReadTemperature()) + " °C")
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PrintFrequency(pg)
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pg.PrintControl()
pg.PrintStatus()
pg.PrintDebug()
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'''
pg.Ad9512ActivateWbAccess()
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pg.ad9512.debug = True
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pg.ad9512.Config(ad9512Config)
pg.ad9512.Check(ad9512Config)
pg.Ad9512DisableWbAccess()
'''
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