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Requirements
============

1 MHz <= f_ClkIn0_ik <= 204 MHz

Implementation
==============

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1) Git - make sure submodules are updated

2) make Wishbone slaves:
    mkdir .\doc\manual\svec
    cd .\hdl\svec\wb_gen 
    make carrier_csr
    cd ..\..\ffpg\wb_gen
    make ffpg_csr

3) in .\hdl\ffpg\rtl\ffpg_csr.vhd add this function before function "function "or" (left, right: t_ffpg_in_registers) return t_ffpg_in_registers":
    function f_x_to_zero (x: unsigned) return unsigned is begin
        return unsigned(f_x_to_zero(std_logic_vector(x)));
    end function;
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  (This step is not needed when ./hdl/ip_cores/wishbone-gen_patches are applied.)
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X) synthesize .\hdl\svec\syn\SvecFfpg.xise

Testing
=======

The "!->" determines what to check further when check fails.

1) Plug FMC mezzanine into SVEC carrier board and into VME crate (and configure properly)
2) When using FMC mezzanine version 2 (EDA-03339-V2), check that all power LEDs (LD1, LD2, LD3) are on (!-> SVEC fuses, power supplies)
3) Connect clock (CLK IN) f_CLK = 400.789 MHz and trigger (TRIG IN) f_TRIG = 11.245 kHz - trigger has to be phase aligned with clock
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4) Use /sw/FFPG_driver.py or /sw/FFPG_test.py to configure the GW and run some test
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5) Check:
    a) There is f_CLK/2 clock present on CLK OUT (!-> AD9512 divider)
    b) LED CLK IN is on (!-> clock source is not stable?)
    c) python: PrintFrequency(pg) should return also f_CLK/2 (!-> clock infrastructure)
    d) LED TRIG IN is blinking (!-> trigger input)
    e) python: pg.PrintDebug() should display "CHx FSM state: Outputting" (!-> "WaitForTrigger" - check trigger input; "Stop" - check channel configuration)
    f) python: pg.PrintStatus() should display "Channel x output: enabled" and "Channel 1: running" (!-> channel configuration)
    g) LED OUT x is on (!-> channel configuration)
    h) there is/are pulse(s) on the OUT x output

To isolate output stage (optical switch and fuse) error, you can use front panel LEMO connectors. When channel output is disabled (schematic: OUT_EN_x, python: CHx_OE), output is redirected from front panel connector to FMC feedback loop back to FPGA (schematic CAL_OUT_2). These signal are connected to the SVEC front panel LEMO connectors with this mapping:
    LEMO 1 - FMC2, channel 1
    LEMO 2 - FMC2, channel 2
    LEMO 3 - FMC1, channel 1
    LEMO 4 - FMC1, channel 2