ffpg_csr

FMC DEL 1ns 2cha core registers

Wishbone slave for FMC DEL 1ns 2cha core

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Status register
3.2. Control register
3.3. VCXO voltage register
3.4. Clock ratio-1 register
3.5. SET delay configuration (channel 1)
3.6. RES delay configuration (channel 1)
3.7. SET delay configuration (channel 2)
3.8. RES delay configuration (channel 2)
3.9. Trigger threshold voltage register
3.10. Overflow
3.11. Trigger latency (channel 1)
3.12. Clock frequency
3.13. Debug register
3.14. Gateware version
3.15. Trigger latency (channel 2)
3.16. AD9512 OUT4 fine delay
4. Memory blocks
4.1. CH1 SET serial stream
4.2. CH1 RES serial stream
4.3. CH2 SET serial stream
4.4. CH2 RES serial stream

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	Status register	ffpg_status	STATUS
0x1	REG	Control register	ffpg_control	CONTROL
0x2	REG	VCXO voltage register	ffpg_vcxo_voltage	VCXO_VOLTAGE
0x3	REG	Clock ratio-1 register	ffpg_clock_ratio_m1	CLOCK_RATIO_M1
0x4	REG	SET delay configuration (channel 1)	ffpg_ch1_delay_set	CH1_DELAY_SET
0x5	REG	RES delay configuration (channel 1)	ffpg_ch1_delay_reset	CH1_DELAY_RESET
0x6	REG	SET delay configuration (channel 2)	ffpg_ch2_delay_set	CH2_DELAY_SET
0x7	REG	RES delay configuration (channel 2)	ffpg_ch2_delay_reset	CH2_DELAY_RESET
0x8	REG	Trigger threshold voltage register	ffpg_trigger_threshold	TRIGGER_THRESHOLD
0x9	REG	Overflow	ffpg_overflow	OVERFLOW
0xa	REG	Trigger latency (channel 1)	ffpg_ch1_trigger_latency	CH1_TRIGGER_LATENCY
0xb	REG	Clock frequency	ffpg_frequency	FREQUENCY
0xc	REG	Debug register	ffpg_debug	DEBUG
0xd	REG	Gateware version	ffpg_version	VERSION
0xe	REG	Trigger latency (channel 2)	ffpg_ch2_trigger_latency	CH2_TRIGGER_LATENCY
0xf	REG	AD9512 OUT4 fine delay	ffpg_fine_delay	FINE_DELAY
0x800 - 0xfff	MEM	CH1 SET serial stream	ffpg_ch1_set_mem	CH1_SET_MEM
0x1000 - 0x17ff	MEM	CH1 RES serial stream	ffpg_ch1_res_mem	CH1_RES_MEM
0x1800 - 0x1fff	MEM	CH2 SET serial stream	ffpg_ch2_set_mem	CH2_SET_MEM
0x2000 - 0x27ff	MEM	CH2 RES serial stream	ffpg_ch2_res_mem	CH2_RES_MEM

2. HDL symbol

→	rst_n_i	Status register:
→	clk_sys_i	ffpg_status_clock_infrastructure_busy_i	←
⇒	wb_adr_i[13:0]	ffpg_status_dac_vcxo_busy_i	←
⇒	wb_dat_i[31:0]	ffpg_status_dac_trigger_busy_i	←
⇐	wb_dat_o[31:0]	ffpg_status_delay_configuration_busy_i	←
→	wb_cyc_i	ffpg_status_channel_1_oe_i	←
⇒	wb_sel_i[3:0]	ffpg_status_channel_2_oe_i	←
→	wb_stb_i	ffpg_status_channel_1_running_i	←
→	wb_we_i	ffpg_status_channel_2_running_i	←
←	wb_ack_o	ffpg_status_input_clock_stable_i	←
←	wb_stall_o
		Control register:
		ffpg_control_clock_selection_o[1:0]	⇒
		ffpg_control_ch1_oe_o	→
		ffpg_control_ch2_oe_o	→
		ffpg_control_ch1_mode_o[1:0]	⇒
		ffpg_control_ch2_mode_o[1:0]	⇒
		ffpg_control_led_test_o	→
		ffpg_control_ad9512_sync_o	→
		ffpg_control_fine_delay_enable_o	→

		VCXO voltage register:
		ffpg_vcxo_voltage_o[15:0]	⇒
		ffpg_vcxo_voltage_i[15:0]	⇐
		ffpg_vcxo_voltage_load_o	→

		Clock ratio-1 register:
		ffpg_clock_ratio_m1_o[4:0]	⇒
		ffpg_clock_ratio_m1_i[4:0]	⇐
		ffpg_clock_ratio_m1_load_o	→

		SET delay configuration (channel 1):
		ffpg_ch1_delay_set_o[9:0]	⇒
		ffpg_ch1_delay_set_i[9:0]	⇐
		ffpg_ch1_delay_set_load_o	→

		RES delay configuration (channel 1):
		ffpg_ch1_delay_reset_o[9:0]	⇒
		ffpg_ch1_delay_reset_i[9:0]	⇐
		ffpg_ch1_delay_reset_load_o	→

		SET delay configuration (channel 2):
		ffpg_ch2_delay_set_o[9:0]	⇒
		ffpg_ch2_delay_set_i[9:0]	⇐
		ffpg_ch2_delay_set_load_o	→

		RES delay configuration (channel 2):
		ffpg_ch2_delay_reset_o[9:0]	⇒
		ffpg_ch2_delay_reset_i[9:0]	⇐
		ffpg_ch2_delay_reset_load_o	→

		Trigger threshold voltage register:
		ffpg_trigger_threshold_o[15:0]	⇒
		ffpg_trigger_threshold_i[15:0]	⇐
		ffpg_trigger_threshold_load_o	→

		Overflow:
		ffpg_overflow_o[15:0]	⇒
		ffpg_overflow_i[15:0]	⇐
		ffpg_overflow_load_o	→

		Trigger latency (channel 1):
		ffpg_ch1_trigger_latency_o[15:0]	⇒
		ffpg_ch1_trigger_latency_i[15:0]	⇐
		ffpg_ch1_trigger_latency_load_o	→

		Clock frequency:
		ffpg_frequency_i[31:0]	⇐

		Debug register:
		ffpg_debug_i[31:0]	⇐

		Gateware version:
		ffpg_version_revision_i[11:0]	⇐
		ffpg_version_minor_i[9:0]	⇐
		ffpg_version_major_i[9:0]	⇐

		Trigger latency (channel 2):
		ffpg_ch2_trigger_latency_o[15:0]	⇒
		ffpg_ch2_trigger_latency_i[15:0]	⇐
		ffpg_ch2_trigger_latency_load_o	→

		AD9512 OUT4 fine delay:
		ffpg_fine_delay_value_o[4:0]	⇒
		ffpg_fine_delay_value_i[4:0]	⇐
		ffpg_fine_delay_value_load_o	→
		ffpg_fine_delay_current_o[2:0]	⇒
		ffpg_fine_delay_current_i[2:0]	⇐
		ffpg_fine_delay_current_load_o	→
		ffpg_fine_delay_capacitors_o[2:0]	⇒
		ffpg_fine_delay_capacitors_i[2:0]	⇐
		ffpg_fine_delay_capacitors_load_o	→

		CH1 SET serial stream:
		ffpg_ch1_set_mem_addr_i[10:0]	⇐
		ffpg_ch1_set_mem_data_o[31:0]	⇒
		ffpg_ch1_set_mem_rd_i	←

		CH1 RES serial stream:
		ffpg_ch1_res_mem_addr_i[10:0]	⇐
		ffpg_ch1_res_mem_data_o[31:0]	⇒
		ffpg_ch1_res_mem_rd_i	←

		CH2 SET serial stream:
		ffpg_ch2_set_mem_addr_i[10:0]	⇐
		ffpg_ch2_set_mem_data_o[31:0]	⇒
		ffpg_ch2_set_mem_rd_i	←

		CH2 RES serial stream:
		ffpg_ch2_res_mem_addr_i[10:0]	⇐
		ffpg_ch2_res_mem_data_o[31:0]	⇒
		ffpg_ch2_res_mem_rd_i	←

3.1. Status register

HW prefix:	ffpg_status
HW address:	0x0
C prefix:	STATUS
C offset:	0x0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	INPUT_CLOCK_STABLE

7	6	5	4	3	2	1	0
CHANNEL_2_RUNNING	CHANNEL_1_RUNNING	CHANNEL_2_OE	CHANNEL_1_OE	DELAY_CONFIGURATION_BUSY	DAC_TRIGGER_BUSY	DAC_VCXO_BUSY	CLOCK_INFRASTRUCTURE_BUSY

[0] CLOCK_INFRASTRUCTURE_BUSY [read-only]: Clock infrastructure configuration in progress
Status of the clock infrastructure configuration
0: configuration done
1: configuration in progress
[1] DAC_VCXO_BUSY [read-only]: VCXO DAC busy
Status of the VCXO DAC communication
0: DAC idle, value already set
1: DAC busy, communication in progress
[2] DAC_TRIGGER_BUSY [read-only]: Trigger DAC busy
Status of the trigger DAC communication
0: DAC idle, value already set
1: DAC busy, communication in progress
[3] DELAY_CONFIGURATION_BUSY [read-only]: Delay configuration in progress
Status of the delay configuration
0: configuration done
1: configuration in progress
[4] CHANNEL_1_OE [read-only]: Channel 1 output enabled
Channel 1 output enabled
0: output disabled
1: output enabled
[5] CHANNEL_2_OE [read-only]: Channel 2 output enabled
Channel 2 output enabled
0: output disabled
1: output enabled
[6] CHANNEL_1_RUNNING [read-only]: Pulse generator channel 1 running
Pulse generator channel 1 running
0: channel 1 is not running
1: channel 1 is running, pulses are generated
[7] CHANNEL_2_RUNNING [read-only]: Pulse generator channel 2 running
Pulse generator channel 2 running
0: channel 2 is not running
1: channel 2 is running, pulses are generated
[8] INPUT_CLOCK_STABLE [read-only]: Input clock stable
Indicates the stability of the input clock.
0: input clock not present or not stable
1: input clock present and stable

3.2. Control register

HW prefix:	ffpg_control
HW address:	0x1
C prefix:	CONTROL
C offset:	0x4

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	FINE_DELAY_ENABLE	AD9512_SYNC	LED_TEST

7	6	5	4	3	2	1	0
CH2_MODE[1:0]		CH1_MODE[1:0]		CH2_OE	CH1_OE	CLOCK_SELECTION[1:0]

[2:0] CLOCK_SELECTION [read/write]: Clock source selection
0 (default): external clock used (connector on the front panel)
1: FPGA loop clock used
2: on-board VCXO clock used
[2] CH1_OE [read/write]: CH1 output enable
[3] CH2_OE [read/write]: CH2 output enable
[6:4] CH1_MODE [read/write]: CH1 mode selection
0 (default): stopped (no output generated)
1: continuous (non-stop memory looping)
2: one-shot (loop memory just once)
[8:6] CH2_MODE [read/write]: CH2 mode selection
0 (default): stopped (no output generated)
1: continuous (non-stop memory looping)
2: one-shot (loop memory just once)
[8] LED_TEST [read/write]: LED test
If set to 1, all LEDs on the FFPG front panel will be blinking.
[9] AD9512_SYNC [write-only]: AD9512 Synchronization
When written with 1 AD9512 dividers synchronization is performed. It automatically clear to 0.
[10] FINE_DELAY_ENABLE [read/write]: AD9512 OUT4 fine delay enable
If set to 1, fine delay on OUT4 output of AD9512 is enabled. Fine delay itself can be set in a separate register.

3.3. VCXO voltage register

HW prefix:	ffpg_vcxo_voltage
HW address:	0x2
C prefix:	VCXO_VOLTAGE
C offset:	0x8

This register value D determines output voltage of the VCXO DAC.
Voltage should be V_OUT = D * 5 / 65536 [V] (see datasheet), but is limited by 3.3 V supply voltage of the DAC.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
VCXO_VOLTAGE[15:8]

7	6	5	4	3	2	1	0
VCXO_VOLTAGE[7:0]

[16:0] VCXO_VOLTAGE [read/write]: VCXO voltage register value

3.4. Clock ratio-1 register

HW prefix:	ffpg_clock_ratio_m1
HW address:	0x3
C prefix:	CLOCK_RATIO_M1
C offset:	0xc

Clock ratio specifies the frequency of the serial stream clock generated by the AD9512 clock divider: f_generated = f_input / (RATIO+1). This ratio is used for all clocks generated on the FMC card. Permitted values are 0-31 which renders to actual ratio 1-32.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	CLOCK_RATIO_M1[4:0]

[5:0] CLOCK_RATIO_M1 [read/write]: Clock ratio-1

3.5. SET delay configuration (channel 1)

HW prefix:	ffpg_ch1_delay_set
HW address:	0x4
C prefix:	CH1_DELAY_SET
C offset:	0x10

10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH1 pulse delay

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	CH1_DELAY_SET[9:8]

7	6	5	4	3	2	1	0
CH1_DELAY_SET[7:0]

[10:0] CH1_DELAY_SET [read/write]: CH1 SET delay

3.6. RES delay configuration (channel 1)

HW prefix:	ffpg_ch1_delay_reset
HW address:	0x5
C prefix:	CH1_DELAY_RESET
C offset:	0x14

10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH1 pulse width

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	CH1_DELAY_RESET[9:8]

7	6	5	4	3	2	1	0
CH1_DELAY_RESET[7:0]

[10:0] CH1_DELAY_RESET [read/write]: CH1 RES delay

3.7. SET delay configuration (channel 2)

HW prefix:	ffpg_ch2_delay_set
HW address:	0x6
C prefix:	CH2_DELAY_SET
C offset:	0x18

10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH2 pulse delay

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	CH2_DELAY_SET[9:8]

7	6	5	4	3	2	1	0
CH2_DELAY_SET[7:0]

[10:0] CH2_DELAY_SET [read/write]: CH2 SET delay

3.8. RES delay configuration (channel 2)

HW prefix:	ffpg_ch2_delay_reset
HW address:	0x7
C prefix:	CH2_DELAY_RESET
C offset:	0x1c

10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH2 pulse width

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	CH2_DELAY_RESET[9:8]

7	6	5	4	3	2	1	0
CH2_DELAY_RESET[7:0]

[10:0] CH2_DELAY_RESET [read/write]: CH2 RES delay

3.9. Trigger threshold voltage register

HW prefix:	ffpg_trigger_threshold
HW address:	0x8
C prefix:	TRIGGER_THRESHOLD
C offset:	0x20

This register value D determines output voltage of the trigger threshold DAC.
Voltage should be V_OUT = D * 5 / 65536 [V] (see datasheet).

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
TRIGGER_THRESHOLD[15:8]

7	6	5	4	3	2	1	0
TRIGGER_THRESHOLD[7:0]

[16:0] TRIGGER_THRESHOLD [read/write]: Trigger threshold voltage register value

3.10. Overflow

HW prefix:	ffpg_overflow
HW address:	0x9
C prefix:	OVERFLOW
C offset:	0x24

Overflow index for serial stream memory. When this index is reach when looping the memory, memory index is reset back to 0.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
OVERFLOW[15:8]

7	6	5	4	3	2	1	0
OVERFLOW[7:0]

[16:0] OVERFLOW [read/write]: Overflow value

3.11. Trigger latency (channel 1)

HW prefix:	ffpg_ch1_trigger_latency
HW address:	0xa
C prefix:	CH1_TRIGGER_LATENCY
C offset:	0x28

The latency of the trigger in number of clock cycles of the serial stream clock, for channel 1. When trigger is received, serial stream memory pointer is set to this value.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
CH1_TRIGGER_LATENCY[15:8]

7	6	5	4	3	2	1	0
CH1_TRIGGER_LATENCY[7:0]

[16:0] CH1_TRIGGER_LATENCY [read/write]: Trigger latency value

3.12. Clock frequency

HW prefix:	ffpg_frequency
HW address:	0xb
C prefix:	FREQUENCY
C offset:	0x2c

Frequency of the input clock in Hz.

31	30	29	28	27	26	25	24
FREQUENCY[31:24]

23	22	21	20	19	18	17	16
FREQUENCY[23:16]

15	14	13	12	11	10	9	8
FREQUENCY[15:8]

7	6	5	4	3	2	1	0
FREQUENCY[7:0]

[32:0] FREQUENCY [read-only]: Clock frequency value

3.13. Debug register

HW prefix:	ffpg_debug
HW address:	0xc
C prefix:	DEBUG
C offset:	0x30

For internal use only, do not use!

31	30	29	28	27	26	25	24
DEBUG[31:24]

23	22	21	20	19	18	17	16
DEBUG[23:16]

15	14	13	12	11	10	9	8
DEBUG[15:8]

7	6	5	4	3	2	1	0
DEBUG[7:0]

[32:0] DEBUG [read-only]: Debug field

3.14. Gateware version

HW prefix:	ffpg_version
HW address:	0xd
C prefix:	VERSION
C offset:	0x34

Version of the current gateware in form of major.minor.revision

31	30	29	28	27	26	25	24
MAJOR[9:2]

23	22	21	20	19	18	17	16
MAJOR[1:0]		MINOR[9:4]

15	14	13	12	11	10	9	8
MINOR[3:0]				REVISION[11:8]

7	6	5	4	3	2	1	0
REVISION[7:0]

[12:0] REVISION [read-only]: Revision
[22:12] MINOR [read-only]: Minor version
[32:22] MAJOR [read-only]: Major version

3.15. Trigger latency (channel 2)

HW prefix:	ffpg_ch2_trigger_latency
HW address:	0xe
C prefix:	CH2_TRIGGER_LATENCY
C offset:	0x38

The latency of the trigger in number of clock cycles of the serial stream clock, for channel 2. When trigger is received, serial stream memory pointer is set to this value.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
CH2_TRIGGER_LATENCY[15:8]

7	6	5	4	3	2	1	0
CH2_TRIGGER_LATENCY[7:0]

[16:0] CH2_TRIGGER_LATENCY [read/write]: Trigger latency value

3.16. AD9512 OUT4 fine delay

HW prefix:	ffpg_fine_delay
HW address:	0xf
C prefix:	FINE_DELAY
C offset:	0x3c

Value of the AD9512 OUT4 output fine delay. The actual delay applied to the OUT4 output has an offset, i.e. it is non-zero even when zero is written to this register (when the fine delay is enabled - see the status register for the enable bit).

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	CAPACITORS[2:0]

7	6	5	4	3	2	1	0
CURRENT[2:0]			VALUE[4:0]

[5:0] VALUE [read/write]: AD9512 OUT4 fine delay value
[8:5] CURRENT [read/write]: Ramp current
[11:8] CAPACITORS [read/write]: Ramp capacitors

4.1. CH1 SET serial stream

HW prefix:	ffpg_ch1_set_mem
HW address:	0x800
C prefix:	CH1_SET_MEM
C offset:	0x2000
Size:	2048 32-bit words
Data width:	32
Access (bus):	read/write
Access (device):	read-only
Mirrored:	no
Byte-addressable:	no
Peripheral port:	asynchronous (clk_rf_ik)

⇒	ffpg_ch1_set_mem_addr_i[10:0]	ffpg_ch1_set_mem_data_o[31:0]	⇒
→	ffpg_ch1_set_mem_rd_i
→	clk_rf_ik

4.2. CH1 RES serial stream

HW prefix:	ffpg_ch1_res_mem
HW address:	0x1000
C prefix:	CH1_RES_MEM
C offset:	0x4000
Size:	2048 32-bit words
Data width:	32
Access (bus):	read/write
Access (device):	read-only
Mirrored:	no
Byte-addressable:	no
Peripheral port:	asynchronous (clk_rf_ik)

⇒	ffpg_ch1_res_mem_addr_i[10:0]	ffpg_ch1_res_mem_data_o[31:0]	⇒
→	ffpg_ch1_res_mem_rd_i
→	clk_rf_ik

4.3. CH2 SET serial stream

HW prefix:	ffpg_ch2_set_mem
HW address:	0x1800
C prefix:	CH2_SET_MEM
C offset:	0x6000
Size:	2048 32-bit words
Data width:	32
Access (bus):	read/write
Access (device):	read-only
Mirrored:	no
Byte-addressable:	no
Peripheral port:	asynchronous (clk_rf_ik)

⇒	ffpg_ch2_set_mem_addr_i[10:0]	ffpg_ch2_set_mem_data_o[31:0]	⇒
→	ffpg_ch2_set_mem_rd_i
→	clk_rf_ik

4.4. CH2 RES serial stream

HW prefix:	ffpg_ch2_res_mem
HW address:	0x2000
C prefix:	CH2_RES_MEM
C offset:	0x8000
Size:	2048 32-bit words
Data width:	32
Access (bus):	read/write
Access (device):	read-only
Mirrored:	no
Byte-addressable:	no
Peripheral port:	asynchronous (clk_rf_ik)

⇒	ffpg_ch2_res_mem_addr_i[10:0]	ffpg_ch2_res_mem_data_o[31:0]	⇒
→	ffpg_ch2_res_mem_rd_i
→	clk_rf_ik

ffpg_csr

FMC DEL 1ns 2cha core registers

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