Commit 410ac7fe authored by Mariusz Mroz's avatar Mariusz Mroz

Production Test Suite for the fmc-dac-600m-12b-1cha board. Initial version.

parents
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*.*\#
\#*
.\#*
*.*~
gateware/syn/*
!gateware/syn/*.xise
!gateware/syn/*.bin
!gateware/syn/*.bit
!gateware/syn/fpga_xst.bmm
gateware/ip_cores/debug/*
!gateware/ip_cores/debug/*.vhd
!gateware/ip_cores/debug/*.ngc
work
*.wlf
modelsim.ini
transcript
*.vstf
*.bak
*.vcd
#*.h
doc/*.pdf
*.o
*.so
*.pyc
*.elf
output
software/rf-test
*.png
*.odt.saved
python/sdbfs/IPMI-FRU
\ No newline at end of file
[submodule "gateware/ip_cores/wr-cores"]
path = gateware/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "gateware/ip_cores/general-cores"]
path = gateware/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "gateware/ip_cores/gn4124-core"]
path = gateware/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "software/wrpc-sw"]
path = software/wrpc-sw
url = git://ohwr.org/hdl-core-lib/wr-cores/wrpc-sw.git
[submodule "gateware/ip_cores/etherbone-core"]
path = gateware/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
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<name>pts_dds</name>
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WR RF Distribution Demo
Tomasz Wlostowski/CERN BE-CO-HT 2013
---------------------------------------
(c) Copyright CERN 2013
All of the code in this repository is licensed under GNU General Public License version 2 unless otherwise
stated in the file headers.
\ No newline at end of file
#!/bin/bash
echo "WARRNING!!!"
echo "errors indicating that modules are not loaded should be ignored"
echo "i.e: rmmod: \"ERROR: Module fmc_adc_100m14b is not currently loaded\" should be ignored"
rmmod fmc_adc_100m14b > /dev/null
rmmod zio > /dev/null
rmmod rawrabbit > /dev/null
rmmod spec > /dev/null
rmmod fmc > /dev/null
modprobe usbserial
rmmod cp210x
rmmod usbtmc
prg=$0
if [ ! -e "$prg" ]; then
case $prg in
(*/*) exit 1;;
(*) prg=$(command -v -- "$prg") || exit;;
esac
fi
dir=$(
cd -P -- "$(dirname -- "$prg")" && pwd -P
) || exit
prg=$dir/$(basename -- "$prg") || exit
top=`echo "$prg" | sed 's/pts.*/pts\//'`
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-bus/kernel/fmc.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/spec-sw/kernel/spec.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/zio/zio.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko"
insmod "$top/cp210x/cp210x.ko"
# "$top/usbdriver/usbtmc_load"
LOGDIR="$top/log_fmcdac600m12b1chadds"
mkdir -p "$LOGDIR"
mkdir -p "$LOGDIR/eeprom"
# sudo rm -fr $LOGDIR/pts*
serial=$1
if [ x$1 = x"" ]; then
echo -n "Please scan CERN serial number bar-code, then press [ENTER]: "
read serial
fi
if [ x$serial = x"" ]; then
serial=0000
fi
extra_serial=$2
if [ x$2 = x"" ]; then
echo -n "If needed input extra serial number and press [ENTER] OR just press [ENTER]: "
read extra_serial
fi
if [ x$extra_serial = x"" ]; then
extra_serial=0000
fi
echo " "
nb_test_limit=2
nb_test=1
while [ "$nb_test" -le "$nb_test_limit" ]
do
echo "--------------------------------------------------------------"
echo "Test series run $nb_test out of $nb_test_limit"
echo " "
# sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 02 03 04 05 06 07
sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 03 04 05 06 07
if [ "$nb_test" != "$nb_test_limit" ]
then
echo " "
echo -n "Do you want to run the test series again [y,n]? "
read reply
if [ "$reply" != "y" ]
then
break
fi
fi
nb_test=$(($nb_test+1))
done
echo "--------------------------------------------------------------"
echo " "
echo -n "End of the test, do you want to switch the computer OFF? [y,n]"
read reply
if [ "$reply" = "y" ]
then
sudo halt
fi
#!/bin/bash
echo "WARRNING!!!"
echo "errors indicating that modules are not loaded should be ignored"
echo "i.e: rmmod: \"ERROR: Module fmc_adc_100m14b is not currently loaded\" should be ignored"
rmmod fmc_adc_100m14b > /dev/null
rmmod zio > /dev/null
rmmod rawrabbit > /dev/null
rmmod spec > /dev/null
rmmod fmc > /dev/null
modprobe usbserial
rmmod cp210x
rmmod usbtmc
prg=$0
if [ ! -e "$prg" ]; then
case $prg in
(*/*) exit 1;;
(*) prg=$(command -v -- "$prg") || exit;;
esac
fi
dir=$(
cd -P -- "$(dirname -- "$prg")" && pwd -P
) || exit
prg=$dir/$(basename -- "$prg") || exit
top=`echo "$prg" | sed 's/pts.*/pts\//'`
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-bus/kernel/fmc.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/spec-sw/kernel/spec.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/zio/zio.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko"
insmod "$top/cp210x/cp210x.ko"
# "$top/usbdriver/usbtmc_load"
LOGDIR="$top/log_fmcdac600m12b1chadds"
mkdir -p "$LOGDIR"
mkdir -p "$LOGDIR/eeprom"
# sudo rm -fr $LOGDIR/pts*
serial=$1
if [ x$1 = x"" ]; then
echo -n "Please scan CERN serial number bar-code, then press [ENTER]: "
read serial
fi
if [ x$serial = x"" ]; then
serial=0000
fi
extra_serial=$2
if [ x$2 = x"" ]; then
echo -n "If needed input extra serial number and press [ENTER] OR just press [ENTER]: "
read extra_serial
fi
if [ x$extra_serial = x"" ]; then
extra_serial=0000
fi
echo " "
nb_test_limit=2
nb_test=1
while [ "$nb_test" -le "$nb_test_limit" ]
do
echo "--------------------------------------------------------------"
echo "Test series run $nb_test out of $nb_test_limit"
echo " "
# sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 02 03 04 05 06 07
sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 03 04 05 06 07
if [ "$nb_test" != "$nb_test_limit" ]
then
echo " "
echo -n "Do you want to run the test series again [y,n]? "
read reply
if [ "$reply" != "y" ]
then
break
fi
fi
nb_test=$(($nb_test+1))
done
echo "--------------------------------------------------------------"
echo " "
echo -n "End of the test, do you want to switch the computer OFF? [y,n]"
read reply
if [ "$reply" = "y" ]
then
sudo halt
fi
This diff is collapsed.
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon.vhd
-- /___/ /\ Timestamp : czw lut 12 16:53:28 CET 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon IS
port (
CONTROL0: inout std_logic_vector(35 downto 0));
END chipscope_icon;
ARCHITECTURE chipscope_icon_a OF chipscope_icon IS
BEGIN
END chipscope_icon_a;
This diff is collapsed.
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon2.vhd
-- /___/ /\ Timestamp : śro kwi 08 13:56:51 CEST 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon2 IS
port (
CONTROL0: inout std_logic_vector(35 downto 0));
END chipscope_icon2;
ARCHITECTURE chipscope_icon2_a OF chipscope_icon2 IS
BEGIN
END chipscope_icon2_a;
This diff is collapsed.
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila.vhd
-- /___/ /\ Timestamp : czw lut 12 16:52:44 CET 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(63 downto 0));
END chipscope_ila;
ARCHITECTURE chipscope_ila_a OF chipscope_ila IS
BEGIN
END chipscope_ila_a;
This diff is collapsed.
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila2.vhd
-- /___/ /\ Timestamp : śro kwi 08 13:58:49 CEST 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila2 IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(191 downto 0));
END chipscope_ila2;
ARCHITECTURE chipscope_ila2_a OF chipscope_ila2 IS
BEGIN
END chipscope_ila2_a;
files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd","dds_tx_path.vhd","dds_rx_path.vhd","timestamp_compare.vhd","pll_init.v" ]
modules = {"local":"streamers"}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dds_wbgen2_pkg.all;
entity ad7980_if is
-- when triggered sets CNV (conversion) high for gc_conversion_time
-- reads sample value (from SPI interface)
-- outputs sample value and confirms with data_valid
generic (
-- should be over 700 ns
gc_conversion_time : natural := 100
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
d_o : out std_logic_vector(15 downto 0);
d_valid_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic
);
end ad7980_if;
architecture rtl of ad7980_if is
component spi_master
generic (
g_div_ratio_log2 : integer;
g_num_data_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
start_i : in std_logic;
cpol_i : in std_logic;
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
drdy_o : out std_logic;
ready_o : out std_logic;
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic);
end component;
signal count : unsigned(7 downto 0);
signal do_acq : std_logic;
type t_state is (WAIT_TRIG, START_CNV, READBACK);
signal state : t_state;
signal d_rdy : std_logic;
begin -- rtl
-- recieves spi data (mosi is not even connect)
-- it is always high because ADC uses it only as mode selector
-- AD7980 p17
U_SPI_Master : spi_master
generic map (
g_div_ratio_log2 => 3,
g_num_data_bits => 16)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
start_i => do_acq,
cpol_i => '0',
data_i => x"0000",
data_o => d_o,
drdy_o => d_rdy,
spi_sclk_o => adc_sck_o,
spi_miso_i => adc_sdo_i);
d_valid_o <= d_rdy;
adc_sdi_o <= '1';
-- sdi is high so ADC works in nCS mode
p_acquire : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= (others => '0');
adc_cnv_o <= '0';
do_acq <= '0';
state <= WAIT_TRIG;
else
case state is
when WAIT_TRIG =>
if(trig_i = '1') then
count <= (others => '0');
adc_cnv_o <= '1';
state <= START_CNV;
end if;
when START_CNV =>
count<= count +1;
if(count = gc_conversion_time ) then
adc_cnv_o <= '0';
do_acq <= '1';
state <= READBACK;
end if;
when READBACK =>
do_acq <= '0';
if(d_rdy = '1') then
state <= WAIT_TRIG;
end if;
end case;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dds_wbgen2_pkg.all;
use std.textio.all;
entity ad7980_if_sim is
-- when triggered sets CNV (conversion) high for gc_conversion_time
-- reads sample value (from SPI interface)
-- outputs sample value and confirms with data_valid
generic (
-- should be over 700 ns
gc_conversion_time : natural := 100
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
d_o : out std_logic_vector(15 downto 0) := (others => '0' );
d_valid_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic
);
end ad7980_if_sim;
architecture rtl of ad7980_if_sim is
component spi_master
generic (
g_div_ratio_log2 : integer;
g_num_data_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
start_i : in std_logic;
cpol_i : in std_logic;
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
drdy_o : out std_logic;
ready_o : out std_logic;
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic);
end component;
signal count : unsigned(7 downto 0);
signal do_acq : std_logic;
type t_state is (WAIT_TRIG, START_CNV, READBACK);
signal state : t_state;
signal adc_cnv_ob : std_logic;
signal adc_cnv_ob_prev : std_logic;
signal del_cnt_r : unsigned( 15 downto 0 );
signal d_rdy : std_logic;
begin -- rtl
-- recieves spi data (mosi is not even connect)
-- it is always high because ADC uses it only as mode selector
-- AD7980 p17
-- U_SPI_Master : spi_master
-- generic map (
-- g_div_ratio_log2 => 3,
-- g_num_data_bits => 16)
-- port map (
-- clk_sys_i => clk_i,
-- rst_n_i => rst_n_i,
-- start_i => do_acq,
-- cpol_i => '0',
-- data_i => x"0000",
-- data_o => d_o,
-- drdy_o => d_rdy,
-- spi_sclk_o => adc_sck_o,
-- spi_miso_i => adc_sdo_i);
reading : process( clk_i )
file infile : text is in "data.csv"; --declare input file
variable inline : line; --line number declaration
variable dataread : integer;
variable ret : boolean;
begin
if rising_edge( clk_i ) then
if ( adc_cnv_ob = '1' ) and (adc_cnv_ob_prev = '0') then
if( not endfile( infile ) ) then --checking the "END OF FILE" is not reached.
readline( infile, inline ); --reading a line from the file.
read( inline, dataread, ret ); --reading the data from the line and putting it in a real type variable.
d_o <= std_logic_vector( to_unsigned( dataread, 16 ) ); --put the value available in variable in a signal.
end if;
end if;
end if;
end process;
-- d_o <= std_logic_vector( to_unsigned( (2**15)-1, 16 ) );
-- d_rdy <= '1';
p_acquisition_del: process( clk_i, rst_n_i )
begin
if rst_n_i = '0' then
d_rdy <= '0';
del_cnt_r <= ( others => '0' );
adc_cnv_ob_prev <= '0';
elsif rising_edge( clk_i ) then
if ( adc_cnv_ob = '1' ) then
del_cnt_r <= ( others => '0' );
d_rdy <= '0';
else
if del_cnt_r < 16 then
del_cnt_r <= del_cnt_r + 1;
d_rdy <= '0';
elsif del_cnt_r = 16 then
del_cnt_r <= del_cnt_r + 1;
d_rdy <= '1';
else
d_rdy <= '0';
del_cnt_r <= del_cnt_r;
end if;
end if;
adc_cnv_ob_prev <= adc_cnv_ob;
end if;
end process;
adc_cnv_o <= adc_cnv_ob;
d_valid_o <= d_rdy;
adc_sdi_o <= '1';
-- sdi is high so ADC works in nCS mode
p_acquire : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= (others => '0');
adc_cnv_ob <= '0';
do_acq <= '0';
state <= WAIT_TRIG;
else
case state is
when WAIT_TRIG =>
if(trig_i = '1') then
count <= (others => '0');
adc_cnv_ob <= '1';
state <= START_CNV;
end if;
when START_CNV =>
count<= count +1;
if(count = gc_conversion_time ) then
adc_cnv_ob <= '0';
do_acq <= '1';
state <= READBACK;
end if;
when READBACK =>
do_acq <= '0';
if(d_rdy = '1') then
state <= WAIT_TRIG;
end if;
end case;
end if;
end if;
end process;
end rtl;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dds_control is
-- used in pts to control dds output
-- it enables changeing singal amplitude
-- and selecting between dds singal and constant value
generic(
data_len_g : natural := 16
);
port(
-- Clocks & resets
clk_i : in std_logic;
rst_n_i : in std_logic;
-- 01 means that scaled sine will be outputed
-- out <= ampl*in
-- 00 means that will output constant singnal
-- out <= ampl
-- 10 means that will output square singnal will be outputed
-- out <= 999 when ampl > max/2 else 0
type_i : in std_logic_vector( 1 downto 0);
-- enable/disable output signal
output_enable_i : in std_logic;
-- ampitude value
-- ffff = 1, ffff/x =1/x
amplitude_i : in std_logic_vector( data_len_g - 1 downto 0 );
-- dds signal input
input0_i : in std_logic_vector( data_len_g - 1 downto 0 );
input1_i : in std_logic_vector( data_len_g - 1 downto 0 );
input2_i : in std_logic_vector( data_len_g - 1 downto 0 );
input3_i : in std_logic_vector( data_len_g - 1 downto 0 );
-- scaled singal output
output0_o : out std_logic_vector( data_len_g - 1 downto 0 );
output1_o : out std_logic_vector( data_len_g - 1 downto 0 );
output2_o : out std_logic_vector( data_len_g - 1 downto 0 );
output3_o : out std_logic_vector( data_len_g - 1 downto 0 )
);
end dds_control;
architecture arch of dds_control is
type arr_t is array (0 to 3) of unsigned(data_len_g - 1 downto 0);
signal data_arr_i : arr_t;
signal data_scaled_r : arr_t;
signal data_final_r : arr_t;
signal amplitude_r : unsigned( data_len_g - 1 downto 0 );
signal type_r : std_logic_vector( 1 downto 0 );
signal output_enable_r : std_logic;
begin
-- type conversions
-- array creation (to simplify code)
data_arr_i( 0 ) <= unsigned( input0_i );
data_arr_i( 1 ) <= unsigned( input1_i );
data_arr_i( 2 ) <= unsigned( input2_i );
data_arr_i( 3 ) <= unsigned( input3_i );
-- convert to unsigned
-- makeing shure ampliture is latched with correct clock
conf_reg_sp : process( clk_i )
begin
if rising_edge( clk_i ) then
amplitude_r <= unsigned( amplitude_i );
type_r <= type_i;
output_enable_r <= output_enable_i;
end if;
end process;
-- scaleing of sine data
chanel_mult_gen: for i in 0 to 3 generate
begin
mult_sp: process( clk_i )
begin
if rising_edge( clk_i ) then
-- amplitude ffff should give signal value decremented by 1
-- amplitude ffff/2 sould give singal value divded by 2 decremented by 1
data_scaled_r( i ) <= resize( shift_right( data_arr_i( i ) * amplitude_r, data_len_g ), data_len_g ) ;
end if;
end process;
mux_sp: process( clk_i )
begin
if rising_edge( clk_i ) then
if output_enable_r = '0' then
data_final_r(i) <= ( others => '0' );
elsif type_r = "10" then
-- scaling error correction
data_final_r(i) <= data_scaled_r(i) + 1;
elsif type_r = "11" then
if data_arr_i(i)( data_len_g-1 ) = '1' then
data_final_r(i) <= amplitude_r;
else
data_final_r(i) <= (others => '0' );
end if;
else
data_final_r(i) <= amplitude_r;
end if;
end if;
end process;
end generate;
-- type conversions
output0_o <= std_logic_vector( data_final_r(0) );
output1_o <= std_logic_vector( data_final_r(1) );
output2_o <= std_logic_vector( data_final_r(2) );
output3_o <= std_logic_vector( data_final_r(3) );
end arch;
\ No newline at end of file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.dds_wbgen2_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.streamers_pkg.all;
entity dds_core_tb is
end dds_core_tb;
architecture arch of dds_core_tb is
component dds_core_sim
port (
-- Clocks & resets
clk_sys_i : in std_logic;
clk_dds_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
-- Timing (WRC)
tm_link_up_i : in std_logic := '1';
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
-- DDS Dac I/F (Maxim)
dac_n_o : out std_logic_vector(13 downto 0);
dac_p_o : out std_logic_vector(13 downto 0);
-- dac_pwdn_o : out std_logic;
-- AD9516 (SYS) and AD9510 (VCXO cleaner) PLL control
clk_dds_locked_i : in std_logic;
pll_vcxo_cs_n_o : out std_logic;
pll_vcxo_function_o : out std_logic;
pll_vcxo_sdo_i : in std_logic;
pll_vcxo_status_i : in std_logic;
pll_sys_cs_n_o : out std_logic;
-- pll_sys_refmon_i : in std_logic;
pll_sys_ld_i : in std_logic;
pll_sys_reset_n_o : out std_logic;
-- pll_sys_status_i : in std_logic;
pll_sys_sync_n_o : out std_logic;
pll_sclk_o : out std_logic;
pll_sdio_b : inout std_logic;
-- Phase Detector & ADC
-- pd_ce_o : out std_logic;
pd_lockdet_i : in std_logic;
pd_clk_o : out std_logic;
pd_data_b : inout std_logic;
pd_le_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic;
-- slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
-- snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
swrst_o : out std_logic;
fpll_reset_o : out std_logic
);
end component;
signal clk_ref : std_logic := '0';
signal clk_dds : std_logic := '0';
signal reset : std_logic := '1';
begin
p_clk_ref: process
begin
clk_ref <= not clk_ref;
wait for 8 ns;
end process;
p_clk_dds: process
begin
clk_dds <= not clk_dds;
wait for 2 ns;
end process;
p_rst: process
begin
reset <= '0';
wait for 100 ns;
reset <= '1';
wait for 100 ns;
reset <= '0';
wait;
end process;
cos: dds_core_sim
port map(
-- Clocks & resets
clk_sys_i => clk_ref,
clk_dds_i => clk_dds,
clk_ref_i => clk_ref,
rst_n_i => not reset,
-- Timing (WRC)
tm_link_up_i => '1',
tm_time_valid_i => '1',
tm_tai_i => ( others => '0' ),
tm_cycles_i => ( others => '0' ),
-- DDS Dac I/F (Maxim)
-- dac_n_o : out std_logic_vector(13 downto 0);
-- dac_p_o : out std_logic_vector(13 downto 0);
-- dac_pwdn_o : out std_logic;
-- AD9516 (SYS) and AD9510 (VCXO cleaner) PLL control
clk_dds_locked_i => '1',
-- pll_vcxo_cs_n_o : out std_logic;
-- pll_vcxo_function_o : out std_logic;
pll_vcxo_sdo_i => '1',
pll_vcxo_status_i => '1',
-- pll_sys_cs_n_o : out std_logic;
-- pll_sys_refmon_i : in std_logic;
pll_sys_ld_i => '1',
-- pll_sys_reset_n_o : out std_logic;
-- pll_sys_status_i : in std_logic;
-- pll_sys_sync_n_o : out std_logic;
-- pll_sclk_o : out std_logic;
-- pll_sdio_b : inout std_logic;
-- Phase Detector & ADC
-- pd_ce_o : out std_logic;
pd_lockdet_i => '1',
-- pd_clk_o : out std_logic;
-- pd_data_b : inout std_logic;
-- pd_le_o : out std_logic;
adc_sdo_i => '1'
-- adc_sck_o : out std_logic;
-- adc_cnv_o : out std_logic;
-- adc_sdi_o : out std_logic;
-- slave_i : in t_wishbone_slave_in;
-- slave_o : out t_wishbone_slave_out;
-- src_i : in t_wrf_source_in;
-- src_o : out t_wrf_source_out;
-- snk_i : in t_wrf_sink_in;
-- snk_o : out t_wrf_sink_out;
-- swrst_o : out std_logic;
-- fpll_reset_o : out std_logic
);
end arch;
\ No newline at end of file
`timescale 1ns/1ps
module dds_quad_channel
(
clk_i,
rst_n_i,
acc_i,
acc_o,
dreq_i,
tune_i,
tune_load_i,
acc_load_i,
y0_o,
y1_o,
y2_o,
y3_o);
parameter integer g_acc_frac_bits = 32;
parameter integer g_output_bits = 14;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
parameter integer g_lut_size_log2 = 10;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_lut_cell_size = g_lut_sample_bits + g_lut_slope_bits;
input clk_i;
input rst_n_i;
input acc_load_i;
input tune_load_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
output reg [g_acc_frac_bits + g_lut_size_log2 : 0] acc_o;
input [g_acc_frac_bits + g_lut_size_log2 : 0] tune_i;
input dreq_i;
output wire [g_output_bits-1:0] y0_o, y1_o, y2_o, y3_o;
wire [g_lut_size_log2-1:0] lut_addr[0:3];
reg [c_lut_cell_size-1:0] lut_data[0:3];
reg [c_acc_bits-1:0] acc, acc_d0, acc_f[0:3], tune;
wire [g_output_bits-1:0] y[0:3];
// tune seem to be phase step value
// acc would then be current phase value
always@(posedge clk_i)
begin
if(!rst_n_i)begin
tune <= 0;
acc <= 0;
end else begin
if(tune_load_i)
tune <= tune_i;
if(acc_load_i)
acc <= acc_i;
else if(dreq_i) begin
acc <= acc + tune;
acc_d0 <= acc;
acc_o <= acc;
// this core runs 1/4 of DDS DAC's frequency
// so phase is divided into 4 parts
// differing of 1/4 of tune step
// each subphase value is fed into separate dds channel
acc_f[0] <= acc_d0;
acc_f[1] <= acc_d0 + (tune >> 2);
acc_f[2] <= acc_d0 + (tune >> 1);
acc_f[3] <= acc_d0 + (tune >> 2) + (tune >> 1);
end
end // else: !if(!rst_n_i)
end // always@ (posedge clk_i)
generate
genvar i;
for(i=0;i<4;i=i+1)
begin
dds_stage
#(
.g_acc_frac_bits(g_acc_frac_bits),
.g_output_bits(g_output_bits),
.g_lut_size_log2(g_lut_size_log2),
.g_dither_init_value(i*1234567)
)
U_Stage_X
(
.clk_i(clk_i),
.rst_n_i(rst_n_i),
// current phase
.acc_i(acc_f[i]),
// signal output
.y_o(y[i]),
// looks lke module enable (allways active in this design)
.dreq_i(dreq_i),
// LUT input
.lut_addr_o(lut_addr[i]),
// LUT outpu
.lut_data_i(lut_data[i])
);
end // for (i=0;i<4;i++)
endgenerate
// two dimentional register declaration
// actually lut_init.v is 2 dimentional
// 1024 words of 36 bit
// these probably are 1024 samples with 36 bit precision
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut01[0:2**g_lut_size_log2-1];
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut23[0:2**g_lut_size_log2-1];
`include "lut_init.v"
// this is initialization of two LUT's
// one is called lut01 the other is lut23
// INIT_LUT( 01 ) seems to be a macro initializing lut01 register
// number is concatenated into name
initial begin
`INIT_LUT(01)
`INIT_LUT(23)
end
// there are 4 DDS channes
// this time there is copy paste insted of generate loop
always@(posedge clk_i)
lut_data[0] <= lut01[lut_addr[0]];
always@(posedge clk_i)
lut_data[1] <= lut01[lut_addr[1]];
always@(posedge clk_i)
lut_data[2] <= lut23[lut_addr[2]];
always@(posedge clk_i)
lut_data[3] <= lut23[lut_addr[3]];
// vector assigned to non vector output
assign y0_o = y[0];
assign y1_o = y[1];
assign y2_o = y[2];
assign y3_o = y[3];
endmodule // dds_quad_channel
\ No newline at end of file
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`timescale 1ns/1ps
module dds_single_channel
(
clk_i,
rst_n_i,
acc_load_i,
tune_load_i,
acc_i,
tune_i,
dreq_i,
y_o,
lut_addr_o,
lut_data_i
);
parameter integer g_acc_frac_bits = 32;
parameter integer g_dither_init_value = 32'h00000001;
parameter integer g_output_bits = 12;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
parameter integer g_lut_size_log2 = 12;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
localparam c_dither_bits = (g_lut_sample_bits - g_output_bits - 1);
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_output_shift = g_lut_sample_bits - g_output_bits;
wire signed [c_dither_bits :0 ] dither_in;
input clk_i;
input rst_n_i;
input acc_load_i;
input tune_load_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] tune_i;
input dreq_i;
output reg [g_output_bits-1:0] y_o;
output reg [g_lut_size_log2-1:0] lut_addr_o;
input [g_lut_sample_bits + g_lut_slope_bits - 1:0] lut_data_i;
reg [c_acc_bits-1:0] acc0, acc1, tune;
wire [g_lut_size_log2 : 0] phase;
wire [g_lut_slope_bits-1 : 0] frac;
reg [g_lut_slope_bits-1 : 0] frac_d0, frac_d1, frac_d2, frac_d3;
wire half;
reg [g_lut_size_log2-1:0] addr0, addr1,tmp,tmp2,tmp3;
reg [8:0] sign;
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut_in;
wire signed [g_lut_slope_bits-1:0] lut_slope;
reg signed [g_lut_slope_bits-1:0] slope_d0;
wire signed [g_lut_sample_bits-1:0] lut_sample;
reg signed [g_lut_sample_bits-1:0] sample_d0;
reg signed [g_lut_sample_bits-1:0] interp, interp_d0;
reg signed [g_lut_sample_bits-1:0] qv;
reg signed [g_output_bits:0] yt;
wire signed [2*g_lut_slope_bits-1:0] interp_mul;
reg [g_dither_length-1:0] lfsr=g_dither_init_value;
assign lut_slope = lut_in[g_lut_sample_bits + g_lut_slope_bits - 1 : g_lut_sample_bits ];
assign lut_sample = lut_in[g_lut_sample_bits - 1 : 0];
assign phase = acc1 [ g_acc_frac_bits + g_lut_size_log2 - 1 : g_acc_frac_bits - 1];
assign half = acc1 [g_acc_frac_bits + g_lut_size_log2];
assign frac = acc1 [g_acc_frac_bits - 1 : g_acc_frac_bits-g_lut_slope_bits];
always@(posedge clk_i)
begin
if (!rst_n_i) begin
lfsr <= g_dither_init_value;
end else if (dreq_i) begin
if(lfsr[0])
lfsr <= {1'b0, lfsr[g_dither_length-1:1]} ^ g_dither_taps;
else
lfsr <= {1'b0, lfsr[g_dither_length-1:1]};
end
end
assign dither_in = { lfsr[c_dither_bits+4:5], 1'b0 };
assign interp_mul = signed'(lut_slope) * signed'({1'b0, frac_d3});
always@(posedge clk_i)
begin
if (!rst_n_i) begin
acc0 <= 0;
acc1 <= 0;
tune <= 0;
end else begin
if(tune_load_i)
tune <= tune_i;
if(acc_load_i)
acc0 <= acc_i;
if(dreq_i) begin
acc0 <= acc0 + tune;
acc1 <= acc0;
addr0 <= acc1[g_acc_frac_bits + g_lut_size_log2-1 : g_acc_frac_bits];
sign <= {sign[7:0], half };
lut_addr_o <= addr0;
lut_in <= lut_data_i;
frac_d0 <= frac;
frac_d1 <= frac_d0;
frac_d2 <= frac_d1;
frac_d3 <= frac_d2;
interp <= interp_mul >>> (g_lut_slope_bits + g_interp_shift);
sample_d0 <= lut_sample;
qv <= signed'(sample_d0) + signed'(interp) + signed'(dither_in) + 1;
if(sign[5])
yt <= qv >>> (c_output_shift-1);
else
yt <= (-qv) >>> (c_output_shift-1);
if(yt[0])
y_o <= yt[g_output_bits:1] + 1;
else
y_o <= yt[g_output_bits:1];
end
end // else: !if(!rst_n_i)
end // always@ (posedge clk_i)
endmodule // dds_single_channel
This diff is collapsed.
`timescale 1ns/1ps
module dds_stage
(
clk_i,
rst_n_i,
acc_i,
dreq_i,
y_o,
lut_addr_o,
lut_data_i
);
//32
parameter integer g_acc_frac_bits = 32;
// different for each channel
parameter integer g_dither_init_value = 32'h00000001;
// overwriten by 14
parameter integer g_output_bits = 12;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
// 10
parameter integer g_lut_size_log2 = 12;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
// 18 - 12 - 1 =5
localparam c_dither_bits = (g_lut_sample_bits - g_output_bits - 1);
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_output_shift = g_lut_sample_bits - g_output_bits;
wire signed [c_dither_bits :0 ] dither_in;
input clk_i;
input rst_n_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
input dreq_i;
output reg [g_output_bits-1:0] y_o;
output reg [g_lut_size_log2-1:0] lut_addr_o;
input [g_lut_sample_bits + g_lut_slope_bits - 1:0] lut_data_i;
reg [c_acc_bits-1:0] acc0, acc1, tune;
wire [g_lut_size_log2 : 0] phase;
wire [g_lut_slope_bits-1 : 0] frac;
reg [g_lut_slope_bits-1 : 0] frac_d0, frac_d1, frac_d2, frac_d3;
wire half;
reg [g_lut_size_log2-1:0] addr0, addr1,tmp,tmp2,tmp3;
reg [8:0] sign;
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut_in;
wire signed [g_lut_slope_bits-1:0] lut_slope;
reg signed [g_lut_slope_bits-1:0] slope_d0;
wire signed [g_lut_sample_bits-1:0] lut_sample;
reg signed [g_lut_sample_bits-1:0] sample_d0;
reg signed [g_lut_sample_bits-1:0] interp, interp_d0;
reg signed [g_lut_sample_bits-1:0] qv;
reg signed [g_output_bits:0] yt;
wire signed [2*g_lut_slope_bits-1:0] interp_mul;
reg [g_dither_length-1:0] lfsr=g_dither_init_value;
// values stored in lut are made of
// lut_in [ 18 + 18 - 1 : 18 ] => lut_in[ 36 - 1 : 18 ]
// that is 18 bit value
assign lut_slope = lut_in[g_lut_sample_bits + g_lut_slope_bits - 1 : g_lut_sample_bits ];
// lut_in [ 18 - 1 : 0 ]
// that is 18 bit value
assign lut_sample = lut_in[g_lut_sample_bits - 1 : 0];
// phase is part of acc value?
// not used in this core anyway
// phase = acc[18+10 : 18 - 1 ] = acc[ 28 : 17 ]
// looks strange since lowest bit of this vector is also used as highest bit of frac vector
assign phase = acc_i [ g_acc_frac_bits + g_lut_size_log2 - 1 : g_acc_frac_bits - 1];
// highest bit (32+10 = 42)
// something like sign flag
assign half = acc_i [g_acc_frac_bits + g_lut_size_log2];
// frac = acc[ 18-1 : 18 - 10 ] = acc[ 17 : 8 ] (10 bit)
assign frac = acc_i [g_acc_frac_bits - 1 : g_acc_frac_bits-g_lut_slope_bits];
// lfsr
// shifted when dreq_i is active
always@(posedge clk_i)
begin
if (!rst_n_i) begin
lfsr <= g_dither_init_value;
end else if (dreq_i) begin
if(lfsr[0])
lfsr <= {1'b0, lfsr[g_dither_length-1:1]} ^ g_dither_taps;
else
lfsr <= {1'b0, lfsr[g_dither_length-1:1]};
end
end
wire signed [g_lut_slope_bits:0] interp_frac;
// leading zero added to delayed frac
// this value represents phase value with accuracy bigger then sampling period
// it is delayed lsb part of phase acc
assign interp_frac = {1'b0, frac_d3};
// 5+4:5 = 9:5
// czesc zawartosci LFSR
// dither is random noise added to phase to randomize quantization noise
assign dither_in = { lfsr[c_dither_bits+4:5], 1'b0 };
// lut_in[ 36 - 1 : 18 ] * acc[ 17 : 8 ]
// interpolation of signal value in high precision phase
// lut slope is lsb part of lut value and seems to be coefficient a from y=ax+b
// in this case lut_sample would be b
// interp_frac would be x
assign interp_mul = lut_slope * interp_frac;
always@(posedge clk_i)
begin
if (!rst_n_i) begin
end else if(dreq_i) begin
// msb part of acc is adressing lut
addr0 <= acc_i[g_acc_frac_bits + g_lut_size_log2-1 : g_acc_frac_bits];
// delay
sign <= {sign[7:0], half };
lut_addr_o <= addr0;
lut_in <= lut_data_i;
// more accurate phase part
frac_d0 <= frac;
frac_d1 <= frac_d0;
frac_d2 <= frac_d1;
frac_d3 <= frac_d2;
// shift by 18+7=25 bits
interp <= interp_mul >>> (g_lut_slope_bits + g_interp_shift);
// lut_in [ 18 - 1 : 0 ]
sample_d0 <= lut_sample;
// final signal value is:
// sample_d0 - sampled value read from LUT
// interp - interpolated value (higher resolution)
// dither - random value added to randomize noise
qv <= (sample_d0) + (interp) + (dither_in) + 1;
// probably if sample was negative then this result is also negated
if(sign[5])
yt <= qv >>> (c_output_shift-1);
else
yt <= (-qv) >>> (c_output_shift-1);
if(yt[0])
y_o <= (yt[g_output_bits:1] + (1<<(g_output_bits - 1)) + 1);
else
y_o <= (yt[g_output_bits:1] + (1<<(g_output_bits - 1)));
end // if (dreq_i)
end // always@ (posedge clk_i)
endmodule // dds_single_channel
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity detect_periodic is
-- used in pts to acquire dividers outputs for PD test
generic(
data_len_g : natural := 16
);
port(
-- Clocks & resets
clk_i : in std_logic;
rst_n_i : in std_logic;
-- PD Lock Detect line
signal_i : in std_logic;
-- measured period (Dividers should give periodic pulses)
period_en_o : out std_logic;
period_o : out std_logic_vector( data_len_g - 1 downto 0 )
);
end detect_periodic;
architecture arch of detect_periodic is
constant shr_len_c : natural := 8;
signal signal_shr : std_logic_vector( shr_len_c - 1 downto 0 );
signal cnt_r : unsigned( data_len_g - 1 downto 0 );
signal buffer_r : unsigned( data_len_g - 1 downto 0 );
signal buffer_en_r : std_logic;
begin
period_o <= std_logic_vector( buffer_r );
period_en_o <= buffer_en_r;
shift_reg_sh: process( clk_i, rst_n_i )
begin
if rising_edge( clk_i ) then
if rst_n_i = '0' then
signal_shr <= ( others => '0' );
else
for i in shr_len_c - 1 downto 1 loop
signal_shr(i) <= signal_shr( i - 1 );
end loop;
signal_shr( 0 ) <= signal_i;
end if;
end if;
end process;
cnt_sp : process( clk_i, rst_n_i )
begin
if rising_edge( clk_i ) then
if rst_n_i = '0' then
cnt_r <= ( others => '0' );
buffer_r <= ( others => '0' );
buffer_en_r <= '0';
else
if ( signal_shr( shr_len_c - 1 ) = '0' ) and ( signal_shr( shr_len_c - 2 ) = '1' ) then
cnt_r <= ( others => '0' );
buffer_r <= cnt_r;
buffer_en_r <= '1';
else
cnt_r <= cnt_r + 1;
buffer_r <= buffer_r;
buffer_en_r <= '0';
end if;
end if;
end if;
end process;
end arch;
\ No newline at end of file
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files = [ "xtx_streamer.vhd", "tx_streamer.vhd", "xrx_streamer.vhd", "rx_streamer.vhd", "gc_escape_inserter.vhd", "gc_escape_detector.vhd", "dropping_buffer.vhd","streamers_pkg.vhd" ]
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scripts/wbscript.sh
\ No newline at end of file
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action= "simulation"
target= "xilinx"
fetchto="../../ip_cores"
modules = { "local" : [ "../../rtl" ] }
files = ["main.sv"]
vlog_opt="+incdir+../../sim"
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-0.00038385 -0.0013273 -0.0015635 0.00091054 0.0047773 0.0039991 -0.0042284 -0.010424 -0.001365 0.016826 0.01661 -0.013276 -0.036778 -0.0081087 0.051718 0.054753 -0.038602 -0.12613 -0.049535 0.20453 0.43998 0.43998 0.20453 -0.049535 -0.12613 -0.038602 0.054753 0.051718 -0.0081087 -0.036778 -0.013276 0.01661 0.016826 -0.001365 -0.010424 -0.0042284 0.0039991 0.0047773 0.00091054 -0.0015635 -0.0013273 -0.00038385
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files = ["mem_model.vhd", "textutil.vhd", "gn412x_bfm.vhd", "util.vhd"]
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