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fmc dac 600m 12b 1cha dds - Testing
Commit 410ac7fe authored by Mariusz Mroz's avatar Mariusz Mroz
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Production Test Suite for the fmc-dac-600m-12b-1cha board. Initial version.

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.cproject 0 → 100644
View file @ 410ac7fe
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="cdt.managedbuild.toolchain.gnu.base.220778561">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.toolchain.gnu.base.220778561" moduleId="org.eclipse.cdt.core.settings" name="Default">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration buildProperties="" id="cdt.managedbuild.toolchain.gnu.base.220778561" name="Default" parent="org.eclipse.cdt.build.core.emptycfg">
<folderInfo id="cdt.managedbuild.toolchain.gnu.base.220778561.395404604" name="/" resourcePath="">
<toolChain id="cdt.managedbuild.toolchain.gnu.base.1790678908" name="Linux GCC" superClass="cdt.managedbuild.toolchain.gnu.base">
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="cdt.managedbuild.target.gnu.platform.base.1438761549" name="Debug Platform" osList="linux,hpux,aix,qnx" superClass="cdt.managedbuild.target.gnu.platform.base"/>
<builder id="cdt.managedbuild.target.gnu.builder.base.383187502" managedBuildOn="false" name="Gnu Make Builder.Default" superClass="cdt.managedbuild.target.gnu.builder.base"/>
<tool id="cdt.managedbuild.tool.gnu.archiver.base.842859648" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.base.1915739877" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.base"/>
<tool id="cdt.managedbuild.tool.gnu.c.compiler.base.973137689" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.base"/>
<tool id="cdt.managedbuild.tool.gnu.c.linker.base.1450756394" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.linker.base.1046795642" name="GCC C++ Linker" superClass="cdt.managedbuild.tool.gnu.cpp.linker.base"/>
<tool id="cdt.managedbuild.tool.gnu.assembler.base.1378844240" name="GCC Assembler" superClass="cdt.managedbuild.tool.gnu.assembler.base"/>
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</folderInfo>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="pts_dds.null.1344061833" name="pts_dds"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
</cproject>
.gitignore 0 → 100644
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*.*\#
\#*
.\#*
*.*~
gateware/syn/*
!gateware/syn/*.xise
!gateware/syn/*.bin
!gateware/syn/*.bit
!gateware/syn/fpga_xst.bmm
gateware/ip_cores/debug/*
!gateware/ip_cores/debug/*.vhd
!gateware/ip_cores/debug/*.ngc
work
*.wlf
modelsim.ini
transcript
*.vstf
*.bak
*.vcd
#*.h
doc/*.pdf
*.o
*.so
*.pyc
*.elf
output
software/rf-test
*.png
*.odt.saved
python/sdbfs/IPMI-FRU
\ No newline at end of file
.gitmodules 0 → 100644
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[submodule "gateware/ip_cores/wr-cores"]
path = gateware/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "gateware/ip_cores/general-cores"]
path = gateware/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "gateware/ip_cores/gn4124-core"]
path = gateware/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "software/wrpc-sw"]
path = software/wrpc-sw
url = git://ohwr.org/hdl-core-lib/wr-cores/wrpc-sw.git
[submodule "gateware/ip_cores/etherbone-core"]
path = gateware/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
.project 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>pts_dds</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>
LICENSE 0 → 100644
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WR RF Distribution Demo
Tomasz Wlostowski/CERN BE-CO-HT 2013
---------------------------------------
(c) Copyright CERN 2013
All of the code in this repository is licensed under GNU General Public License version 2 unless otherwise
stated in the file headers.
\ No newline at end of file
fmcdac600m12b1chadds.sh 0 → 100644
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#!/bin/bash
echo "WARRNING!!!"
echo "errors indicating that modules are not loaded should be ignored"
echo "i.e: rmmod: \"ERROR: Module fmc_adc_100m14b is not currently loaded\" should be ignored"
rmmod fmc_adc_100m14b > /dev/null
rmmod zio > /dev/null
rmmod rawrabbit > /dev/null
rmmod spec > /dev/null
rmmod fmc > /dev/null
modprobe usbserial
rmmod cp210x
rmmod usbtmc
prg=$0
if [ ! -e "$prg" ]; then
case $prg in
(*/*) exit 1;;
(*) prg=$(command -v -- "$prg") || exit;;
esac
fi
dir=$(
cd -P -- "$(dirname -- "$prg")" && pwd -P
) || exit
prg=$dir/$(basename -- "$prg") || exit
top=`echo "$prg" | sed 's/pts.*/pts\//'`
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-bus/kernel/fmc.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/spec-sw/kernel/spec.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/zio/zio.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko"
insmod "$top/cp210x/cp210x.ko"
# "$top/usbdriver/usbtmc_load"
LOGDIR="$top/log_fmcdac600m12b1chadds"
mkdir -p "$LOGDIR"
mkdir -p "$LOGDIR/eeprom"
# sudo rm -fr $LOGDIR/pts*
serial=$1
if [ x$1 = x"" ]; then
echo -n "Please scan CERN serial number bar-code, then press [ENTER]: "
read serial
fi
if [ x$serial = x"" ]; then
serial=0000
fi
extra_serial=$2
if [ x$2 = x"" ]; then
echo -n "If needed input extra serial number and press [ENTER] OR just press [ENTER]: "
read extra_serial
fi
if [ x$extra_serial = x"" ]; then
extra_serial=0000
fi
echo " "
nb_test_limit=2
nb_test=1
while [ "$nb_test" -le "$nb_test_limit" ]
do
echo "--------------------------------------------------------------"
echo "Test series run $nb_test out of $nb_test_limit"
echo " "
# sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 02 03 04 05 06 07
sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 03 04 05 06 07
if [ "$nb_test" != "$nb_test_limit" ]
then
echo " "
echo -n "Do you want to run the test series again [y,n]? "
read reply
if [ "$reply" != "y" ]
then
break
fi
fi
nb_test=$(($nb_test+1))
done
echo "--------------------------------------------------------------"
echo " "
echo -n "End of the test, do you want to switch the computer OFF? [y,n]"
read reply
if [ "$reply" = "y" ]
then
sudo halt
fi
fmcdds.sh 0 → 100644
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#!/bin/bash
echo "WARRNING!!!"
echo "errors indicating that modules are not loaded should be ignored"
echo "i.e: rmmod: \"ERROR: Module fmc_adc_100m14b is not currently loaded\" should be ignored"
rmmod fmc_adc_100m14b > /dev/null
rmmod zio > /dev/null
rmmod rawrabbit > /dev/null
rmmod spec > /dev/null
rmmod fmc > /dev/null
modprobe usbserial
rmmod cp210x
rmmod usbtmc
prg=$0
if [ ! -e "$prg" ]; then
case $prg in
(*/*) exit 1;;
(*) prg=$(command -v -- "$prg") || exit;;
esac
fi
dir=$(
cd -P -- "$(dirname -- "$prg")" && pwd -P
) || exit
prg=$dir/$(basename -- "$prg") || exit
top=`echo "$prg" | sed 's/pts.*/pts\//'`
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-bus/kernel/fmc.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/spec-sw/kernel/spec.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/zio/zio.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko"
insmod "$top/cp210x/cp210x.ko"
# "$top/usbdriver/usbtmc_load"
LOGDIR="$top/log_fmcdac600m12b1chadds"
mkdir -p "$LOGDIR"
mkdir -p "$LOGDIR/eeprom"
# sudo rm -fr $LOGDIR/pts*
serial=$1
if [ x$1 = x"" ]; then
echo -n "Please scan CERN serial number bar-code, then press [ENTER]: "
read serial
fi
if [ x$serial = x"" ]; then
serial=0000
fi
extra_serial=$2
if [ x$2 = x"" ]; then
echo -n "If needed input extra serial number and press [ENTER] OR just press [ENTER]: "
read extra_serial
fi
if [ x$extra_serial = x"" ]; then
extra_serial=0000
fi
echo " "
nb_test_limit=2
nb_test=1
while [ "$nb_test" -le "$nb_test_limit" ]
do
echo "--------------------------------------------------------------"
echo "Test series run $nb_test out of $nb_test_limit"
echo " "
# sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 02 03 04 05 06 07
sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 03 04 05 06 07
if [ "$nb_test" != "$nb_test_limit" ]
then
echo " "
echo -n "Do you want to run the test series again [y,n]? "
read reply
if [ "$reply" != "y" ]
then
break
fi
fi
nb_test=$(($nb_test+1))
done
echo "--------------------------------------------------------------"
echo " "
echo -n "End of the test, do you want to switch the computer OFF? [y,n]"
read reply
if [ "$reply" = "y" ]
then
sudo halt
fi
gateware/ip_cores/debug/chipscope_icon.ngc 0 → 100644
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gateware/ip_cores/debug/chipscope_icon.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon.vhd
-- /___/ /\ Timestamp : czw lut 12 16:53:28 CET 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon IS
port (
CONTROL0: inout std_logic_vector(35 downto 0));
END chipscope_icon;
ARCHITECTURE chipscope_icon_a OF chipscope_icon IS
BEGIN
END chipscope_icon_a;
gateware/ip_cores/debug/chipscope_icon2.ngc 0 → 100644
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gateware/ip_cores/debug/chipscope_icon2.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon2.vhd
-- /___/ /\ Timestamp : śro kwi 08 13:56:51 CEST 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon2 IS
port (
CONTROL0: inout std_logic_vector(35 downto 0));
END chipscope_icon2;
ARCHITECTURE chipscope_icon2_a OF chipscope_icon2 IS
BEGIN
END chipscope_icon2_a;
gateware/ip_cores/debug/chipscope_ila.ngc 0 → 100644
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gateware/ip_cores/debug/chipscope_ila.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila.vhd
-- /___/ /\ Timestamp : czw lut 12 16:52:44 CET 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(63 downto 0));
END chipscope_ila;
ARCHITECTURE chipscope_ila_a OF chipscope_ila IS
BEGIN
END chipscope_ila_a;
gateware/ip_cores/debug/chipscope_ila2.ngc 0 → 100644
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gateware/ip_cores/debug/chipscope_ila2.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila2.vhd
-- /___/ /\ Timestamp : śro kwi 08 13:58:49 CEST 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila2 IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(191 downto 0));
END chipscope_ila2;
ARCHITECTURE chipscope_ila2_a OF chipscope_ila2 IS
BEGIN
END chipscope_ila2_a;
gateware/rtl/Manifest.py 0 → 100644
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files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd","dds_tx_path.vhd","dds_rx_path.vhd","timestamp_compare.vhd","pll_init.v" ]
modules = {"local":"streamers"}