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fmc dac 600m 12b 1cha dds - Testing
Commit 0f8328d6 authored by Mariusz Mroz's avatar Mariusz Mroz
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Fix missing files and modules

parent 40a16639
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Showing with 937 additions and 1039 deletions
.gitmodules
View file @ 0f8328d6
......@@ -13,7 +13,6 @@
[submodule "gateware/ip_cores/etherbone-core"]
path = gateware/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "software/fpga-config-space"]
path = software/fpga-config-space
url = git://ohwr.org/hdl-core-lib/fpga-config-space.git
drivers_test.sh 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
fmcdac600m12b1chadds.sh 100644 → 100755
View file @ 0f8328d6
......@@ -75,7 +75,7 @@ do
echo " "
# sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 02 03 04 05 06 07
sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 03 04 05 06 07
sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 02 03 04 05 06 07
if [ "$nb_test" != "$nb_test_limit" ]
......
fmcdds.sh deleted 100644 → 0
View file @ 40a16639
#!/bin/bash
echo "WARRNING!!!"
echo "errors indicating that modules are not loaded should be ignored"
echo "i.e: rmmod: \"ERROR: Module fmc_adc_100m14b is not currently loaded\" should be ignored"
rmmod fmc_adc_100m14b > /dev/null
rmmod zio > /dev/null
rmmod rawrabbit > /dev/null
rmmod spec > /dev/null
rmmod fmc > /dev/null
modprobe usbserial
rmmod cp210x
rmmod usbtmc
prg=$0
if [ ! -e "$prg" ]; then
case $prg in
(*/*) exit 1;;
(*) prg=$(command -v -- "$prg") || exit;;
esac
fi
dir=$(
cd -P -- "$(dirname -- "$prg")" && pwd -P
) || exit
prg=$dir/$(basename -- "$prg") || exit
top=`echo "$prg" | sed 's/pts.*/pts\//'`
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-bus/kernel/fmc.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/spec-sw/kernel/spec.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/zio/zio.ko"
insmod "$top/test/fmcdac600m12b1chadds/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko"
insmod "$top/cp210x/cp210x.ko"
# "$top/usbdriver/usbtmc_load"
LOGDIR="$top/log_fmcdac600m12b1chadds"
mkdir -p "$LOGDIR"
mkdir -p "$LOGDIR/eeprom"
# sudo rm -fr $LOGDIR/pts*
serial=$1
if [ x$1 = x"" ]; then
echo -n "Please scan CERN serial number bar-code, then press [ENTER]: "
read serial
fi
if [ x$serial = x"" ]; then
serial=0000
fi
extra_serial=$2
if [ x$2 = x"" ]; then
echo -n "If needed input extra serial number and press [ENTER] OR just press [ENTER]: "
read extra_serial
fi
if [ x$extra_serial = x"" ]; then
extra_serial=0000
fi
echo " "
nb_test_limit=2
nb_test=1
while [ "$nb_test" -le "$nb_test_limit" ]
do
echo "--------------------------------------------------------------"
echo "Test series run $nb_test out of $nb_test_limit"
echo " "
# sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 02 03 04 05 06 07
sudo ./ptsDacDDS.py -b FmcDac600m12b1chaDds -s $serial -e $extra_serial -t./test/fmcdac600m12b1chadds/python -l $LOGDIR 00 01 03 04 05 06 07
if [ "$nb_test" != "$nb_test_limit" ]
then
echo " "
echo -n "Do you want to run the test series again [y,n]? "
read reply
if [ "$reply" != "y" ]
then
break
fi
fi
nb_test=$(($nb_test+1))
done
echo "--------------------------------------------------------------"
echo " "
echo -n "End of the test, do you want to switch the computer OFF? [y,n]"
read reply
if [ "$reply" = "y" ]
then
sudo halt
fi
etherbone-core @ c1e676dc
Subproject commit c1e676dc9d35028910c50431d70328e522396c89
general-cores @ 97bc7197
Subproject commit 97bc71975252b32cf8a47ba895f7010734f015e5
gn4124-core @ ffea5479
Subproject commit ffea5479190c09938cbba9b7076953c5c41645f3
wr-cores @ 598a2f6c
Subproject commit 598a2f6ccbf1ac937ff589c0797cd2a487306efe
gateware/rtl/wbscript.sh deleted 100644 → 0
View file @ 40a16639
scripts/wbscript.sh
\ No newline at end of file
gateware/rtl/wbscript.sh 0 → 120000
View file @ 0f8328d6
scripts/wbscript.sh
\ No newline at end of file
gateware/sw2bit.sh 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
gateware/syn/fpga_xst.bmm
View file @ 0f8328d6
/* FILE : fpga.bmm
* Define a BRAM map for the LM32 memory "xwb_dpram".
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory "xwb_dpram"
* g_dpram_size = 90112/4 = 22528
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
*
* ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command
* "data2mem -bm fpga_bd.bmm -bt fpga_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
*
* 131072 / 2048 = 64 blocks
****************************************************************************************/
ADDRESS_SPACE ram RAMB16 [0x00000000:0x0001FFFF]
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram21 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram22 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram23 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram24 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram25 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram26 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram27 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram28 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram29 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram30 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram31 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram32 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram33 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram34 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram35 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram36 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram37 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram38 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram39 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram40 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram41 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram42 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram43 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram44 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram45 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram46 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram47 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram48 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram49 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram50 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram51 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram52 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram53 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram54 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram55 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram56 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram57 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram58 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram59 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram60 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram61 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram62 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram63 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram64 [31:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
/* FILE : fpga.bmm
* Define a BRAM map for the LM32 memory "xwb_dpram".
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory "xwb_dpram"
* g_dpram_size = 90112/4 = 22528
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
*
* ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command
* "data2mem -bm fpga_bd.bmm -bt fpga_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
*
* 131072 / 2048 = 64 blocks
****************************************************************************************/
ADDRESS_SPACE ram RAMB16 [0x00000000:0x0001FFFF]
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram21 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram22 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram23 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram24 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram25 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram26 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram27 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram28 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram29 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram30 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram31 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram32 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram33 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram34 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram35 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram36 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram37 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram38 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram39 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram40 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram41 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram42 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram43 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram44 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram45 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram46 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram47 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram48 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram49 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram50 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram51 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram52 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram53 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram54 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram55 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram56 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram57 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram58 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram59 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram60 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram61 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram62 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram63 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram64 [31:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
gateware/testbench/mdsp/dsp.py 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
ptsDacDDS.py 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
python/acq.sh 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
python/find_usb_tty.py 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
python/fmc_eeprom.py 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
python/test06.py 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
scripts/ad9510_testconf.py
View file @ 0f8328d6
[0x00, 0x10],
[0x02, 0x20],
[0x04, 0x00],
[0x05, 0x00],
[0x06, 0x19],
[0x07, 0x04],
[0x08, 0x45],
[0x09, 0x30],
[0x0A, 0x06],
[0x0B, 0x00],
[0x0C, 0x01],
[0x0D, 0x20],
[0x34, 0x01],
[0x35, 0x00],
[0x36, 0x00],
[0x37, 0x04],
[0x38, 0x01],
[0x39, 0x00],
[0x3A, 0x00],
[0x3B, 0x04],
[0x3C, 0x08],
[0x3D, 0x0B],
[0x3E, 0x0B],
[0x3F, 0x08],
[0x40, 0x03],
[0x41, 0x03],
[0x42, 0x00],
[0x43, 0x03],
[0x44, 0x13],
[0x45, 0x00],
[0x48, 0x00],
[0x49, 0x00],
[0x4A, 0x00],
[0x4B, 0x00],
[0x4C, 0x11],
[0x4D, 0x00],
[0x4E, 0x44],
[0x4F, 0x00],
[0x50, 0x00],
[0x51, 0x00],
[0x52, 0x11],
[0x53, 0x00],
[0x54, 0x44],
[0x55, 0x00],
[0x56, 0x00],
[0x57, 0x00],
[0x58, 0x00],
[0x59, 0x00],
[0x5A, 0x00],
[0x00, 0x10],
[0x02, 0x20],
[0x04, 0x00],
[0x05, 0x00],
[0x06, 0x19],
[0x07, 0x04],
[0x08, 0x45],
[0x09, 0x30],
[0x0A, 0x06],
[0x0B, 0x00],
[0x0C, 0x01],
[0x0D, 0x20],
[0x34, 0x01],
[0x35, 0x00],
[0x36, 0x00],
[0x37, 0x04],
[0x38, 0x01],
[0x39, 0x00],
[0x3A, 0x00],
[0x3B, 0x04],
[0x3C, 0x08],
[0x3D, 0x0B],
[0x3E, 0x0B],
[0x3F, 0x08],
[0x40, 0x03],
[0x41, 0x03],
[0x42, 0x00],
[0x43, 0x03],
[0x44, 0x13],
[0x45, 0x00],
[0x48, 0x00],
[0x49, 0x00],
[0x4A, 0x00],
[0x4B, 0x00],
[0x4C, 0x11],
[0x4D, 0x00],
[0x4E, 0x44],
[0x4F, 0x00],
[0x50, 0x00],
[0x51, 0x00],
[0x52, 0x11],
[0x53, 0x00],
[0x54, 0x44],
[0x55, 0x00],
[0x56, 0x00],
[0x57, 0x00],
[0x58, 0x00],
[0x59, 0x00],
[0x5A, 0x00],
scripts/ad9510conf11.txt
View file @ 0f8328d6
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00011001","19"
"07","00000100","04"
"08","01000101","45"
"09","00110000","30"
"0A","00000110","06"
"0B","00000000","00"
"0C","00000001","01"
"0D","00100000","20"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001000","08"
"3D","00001011","0B"
"3E","00001011","0B"
"3F","00001000","08"
"40","00000011","03"
"41","00000011","03"
"42","00000000","00"
"43","00000011","03"
"44","00010011","13"
"45","00000000","00"
"48","00000000","00"
"49","00000000","00"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","01000100","44"
"4F","00000000","00"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","01000100","44"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",10
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00011001","19"
"07","00000100","04"
"08","01000101","45"
"09","00110000","30"
"0A","00000110","06"
"0B","00000000","00"
"0C","00000001","01"
"0D","00100000","20"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001000","08"
"3D","00001011","0B"
"3E","00001011","0B"
"3F","00001000","08"
"40","00000011","03"
"41","00000011","03"
"42","00000000","00"
"43","00000011","03"
"44","00010011","13"
"45","00000000","00"
"48","00000000","00"
"49","00000000","00"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","01000100","44"
"4F","00000000","00"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","01000100","44"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",10
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
scripts/ad9510conf3.txt
View file @ 0f8328d6
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00011001","19"
"07","00000000","00"
"08","01000101","45"
"09","00110000","30"
"0A","00000110","06"
"0B","00000000","00"
"0C","00000001","01"
"0D","00100000","20"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001000","08"
"3D","00001011","0B"
"3E","00001011","0B"
"3F","00001000","08"
"40","00000011","03"
"41","00000011","03"
"42","00000000","00"
"43","00000011","03"
"44","00010011","13"
"45","00000000","00"
"48","00000000","00"
"49","00000000","00"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","01000100","44"
"4F","00000000","00"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","01000100","44"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",10
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00011001","19"
"07","00000000","00"
"08","01000101","45"
"09","00110000","30"
"0A","00000110","06"
"0B","00000000","00"
"0C","00000001","01"
"0D","00100000","20"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001000","08"
"3D","00001011","0B"
"3E","00001011","0B"
"3F","00001000","08"
"40","00000011","03"
"41","00000011","03"
"42","00000000","00"
"43","00000011","03"
"44","00010011","13"
"45","00000000","00"
"48","00000000","00"
"49","00000000","00"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","01000100","44"
"4F","00000000","00"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","01000100","44"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",10
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
scripts/tesregs.txt
View file @ 0f8328d6
00 10
02 20
04 00
05 00
06 19
07 00
08 45
09 30
0A 06
0B 00
0C 01
0D 20
34 01
35 00
36 00
37 04
38 01
39 00
3A 00
3B 04
3C 08
3D 0B
3E 0B
3F 08
40 03
41 03
42 00
43 03
44 13
45 00
48 00
49 00
4A 00
4B 00
4C 11
4D 00
4E 44
4F 00
50 00
51 00
52 11
53 00
54 44
55 00
56 00
57 00
58 00
59 00
5A 00
00 10
02 20
04 00
05 00
06 19
07 00
08 45
09 30
0A 06
0B 00
0C 01
0D 20
34 01
35 00
36 00
37 04
38 01
39 00
3A 00
3B 04
3C 08
3D 0B
3E 0B
3F 08
40 03
41 03
42 00
43 03
44 13
45 00
48 00
49 00
4A 00
4B 00
4C 11
4D 00
4E 44
4F 00
50 00
51 00
52 11
53 00
54 44
55 00
56 00
57 00
58 00
59 00
5A 00
scripts/ucfgen.py 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
scripts/wbgen2 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
scripts/wbscript.sh 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/ad9510conf3.txt
View file @ 0f8328d6
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00011001","19"
"07","00000000","00"
"08","01000101","45"
"09","00110000","30"
"0A","00000110","06"
"0B","00000000","00"
"0C","00000001","01"
"0D","00100000","20"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001000","08"
"3D","00001011","0B"
"3E","00001011","0B"
"3F","00001000","08"
"40","00000011","03"
"41","00000011","03"
"42","00000000","00"
"43","00000011","03"
"44","00010011","13"
"45","00000000","00"
"48","00000000","00"
"49","00000000","00"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","01000100","44"
"4F","00000000","00"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","01000100","44"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",10
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00011001","19"
"07","00000000","00"
"08","01000101","45"
"09","00110000","30"
"0A","00000110","06"
"0B","00000000","00"
"0C","00000001","01"
"0D","00100000","20"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001000","08"
"3D","00001011","0B"
"3E","00001011","0B"
"3F","00001000","08"
"40","00000011","03"
"41","00000011","03"
"42","00000000","00"
"43","00000011","03"
"44","00010011","13"
"45","00000000","00"
"48","00000000","00"
"49","00000000","00"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","01000100","44"
"4F","00000000","00"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","01000100","44"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",10
"CLKInp1:",10
"CLKInp2:",500
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
software/fmc-adc-100m14b4cha-sw/spec-sw deleted 100644 → 0
View file @ 40a16639
../spec-sw/
\ No newline at end of file
software/fmc-adc-100m14b4cha-sw/spec-sw 0 → 120000
View file @ 0f8328d6
../spec-sw/
\ No newline at end of file
software/fmc-adc-100m14b4cha-sw/tools/fau-config-if 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/fmc-bus/sdb-lib/check-endian 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/fmc-bus/tools/example-fru-generator-loop 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/fmc-bus/tools/fru-generator 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/fmc-bus/tools/libipmi/fmc_eeprom.py 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
fpga-config-space @ 279d8071
Subproject commit 279d8071b6d083825c608f1b16c9d90c349f2b6a
software/load.sh 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/pll_regs.py 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/regs/rf-demo-9516-500m.stp
View file @ 0f8328d6
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00001100","0C"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000110","46"
"0141","01000110","46"
"0142","01000110","46"
"0143","01000110","46"
"0190","00000000","00"
"0191","10000000","80"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00010001","11"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00010001","11"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",1500
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00001100","0C"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000110","46"
"0141","01000110","46"
"0142","01000110","46"
"0143","01000110","46"
"0190","00000000","00"
"0191","10000000","80"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00010001","11"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00010001","11"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",1500
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
software/regs/rf-demo-9516-overclocked.stp
View file @ 0f8328d6
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00010000","10"
"0014","00011000","18"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000001","01"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000010","42"
"0141","01010010","52"
"0142","01000010","42"
"0143","01000010","42"
"0190","00000000","00"
"0191","00000000","00"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00110011","33"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00110011","33"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000000","00"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",2000
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00010000","10"
"0014","00011000","18"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000001","01"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000010","42"
"0141","01010010","52"
"0142","01000010","42"
"0143","01000010","42"
"0190","00000000","00"
"0191","00000000","00"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00110011","33"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00110011","33"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000000","00"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",2000
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
software/regs/rf-demo-9516.stp
View file @ 0f8328d6
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00001100","0C"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000001","01"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000010","42"
"0141","01000011","43"
"0142","01000010","42"
"0143","01000011","43"
"0190","00010000","10"
"0191","00000000","00"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00100010","22"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00100010","22"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000000","00"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",1500
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00001100","0C"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000001","01"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000010","42"
"0141","01000011","43"
"0142","01000010","42"
"0143","01000011","43"
"0190","00010000","10"
"0191","00000000","00"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00100010","22"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00100010","22"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000000","00"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",1500
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
software/regs/rf-demo-9516newdiv.stp
View file @ 0f8328d6
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00001100","0C"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000110","46"
"0141","01000110","46"
"0142","01000110","46"
"0143","01000110","46"
"0190","00000000","00"
"0191","00000000","00"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00010001","11"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00010001","11"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",1500
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000101","05"
"0012","00000000","00"
"0013","00001100","0C"
"0014","00010010","12"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001010","0A"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001010","0A"
"0140","01000110","46"
"0141","01000110","46"
"0142","01000110","46"
"0143","01000110","46"
"0190","00000000","00"
"0191","00000000","00"
"0192","00000000","00"
"0193","10111011","BB"
"0194","00000000","00"
"0195","00000000","00"
"0196","00000000","00"
"0197","00000000","00"
"0198","00000000","00"
"0199","00010001","11"
"019A","00000000","00"
"019B","00010001","11"
"019C","00100000","20"
"019D","00000000","00"
"019E","00010001","11"
"019F","00000000","00"
"01A0","00010001","11"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000001","01"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",25
"REF 2:",30.72
"VCO:",1500
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
software/spec-sw/check-fmc-bus 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/spec-sw/fmc-bus/sdb-lib/check-endian 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/spec-sw/fmc-bus/tools/example-fru-generator-loop 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/spec-sw/fmc-bus/tools/fru-generator 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/spec-sw/fmc-bus/tools/libipmi/fmc_eeprom.py 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
software/speclib/Makefile
View file @ 0f8328d6
CFLAGS = -ggdb -Wall
LDFLAGS = -L. -lspec
LIB = libspec.a
LIBOBJ = speclib.o loader-ll.o
PROGS = spec-cl spec-fwloader spec-vuart # specmem
all: $(LIB) $(PROGS)
$(PROGS): $(LIB)
$(LIB): $(LIBOBJ)
ar r $@ $^
loader-ll.o: ../kernel/loader-ll.c
${CC} -c $^ -I .
clean:
CFLAGS = -ggdb -Wall
LDFLAGS = -L. -lspec
LIB = libspec.a
LIBOBJ = speclib.o loader-ll.o
PROGS = spec-cl spec-fwloader spec-vuart # specmem
all: $(LIB) $(PROGS)
$(PROGS): $(LIB)
$(LIB): $(LIBOBJ)
ar r $@ $^
loader-ll.o: ../kernel/loader-ll.c
${CC} -c $^ -I .
clean:
rm -f *.o $(LIB) $(PROGS) *~
\ No newline at end of file
software/wrc-test.bin 100644 → 100755
View file @ 0f8328d6
File mode changed from 100644 to 100755
wrpc-sw @ 5ab76f6e
Subproject commit 5ab76f6edec6b1b954efc27002108e77a9d421b6
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